Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

Abstract: A semiconductor fabrication facility is provided. The semiconductor fabrication facility includes a processing tool and a transmission assembly. The transmission assembly is connected to the processing tool and comprises a number of transmission lines used to supply electric power or a fluid to the processing tool or remove the fluid or an exhaust gas from the processing tool. The transmission lines includes a first transmission line and a second transmission line. The first transmission line has a first temperature and the second transmission line has a second temperature. The second temperature is higher than the first temperature. The first transmission line and the second transmission line are arranged such that a thermal energy of the second transmission line is able to be transmitted to the first transmission line to change the first temperature of the first transmission line.

Abstract: A substrate processing apparatus includes: at least one processing part for etching a polysilicon film or an amorphous silicon film formed on a substrate using an alkaline chemical liquid; a reservoir configured to recover and store the chemical liquid used in the at least one processing part; processing lines configured to supply the chemical liquid stored in the reservoir to the at least one processing part; a circulation line configured to take out the chemical liquid from the reservoir and to return the same to the reservoir; and a first gas supply line connected to the circulation line and configured to supply an inert gas to the circulation line. The circulation line includes an ejection port configured to eject a mixed fluid of the inert gas supplied by the first gas supply line and the chemical liquid taken out from the reservoir into the chemical liquid stored in the reservoir.

Abstract: A laser processing apparatus includes an energy distribution correcting unit that forms skirt parts of a Gaussian distribution of an energy distribution in a Y-axis direction regarding a laser beam emitted from a laser oscillator into a perpendicular distribution, an imaging lens group composed of two or more lenses that form an image of the beam shape of the laser beam for which the energy distribution has been corrected by the energy distribution correcting unit on the upper surface of the workpiece, and one cylindrical lens that adjusts the energy density in an X-axis direction regarding the laser beam for which the energy distribution has been corrected by the energy distribution correcting unit.

Abstract: The present invention discloses a method and apparatus to correct surface non-uniformities between a donor substrate and a system substrate using a bonding tool. The bonding tool has multiple segments with internal structure to facilitate the objective. In particular, arc shaped guideways and resulting movements exemplify the method.

Abstract: Embodiments of the present disclosure generally relate to a susceptor for thermal processing of semiconductor substrates. In one embodiment, the susceptor includes an inner region having a pattern formed in a top surface thereof, the pattern including a plurality of substrate support features separated by a plurality of venting channels. The susceptor includes a rim surrounding and coupled to the inner region, wherein the inner region is recessed relative to the rim to form a recessed pocket configured to receive a substrate. The susceptor includes a plurality of bumps extending radially inward from an inner diameter of the rim, the plurality of bumps configured to contact an outer edge of a substrate supported by the plurality of substrate support features for positioning the substrate within the recessed pocket.

Abstract: A semiconductor device manufacturing system and a method for manufacturing semiconductor device are provided. The semiconductor device manufacturing system includes a conditioner connected to a semiconductor device manufacturing apparatus, a data collector connected to the conditioner and a processor connected to the data collector. The conditioner is configured to control a temperature and a humidity of an air and deliver the air to the semiconductor device manufacturing apparatus. The data collector is configured to collect data from the conditioner. The processor is configured to receive the data transferred from the data collector.

Abstract: A method for correcting misregistration measurements of a semiconductor wafer for errors therein arising from tilt of the wafer including measuring, for at least one location on a wafer, a difference between a Tool Induced Shift (TIS) of a metrology device in a first illumination arrangement with respect to the wafer wherein a surface of the wafer is generally orthogonally illuminated by an illumination source of the metrology device and a TIS of the metrology device in a second illumination arrangement with respect to the wafer, wherein the surface is obliquely illuminated by the illumination source, and correcting a misregistration measurement measured by the metrology device at the at least one location for errors therein arising from tilt of the wafer at the location by subtracting from the misregistration measurement a weighted value of the difference between the TIS in the first and second illumination arrangements.

Abstract: According to one aspect of the present disclosure, a transfer device has a first holding part configured to contact an edge part of a substrate when holding the substrate, and a second holding part formed with an elastic member and configured to contact only a back surface of the substrate when holding the substrate.

Abstract: A substrate processing apparatus includes: a stage including an electrostatic chuck configured to attract a substrate; a heater configured to heat the stage; a heating drive part configured to supply power to the heater so that a temperature of the stage becomes a target value; and a detector configured to detect an abnormality in attraction of the substrate by the electrostatic chuck, wherein the detector is further configured to detect the abnormality based on fluctuation of the power supplied to the heater, the fluctuation being generated by the attraction of the substrate by the electrostatic chuck.

Abstract: A method includes detecting a location of a particle on a bottom surface of an electrostatic chuck; moving a platform to a position under the bottom surface of the electrostatic chuck and right under the particle; and rotating the platform about a center of the platform to remove the particle from the bottom surface of the electrostatic chuck.

Abstract: An insulating substrate has a sample holding surface. A support is bonded to the insulating substrate. A first through-hole in the insulating substrate and a second through-hole in the support are continuous with each other to serve as a gas inlet. A porous member is located in the second through-hole. The second through-hole has, at its opening adjacent to the insulating substrate (opening adjacent to the substrate), a larger diameter than the first through-hole. The opening of the second through-hole and an electrostatic attraction electrode are at different positions in a direction parallel to the sample holding surface. The electrostatic attraction electrode and the second through-hole avoid overlapping each other as viewed from above.

Abstract: Exemplary substrate processing systems may include a transfer region housing defining a transfer region fluidly coupled with a plurality of processing regions. A sidewall of the transfer region housing may define a sealable access for providing and receiving substrates. The systems may include a plurality of substrate supports disposed within the transfer region. The systems may also include a transfer apparatus having a central hub including a first shaft and a second shaft counter-rotatable with the first shaft. The transfer apparatus may include an eccentric hub extending at least partially through the central hub, and which is radially offset from a central axis of the central hub. The transfer apparatus may also include an end effector coupled with the eccentric hub. The end effector may include a plurality of arms having a number of arms equal to the number of substrate supports of the plurality of substrate supports.

Abstract: The present inventive concept relates to a substrate processing apparatus including a supporting part for supporting a substrate; a disk supporting a plurality of the supporting parts; a lid disposed on the disk; and a first protrusion portion coupled to the disk to protrude in an upward direction from the disk to the lid in a center region disposed inward from the supporting parts and a gap region disposed between the supporting parts.

Abstract: The present invention relates to a substrate support assembly for a substrate treatment apparatus, including: a chuck base supporting the substrate to be treated, disposed rotatable around a rotation axis, and having an installation accommodation portion formed near the outer peripheral surface thereof in a circumferential direction thereof and a receiving recess formed open on the top thereof at the inside surrounded by the installation accommodation portion; chuck pins disposed on the top of the installation accommodation portion of the chuck base and movable along directions away from and approaching the substrate; a mechanism unit disposed in the installation accommodation portion and connected to the chuck pins to move the chuck pins; a driving unit for transmitting power to the mechanism unit; and an ultrasonic cleaning unit disposed in the receiving recess.

Abstract: A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via.

Abstract: A method of processing a wafer includes a groove forming step of forming grooves in the wafer to a depth equal to or larger than a thickness of chips to be produced from the wafer from a face side of the wafer along projected dicing lines, a separation initiating point forming step of positioning a focused spot of a laser at a depth in the wafer corresponding to a thickness of the chips from a reverse side of the wafer, applying the laser beam to the wafer while moving the focused spot and the wafer relatively to each other, thereby forming separation initiating points in the wafer that are parallel to the face side of the wafer and made up of modified layers and cracks, and a chip peeling step of peeling off the chips from the wafer at the separation initiating points.

Abstract: A laser processing method includes a scattered-light blocking film stacking step of stacking a scattered-light blocking film that blocks scattered light of a laser beam on an upper surface side of a wafer, a holding step of holding a lower surface side of the wafer by a chuck table, a laser processing step of forming a layer of water on the upper surface side of the wafer and irradiating a region to be processed in the wafer with the laser beam while moving the chuck table and a laser beam irradiation unit relatively, and a scattered-light blocking film removal step of removing the scattered-light blocking film from the wafer for which the laser processing step has ended.

Abstract: A method for separating dies from a semiconductor substrate having dies adjoining a first surface of the substrate includes: attaching the substrate to a carrier via the first surface; generating first modifications by introducing laser irradiation into an interior of the substrate via a second surface of the substrate, the first modifications extending between the first surface and a vertical level in the interior that is being spaced from the second surface, the first modifications laterally surrounding the dies; generating second modifications by introducing laser irradiation into the interior via the second surface, the second modifications sub-dividing the substrate into a first part between the first surface and the second modifications, and a second part between the second surface and the second modifications; separating the parts along a first separation area defined by the second modifications; and separating the dies along a second separation area defined by the first modifications.

Abstract: A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.

Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.

Abstract: A semiconductor device includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and second transistors operate under a lower gate voltage than the third and fourth transistors. The first transistor has a first active gate structure and the second transistor has a second active gate structure. The first and second active gate structures are separated by a first gate isolation structure along a first direction. The third transistor has a third active gate structure and the fourth transistor has a fourth active gate structure. The third and fourth active gate structures are separated by a second gate isolation structure along the first direction. The variation of a first distance between respective sidewalls of the first gate isolation structure is equal to the variation of a second distance between respective sidewalls of the second gate isolation structure along the first direction.

Abstract: Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Abstract: The present disclosure provides a manufacturing method and measurement method of a semiconductor structure, and a semiconductor structure, relating to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a base including multiple gate trenches; and forming a gate structure in each of the gate trenches, wherein each gate structure includes a barrier layer and a conductive layer, the barrier layer and the conductive layer are sequentially stacked, the barrier layer is in contact with a bottom wall of each of the gate trenches, and a material of the conductive layers includes polysilicon.

Abstract: A plasma treatment apparatus includes a light generator that generates light, a chamber that receives the light generated from the light generator, an optical element provided between the light generator and the chamber, a light detector that detects the light reflected in the chamber, and a controller connected to the light generator and the light detector. The chamber includes an electrostatic chuck provided in a lower portion of the chamber, an edge ring provided around the electrostatic chuck, an outer wall for sealing an inner space of the chamber, and a gas supply that injects a process gas into the chamber. The optical element branches the generated light to irradiate branched light to different regions of the chamber.

Abstract: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.

Abstract: A semiconductor structure according to the present disclosure includes a circuit region disposed over a substrate and a seal ring region disposed over the substrate and completely surrounding the circuit region. The circuit region includes first fins, second fins, n-type epitaxial structures over the first fins, and p-type epitaxial structures over the second fins. The seal ring region includes fin rings extending completely around the circuit region, epitaxial rings disposed over and extending parallel to the fin rings. All of the epitaxial rings over all of the fin rings in the seal ring region are p-type epitaxial rings.

Abstract: A method for forming a package structure is provided. The method includes bonding a package component to a substrate through a plurality of first connectors. The package component comprises a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the substrate and surrounding the first connectors. A top surface of the dam structure is lower than a bottom surface of the package component. The method further includes filling an underfill layer in a space between the dam structure and the first connectors. In addition, the method includes removing the dam structure after the underfill layer is formed.

Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, semiconductor dies over the package substrate, and an underfill element over the package substrate and surrounding the semiconductor dies. A portion of the underfill element is located between the semiconductor dies. The semiconductor die package also includes lid structures respectively attached to the top surfaces of the semiconductor dies. In plan view, each lid structure is located within the periphery of the top surface of the corresponding semiconductor die. Each lid structure is disconnected from other lid structures, and a gap is formed between adjacent lid structures and located over the portion of the underfill element.

Abstract: A method includes applying a sintering precursor material layer to each of a first surface and a second surface of a ceramic tile, and assembling a precursor assembly of a direct bonded copper (DBC) substrate by coupling a first leadframe on the sinter precursor material layer on the first surface of the ceramic tile and a second leadframe on the second surface of the sinter precursor material layer on a second surface of the ceramic tile such that the ceramic tile is disposed between the first leadframe and the second leadframe. The method further includes sinter bonding the first leadframe and the second leadframe to the ceramic tile to form a sinter bonded DBC substrate.

Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

Abstract: The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.

Abstract: A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.

Abstract: Various embodiments of the present disclosure are directed towards an apparatus comprising a semiconductor substrate. A conductive pillar is disposed in the semiconductor substrate. An isolation region is disposed in the semiconductor substrate and extends laterally around the conductive pillar. The isolation region is configured to electrically isolate the conductive pillar from a surrounding portion of the semiconductor substrate. An opening is disposed in the isolation region. A dielectric anchor is disposed in the isolation region. The dielectric anchor extends vertically through the semiconductor substrate along a side of the opening. The dielectric anchor anchors the conductive pillar to the semiconductor substrate.

Abstract: An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.

Abstract: A method includes providing a semiconductor structure having a metal gate structure (MG), gate spacers disposed on sidewalls of the MG, and a source/drain (S/D) feature disposed adjacent to the gate spacers; forming a first metal layer over the S/D feature and between the gate spacers; recessing the first metal layer to form a trench; forming a dielectric layer on sidewalls of the trench; forming a second metal layer over the first metal layer in the trench, wherein sidewalls of the second metal layer are defined by the dielectric layer; and forming a contact feature over the MG to contact the MG.

Abstract: A semiconductor process system etches thin films on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an etching process by receiving static process conditions and target thin-film data. The analysis model identifies dynamic process conditions data that, together with the static process conditions data, result in predicted remaining thin-film data that matches the target thin-film data. The process system then uses the static and dynamic process conditions data for the next etching process.

Abstract: A semiconductor memory device includes first memory layers and second memory layers arranged in alternation in a first direction. First memory layers and second memory layers include memory strings and first wirings connected to these memory strings in common. First memory layers and second memory layers include: signal amplifier circuits electrically connected to the first wirings; second wirings connected to the signal amplifier circuits; first switch transistors connected to the second wirings; third wirings electrically connected to the second wirings via the first switch transistors; and fourth wirings electrically connected to the second wirings without via the first switch transistors. The semiconductor memory device includes: first via-contact electrodes extending in the first direction and connected to the third wirings in first memory layers; and second via-contact electrodes extending in the first direction and connected to the fourth wirings in second memory layers.

Abstract: An interconnection structure, including: a first BEOL (Back-End-Of-Line) level which includes a first MLG (Multi-Layer Graphene) layer which includes at least one first line structure of MLG material; and a first isolation layer which includes an electrically isolating material and is disposed above and beside the at least one first line structure of MLG material; a second BEOL level which includes a second MLG layer (includes MLG material) disposed above the first isolation layer; a connection path electrically connecting first MLG layer to second MLG layer; and at least one via with serrated edges mitigating misalignment impacts and providing low via to line contact resistance, where the connection path includes one of the at least one via, where a width of the at least one first line structure of MLG material is greater than a diameter of the one of the at least one via, and where both MLG layers are intercalation doped.

Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.

Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of ?-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate that has a first trench that extends through a top surface of the redistribution substrate, a first semiconductor chip on the redistribution substrate, a capacitor chip on a bottom surface of the first semiconductor chip, and an under-fill layer on the bottom surface of the first semiconductor chip. The redistribution substrate includes a plurality of dielectric layers vertically stacked, a plurality of redistribution patterns in each of the dielectric layers, and a plurality of dummy redistribution patterns in the first trench. The dummy redistribution patterns vertically overlap the first semiconductor chip. An uppermost surface of the dummy redistribution pattern is located at a level higher than a level of a bottom surface of the first trench.

Abstract: A base substrate, high-k substrate layers on the base substrate with discrete decoupling capacitors embedded, high density substrate layers on the high-k substrate layers supporting wiring and wiring spacing of less than 2 up to about 10 micron width, pitch connectivity between the upper surface of the base substrate and a lower surface of the set of high density substrate layers supports less than 50 up to about 300 micron pitch, the pitch connectivity on an upper surface of the set of high density substrate layers supports less than about 150 micron pitch. A method including attaching a set of metal posts at each contact on a lower surface of a set of high density substrate layers, attaching to a handler, attaching an interconnect layer to a base substrate, and attaching the set of high density substrate layers to the base substrate while aligning each metal post with a contact.

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

Abstract: A semiconductor device has first and second current terminals and a control terminal that can be biased to form an electrically conductive path from the first current terminal to the second current terminal through a channel region is provided with a temperature-sensitive current limiting device. The current-limiting device is integrally formed from semiconductor material of the control terminal and is configured to cause a reduction in electrical current flowing through the channel region when the temperature of the device in the channel region exceeds a predetermined threshold temperature.

Abstract: A semiconductor device is configured to include: a base member of a semiconductor material which forms a thin plate shape; a front face electrode which is placed on a front surface of the base member; a rear face electrode which covers a rear surface of the base member; and a via hole which forms a hole shape provided with the front face electrode as a bottom and being open onto the rear surface, and through which the front face electrode and the rear face electrode are electrically connected to each other; wherein, at a circumferential edge portion of the base member on its side where the rear surface is located, a protrusion portion which protrudes in a thickness direction is disposed.

Abstract: A method for fabricating a semiconductor product includes forming a dielectric layer over a top level metallization layer of a semiconductor process wafer. The dielectric layer is patterned using a grayscale mask process to define a contact pad opening in the dielectric layer, thereby producing a patterned dielectric layer in which the contact pad opening is aligned to a contact pad defined in the top level metallization layer. A metal layer is deposited over the patterned dielectric layer, including within the contact pad opening. A portion of the metal layer is removed by a chemical mechanical polishing (CMP) process, with a remaining portion of the metal layer having a sloped sidewall.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second semiconductor layer, a first peripheral circuit of the array of memory cells including a first transistor in contact with a first side of the second semiconductor layer, and a second peripheral circuit of the array of NAND memory strings including a second transistor in contact with a second side of the second semiconductor layer opposite to the first side.