Abstract: In certain aspects, a memory device includes a semiconductor layer, a peripheral circuit including a peripheral transistor in contact with the semiconductor layer, an array of memory cells disposed beside the semiconductor layer and the peripheral circuit, and bit lines coupled to the memory cells. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. Each of the bit lines extends in a second direction perpendicular to the first direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.

Abstract: A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.

Abstract: Provided is a semiconductor package including: a pad substrate on which a semiconductor chip is installed; a solder formed on the pad substrate having a length same as or longer than a side of the semiconductor chip; and an intagliated groove formed on the pad substrate having a length longer than at least the side of the semiconductor chip and filled with at least a certain amount of melted solder, wherein the solder having a thickness of at least 1 ?m or above is filled in the intagliated groove to have a length of at least 3 ?m or above and an intermetallic compound layer is formed on a certain area included in an inner wall of the intagliated groove. Accordingly, movement of the semiconductor chip may be restricted so that the quality of following processes may be improved, and electrical and mechanical combination between the solder and the pad substrate may be stabled.

Abstract: An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In some embodiments, a method of manufacture includes a face-to-face process in which a first GPU chiplet and a second GPU chiplet are bonded to a temporary carrier wafer. A face surface of an active bridge chiplet is bonded to a face surface of the first and second GPU chiplets before mounting the GPU chiplets to a carrier substrate. In other embodiments, a method of manufacture includes a face-to-back process in which a face surface of an active bridge chiplet is bonded to a back surface of the first and second GPU chiplets.

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.

Abstract: A semiconductor package includes a processor die, a storage module and a package substrate. The storage module includes an array of cache units and an array of memory units stacked over one another, and electrically connected to the processor die, wherein the array of cache units is configured to hold copies of data stored in the array of memory units and frequently used by the processor die. The package substrate is on which the processor die and the storage module are disposed.

Abstract: A semiconductor package includes a chip stack comprising semiconductor chips vertically stacked on a substrate in a first direction perpendicular to a top surface of the substrate, pillars between the substrate and the chip stack, an adhesive layer on a bottom surface of a lowermost semiconductor chip of the semiconductor chips, a first lower protective layer between the adhesive layer and the pillars, a second lower protective layer between the first lower protective layer and the adhesive layer, and a mold layer covering the chip stack and filling a space between the pillars. A thickness of the second lower protective layer in the first direction is greater than a thickness of the adhesive layer in the first direction.

Abstract: A structure includes core substrates attached to a first side of a redistribution structure, wherein the redistribution structure includes first conductive features and first dielectric layers, wherein each core substrate includes conductive pillars, wherein the conductive pillars of the core substrates physically and electrically contact first conductive features; an encapsulant extending over the first side of the redistribution structure, wherein the encapsulant extends along sidewalls of each core substrate; and an integrated device package connected to a second side of the redistribution structure.

Abstract: Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

Abstract: A display device and a method of manufacturing a display device are provided. A method of manufacturing a display device may include: forming a sacrificial layer on a carrier glass; forming a first substrate layer on the sacrificial layer, the first substrate layer including an organic insulation material; forming a first through-hole in the first substrate layer, the first through-hole passing through the first substrate layer; forming a wiring on an upper surface of the first substrate layer, the wiring extending into the first through-hole; sequentially forming a circuit layer, an emission layer, and an encapsulation layer on the wiring; separating the sacrificial layer and the carrier glass from the first substrate layer by irradiating the sacrificial layer with a laser; and attaching a driving element on a lower surface of the first substrate layer, the driving element being electrically connected to the wiring through the first through-hole.

Abstract: An anisotropic conductive film in which conductive particles are dispersed in a resin includes a first region having a first pattern in which the conductive particles are discretely arranged, and a second region having a first shape by aggregating the conductive particles. Further, a display device includes a substrate provided with a plurality of electrodes arranged in a first pattern, the anisotropic conductive film, and a plurality of light emitting diodes. The plurality of light emitting diodes is electrically connected to the plurality of electrodes through the conductive particles in the first region.

Abstract: A micro-light-emitting diode (LED) display includes a number of micro-LED pixel elements and multiple optical sensors integrated with the micro-LED pixel elements. A transparent conductor layer is disposed over the micro-LED pixel elements and optical sensors.

Abstract: A display device and a method of fabricating a display device. The display device includes a substrate including an emission area and a subarea adjacent to the emission area, a bank disposed in the emission area of the substrate, a height difference compensation pattern disposed in the subarea of the substrate, a first electrode and a second electrode that are disposed on the bank, the first electrode and the second electrode being spaced apart from each other, and a light-emitting element disposed in the emission area, between the first electrode and the second electrode.

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.

Abstract: A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.

Abstract: An integrated circuit includes a driver cell and at least one transmission cell. The driver cell includes a first active area and a second active area, and a first conductive line coupled to the first active area and the second active area on a back side of the integrated circuit. The at least one transmission cell having a second cell height includes a third active area and a fourth active area, a second conductive line coupled to the third active area and the fourth active area on the back side of the integrated circuit, and a conductor coupled to the third active area and the fourth active area. The integrated circuit further includes a third conductive line coupled between the first conductive line and the second conductive line on the back side to transmit a signal between the driver cell and the at least one transmission cell.

Abstract: A semiconductor device comprising first and second unit cells, the first unit cell comprising a first fin pattern extending in a first direction, a first gate pattern extending in a second direction, and a first contact disposed on a side of the first gate pattern contacting the first fin pattern, the second unit cell comprising a second fin pattern extending in the first direction, a second gate pattern extending in the second direction, and a second contact disposed on a side of the second gate pattern contacting the second fin pattern, wherein the first and second gate patterns are spaced apart and lie on a first straight line extending in the second direction, the first and second contacts are spaced apart and lie on a second straight line extending in the second direction, and a first middle contact is disposed on and connects the first and second contacts.

Abstract: Semiconductor devices and method of forming the same are provided. In one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes two first source/drain features and a first number of nanostructures that are stacked vertically one over another and extend lengthwise between the two first source/drain features. The second transistor includes two second source/drain features and a second number of nanostructures that are stacked vertically one over another and extend lengthwise between the two second source/drain features.

Abstract: A method of manufacturing a gate structure includes at least the following steps. A gate dielectric layer is formed. A work function layer is deposited on the gate dielectric layer. A barrier layer is formed on the work function layer. A metal layer is deposited on the barrier layer to introduce fluorine atoms into the barrier layer. The barrier layer is formed by at least the following steps. A first TiN layer is formed on the work function layer. A top portion of the first TiN layer is converted into a trapping layer, and the trapping layer includes silicon atoms or aluminum atoms. A second TiN layer is formed on the trapping layer.

Abstract: A semiconductor device includes: a first active pattern extended in a first direction on a substrate; a second active pattern extended in the first direction and spaced apart from the first active pattern in a second direction on the substrate; a field insulating layer between the first active pattern and the second active pattern on the substrate; a first gate electrode on the first active pattern; a second gate electrode on the second active pattern; and a gate isolation structure separating the first gate electrode and the second gate electrode from each other on the field insulating layer, wherein a width of the gate isolation structure in the second direction varies in a downward direction from the upper isolation pattern.

Abstract: A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.

Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip comprises a semiconductor substrate. A semiconductor layer is disposed over the semiconductor substrate. An insulating structure is buried between the semiconductor substrate and the semiconductor layer. The insulating structure has a first region and a second region. The insulating structure has a first thickness in the first region of the insulating structure, and the insulating structure has a second thickness different than the first thickness in the second region of the insulating structure.

Abstract: Provided is a display device.

Abstract: Provided is an array substrate, including: a display region including signal lines and a peripheral region including a bonding region; wherein the bonding region includes at least one row of signal line input terminals disposed on a first substrate, the signal line input terminals being electrically connected to the signal lines; and the signal line input terminal includes an etched conductive layer, at least the etched conductive layers in two adjacent signal line input terminals disposed in a same row being disposed on different layers.

Abstract: A wiring structure includes a structure body including a pattern, a first conductive layer above the structure body, the first conductive layer having a shape, the shape crossing an edge of a pattern of the structure body and reflecting a step of the edge of the pattern of the structure body, a first insulating layer above the first conductive layer, the first insulating layer having a first opening overlapping the edge of the pattern of the structure body in a plane view, and r is arranged with a second opening in a region overlapping the semiconductor layer in a plane view, a second conductive layer in the first opening, the second conductive layer being connected to the first conductive layer.

Abstract: A display device includes a pixel component including scan lines, data lines, and pixels electrically connected to the scan lines and the data lines, and defining pixel columns and pixel rows, a data driver disposed on a side of the pixel component, and a scan driver disposed on the side of the pixel component. The pixel component includes sub-scan lines, and dummy lines. Each scan line may be electrically connected to the sub-scan lines by contacts. The contacts are divided into contact groups having a same arrangement. The pixel component is divided into pixel blocks corresponding to the contact groups. Each pixel block includes first and second area divided by contact group. The first area is closer to the scan driver than the second area. The pixel component further includes supplementary power lines spaced apart from the respective sub-scan lines.

Abstract: In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied include a plurality of first signal lines to which the drive signal is supplied. The first signal line is connected to a driving driver, and is formed in an edge region positioned between an end portion of a substrate and a pixel region and in the pixel region. The first signal line is formed to pass through a first wiring formed in a first layer from a second wiring formed in a second layer in the edge region.

Abstract: Provided is a display device with extremely high resolution, a display device with higher display quality, a display device with improved viewing angle characteristics, or a flexible display device. Same-color subpixels are arranged in a zigzag pattern in a predetermined direction. In other words, when attention is paid to a subpixel, another two subpixels exhibiting the same color as the subpixel are preferably located upper right and lower right or upper left and lower left. Each pixel includes three subpixels arranged in an L shape. In addition, two pixels are combined so that pixel units including subpixel are arranged in matrix of 3×2.

Abstract: Provided are a display panel and a display device. The display panel includes a base substrate; a first transistor including a first active layer including silicon, a first gate, a first source and a first drain; a second transistor including a second active layer including an oxide semiconductor, a second gate located on a side of the second active layer facing away from the base substrate, a second source and a second drain; a first insulating layer including an inorganic material; and a planarization layer including an organic material. The first insulating layer includes a first insulating sublayer and a second insulating sublayer. The second insulating sublayer is located on a side of the first insulating sublayer facing away from the base substrate, and a compactness of the second insulating sublayer is greater than a compactness of the first insulating sublayer.

Abstract: An array substrate includes a thin film transistor including a drain electrode, a first insulation film included in an upper layer than the drain electrode and including a contact hole overlapping the drain electrode, a pixel electrode included in an upper layer than the first insulation film and overlaps the drain electrode at least inside the contact hole and is connected to the drain electrode, a second insulation film included in an upper layer than the pixel electrode and overlaps the pixel electrode inside the contact hole and extends outside the contact hole, a conductive portion included in an upper layer than the second insulation film and overlaps the pixel electrode at least inside the contact hole, and an insulation portion included in an upper layer than the pixel electrode and in a lower layer than the conductive portion and overlaps the pixel electrode inside the contact hole.

Abstract: An array substrate, a preparation method thereof and a display apparatus are provided. The array substrate includes a plurality of pixel units distributed in a matrix and a plurality of scan lines and a plurality of data lines. Each pixel unit includes a display region and a device region. The display region includes a pixel electrode and a common electrode. The pixel electrode at least partially overlaps with the common electrode to form a first storage capacitor. The device region includes a drive transistor. The gate extends in a direction towards the display region to form a first extension portion; the drain extends in the direction towards the display region to form a second extension portion. The second extension portion is electrically connected to the pixel electrode. The first extension portion and the second extension portion overlap to form a second storage capacitor.

Abstract: A photomask according to an exemplary embodiment includes: a mask substrate; and a first test pattern and a second test pattern disposed along a first edge of the mask substrate, wherein the first test pattern has a first outer shape and a first inner shape, the second test pattern has a second outer shape, and the second outer shape of the second test pattern is larger than the first inner shape of the first test pattern and smaller than the first outer shape of the first test pattern.

Abstract: Disclosed is an image sensor comprising a semiconductor substrate that includes first through fourth pixel regions, each including first through fourth photoelectric conversion sections, and a pixel separation structure disposed in the semiconductor substrate and separating the first through fourth pixel regions from each other. The second pixel region is spaced apart in a first direction from the first pixel region. The fourth pixel region is spaced apart in a second direction from the first pixel region. The second direction intersects the first direction. The semiconductor substrate includes first impurity sections disposed on corresponding central portions of the first through fourth pixel regions, and a second impurity section disposed between the second and fourth pixel regions. Impurities doped in the first impurity sections have a conductivity type different from that of impurities doped in the second impurity section.

Abstract: This application belongs to the technical field of semiconductor devices, and relates to a pixel circuit, a control method, and an image sensor, including: at least two pixel units arranged in an array, wherein transmission transistors of at least two pixels of at least one pixel unit are connected to a corresponding first group of transmission control lines, and a transmission transistor of one other pixel is connected to a corresponding second group of transmission control lines. Therefore, the pixel circuit, the control method and the image sensor provided in the present application can control the density of phase focus of the image sensor by controlling the first group of transmission control lines and the second group of transmission control lines without changing the structure of the pixel, the structure is simple, and the optical performance is good.

Abstract: An image sensor includes: a semiconductor substrate including a first surface and a second surface opposite to each other; a buried transfer gate electrode arranged in a transfer gate trench extending from the first surface of the semiconductor substrate into the semiconductor substrate, wherein the buried transfer gate electrode has an upper surface arranged at a level lower than that of the first surface of the semiconductor substrate with respect to the second surface of the semiconductor substrate; and a transfer gate spacer arranged on an upper sidewall of the transfer gate trench and on the buried transfer gate electrode.

Abstract: Image sensors are provided. The image sensors may include a plurality of unit pixels and a color filter array on the plurality of unit pixels. The color filter array may include a color filter unit including four color filters that are arranged in a two-by-two array, and the color filter unit may include two yellow color filters, a cyan color filter, and one of a red color filter or a green color filter.

Abstract: A device may include a multispectral filter array disposed on the substrate. The multispectral filter array may include a first metal mirror disposed on the substrate. The multispectral filter may include a spacer disposed on the first metal mirror. The spacer may include a set of layers. The spacer may include a second metal mirror disposed on the spacer. The second metal mirror may be aligned with two or more sensor elements of a set of sensor elements.

Abstract: An electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. By using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. As a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. Additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.

Abstract: Some aspects of the present disclosure relate to a method. In the method, a semiconductor substrate is received. A photodetector is formed in the semiconductor substrate. An interconnect structure is formed over the photodetector and over a frontside of the semiconductor substrate. A backside of the semiconductor substrate is thinned, the backside being furthest from the interconnect structure. A ring-shaped structure is formed so as to extend into the thinned backside of the semiconductor substrate to laterally surround the photodetector. A series of trench structures are formed to extend into the thinned backside of the semiconductor substrate. The series of trench structures are laterally surrounded by the ring-shaped structure and extend into the photodetector.

Abstract: A semiconductor device capable of realizing a capacitative element of which a capacitance value has low bias dependence and of which capacitance density is high without lowering operating voltage is provided. The semiconductor device includes: a semiconductor substrate; a first capacitative element stacked on the semiconductor substrate; and a second capacitative element which is stacked on an opposite side to a side of the semiconductor substrate of the first capacitative element and of which a capacitance value has bias characteristics being opposite to bias characteristics of a capacitance value of the first capacitative element, wherein the first capacitative element and the second capacitative element are connected in parallel.

Abstract: An imaging element has at least a photoelectric conversion section, a first transistor TR1, and a second transistor TR2, the photoelectric conversion section includes a photoelectric conversion layer 13, a first electrode 11, and a second electrode 12, the imaging element further has a first photoelectric conversion layer extension section 13A, a third electrode 51, and a fourth electrode 51C, the first transistor TR1 includes the second electrode 12 that functions as one source/drain section, the third electrode that functions as a gate section 51, and the first photoelectric conversion layer extension section 13A that functions as the other source/drain section, and the first transistor TR1 (TRrst) is provided adjacent to the photoelectric conversion section.

Abstract: The present disclosure discloses a flat panel detector, a driving method, a driving device and a flat panel detection device. The flat panel detector includes: a base substrate, and a plurality of detection units located on the base substrate; each of the detection units includes a photodiode and a detection transistor; the flat panel detector further includes: a compensation semiconductor material layer including a plurality of compensation structures mutually spaced; each detection transistor is correspondingly provided with a compensation structure, and the compensation structure is located between a gate and a gate insulating layer of the corresponding detection transistor.

Abstract: The present disclosure relates to an imaging device and an electronic device that make it possible to obtain a better pixel signal. A photoelectric conversion part that converts received light into a charge; a holding part that holds a charge transferred from the photoelectric conversion part; and a light shielding part that shields light between the photoelectric conversion part and the holding part are provided. The photoelectric conversion part, the holding part, and the light shielding part are formed in a semiconductor substrate. The light shielding part of a transfer region that transfers the charge from the photoelectric conversion part to the holding part is formed as a non-penetrating light shielding part that does not penetrate the semiconductor substrate. The light shielding part other than the transfer region is formed as a penetrating light shielding part that penetrates the semiconductor substrate. The present technology is applicable to an imaging device.

Abstract: A display device comprises a first substrate, a first power bottom line on the first substrate, a second substrate on the first power bottom line, the second substrate having a first power connection hole to expose the first power bottom line, and a pixel driving unit including a plurality of switching elements on the second substrate.

Abstract: A light emitting display apparatus includes a substrate including a plurality of pixels each including an emission area; a light extraction pattern including a plurality of concave portions in the emission area; and a light emitting portion over the light extraction pattern, wherein at least one of the plurality of concave portions has a curvature of 0.217 ?m?1 to 0.311 ?m?1.

Abstract: A display device comprises a display area, a non-display area surrounding the display area, pixels disposed in the display area of the substrate, each of the pixels including a first electrode, a second electrode, and light-emitting elements electrically connected to the first electrode and the second electrode, and a first voltage wiring disposed in the display area and the non-display area, the first voltage wiring electrically connected to at least some of the pixels. The first voltage wiring includes a first separation wiring disposed in the non-display area, and a second separation wiring disposed in the non-display area and spaced apart from the first separation wiring.