Abstract: A SiC single crystal substrate of an embodiment is a SiC single crystal substrate wherein the main plane of the SiC single crystal substrate has an off angle of 0° to 6° to the (0001) plane in the <11-20> direction and an off angle of 0° to 0.5° to the (0001) plane in the <1-100> direction, and includes non-MP defects wherein when the Si surface is etched in molten KOH at 500° C. for 15 minutes, the non-MP defects that appear by etching are hexagonal and have no core, the area of the observed etch pit of the non-MP defect is more than 10% larger than that of the observed etch pit of the TSD and is less than 110% of that of the observed etch pit of the micropipe (MP), and a transmission X-ray topography image of the non-MP defect is distinguishable from the transmission X-ray topography image of the micropipe (MP), wherein etch pits, which are identified as the non-MP defects, appear in the range of 0.1/cm2 to 50/cm2.

Abstract: A crystal growth method of the present disclosure includes: preparing a crystal growth-derived-layer forming substrate including (a) a substrate having a surface layer, (b) a mask pattern which is formed on the surface layer and which includes a plurality of strip bodies, and (c) a plurality of crystal growth-derived layers which are formed between and on the plurality of stripe bodies so as to have gaps therebetween above the plurality of strip bodies and which differ in lattice constant from the substrate having the surface layer; and growing semiconductor layers on the plurality of crystal growth-derived layers. The semiconductor layers are respectively grown on the plurality of crystal growth-derived layers formed so as to be separated from each other, and semiconductor layers on two adjacent ones of the plurality of crystal growth-derived layers are separated from each other.

Abstract: A nitride semiconductor substrate that is constituted by a single crystal of a group III nitride semiconductor and includes a main surface for which the closest low index crystal plane is a (0001) plane includes an inclined interface growth region that has grown with inclined interfaces other than the (0001) plane serving as growth surfaces. A ratio of an area occupied by the inclined interface growth region in the main surface is 80% or more. When a dislocation density is determined based on a dark spot density by observing the main surface in a field of view that is 250 ?m square using a multiphoton excitation microscope, the main surface does not include a region that has a dislocation density higher than 3×106 cm?2, and the main surface includes dislocation-free regions that are 50 ?m square and do not overlap each other, at a density of 100 regions/cm2 or more.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

Abstract: In at least one embodiment, a loudspeaker assembly is provided. The loudspeaker assembly includes a supporting ring, a flexible surround, a voice coil, a dome, and a bearing ring. The flexible surround includes a first end being attached to the supporting ring and a second end positioned opposite to the first end. The voice coil is positioned about the flexible surround. The dome is positioned about the voice coil and the second end of the flexible surround. The bearing ring is attached to the voice coil and separates the flexible surround from the dome.

Abstract: An electronic device may include conductive structures such as conductive housing structures. A high-brightness, visible-light-reflecting coating may be formed on the conductive structures. The coating may have adhesion and transition layers and an uppermost coloring layer on the adhesion and transition layers. At least the uppermost coloring layer may be deposited using a high impulse magnetron sputtering (HiPIMS) process. The uppermost coloring layer may include a TiCrN film, a TiCrCN film, a TiCN film, or a metal nitride film that contains Ti, Zr, Hf, or Cr. The coating may exhibit a high-brightness gold color.

Abstract: Provided are a method for etching and growing a semiconductor substrate in the same device system, and a device therefor. The method for manufacturing a semiconductor substrate includes a first heating step of heating a heat treatment space which contains a semiconductor substrate and a transmission/reception body that transports atoms between the semiconductor substrate and the transmission/reception body such that a temperature gradient is formed between the semiconductor substrate and the transmission/reception body, and a second heating step of heating the same with the temperature gradient being vertically inverted.

Abstract: There is provided a nitride semiconductor substrate having a diameter of 2 inches or more and having a main surface whose closest low index crystal plane is a (0001) plane, wherein X-ray locking curve measurement for (0002) plane diffraction, which is performed to the main surface by irradiating with (Cu) K?1 X-rays through a two-crystal monochromator of Ge (220) plane and a slit, reveals that full width at half maximum FWHMb is 32 arcsec or less, and FWHMa?FWHMb obtained by subtracting FWHMb from FWHMa is 30% or less of FWHMa, wherein FWHMa is full width at half maximum of the (0002) plane diffraction when a slit width in ? direction is 1 mm, and FWHMb is full width at half maximum of the (0002) plane diffraction when a slit width in ? direction is 0.1 mm.

Abstract: A method for processing a wide band gap semiconductor wafer includes: depositing a support layer including semiconductor material at a back side of a wide band gap semiconductor wafer, the wide band gap semiconductor wafer having a band gap larger than the band gap of silicon; depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer; and splitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer comprising at least a part of the epitaxial layer, and a remaining wafer comprising the support layer.

Abstract: Provided are a method of cleaning a group III nitride single crystal substrate which enables the roughness of a nitrogen-polar face of the group III nitride single crystal substrate to be suppressed to remove foreign substances, and a method of producing a group III nitride single crystal substrate. The method of cleaning a group III nitride single crystal substrate having a group III element-polar face, and the nitrogen-polar face opposite the group III element-polar face includes: cleaning the nitrogen-polar face with a detergent including a fluoroorganic compound.

Abstract: A silicon carbide single crystal contains a heavy metal element having a specific gravity higher than a specific gravity of iron. An addition density of the heavy metal element at least in an outer peripheral portion of the silicon carbide single crystal is set to 1×1015 cm?3 or more.

Abstract: An acoustic wave device includes a piezoelectric substrate and an IDT electrode on the piezoelectric substrate. The IDT electrode includes first and second electrode fingers. When the propagation direction of acoustic waves is a first direction and the direction orthogonal or substantially orthogonal to the first direction is a second direction, an intersecting region of the IDT electrode includes a central region located toward the middle in the second direction and first and second edge regions on both sides in the second direction of the central region. The first and second electrode fingers include epitaxially grown oriented films in the central region and portions that do not include the oriented films in the first and second edge regions.

Abstract: A method of manufacturing a silicon carbide ingot, includes a preparing operation of adjusting internal space of a reactor in which silicon carbide raw materials and a seed crystal are disposed to have a high vacuum atmosphere, a proceeding operation of injecting an inert gas into the internal space, heating the internal space by moving a heater surrounding the reactor to induce the silicon carbide raw materials to sublimate, and growing the silicon carbide ingot on the seed crystal, and a cooling operation of cooling the temperature of the internal space to room temperature. The moving of the heater has a relative position which becomes more distant at a rate of 0.1 mm/hr to 0.48 mm/hr based on the seed crystal.

Abstract: A processing method includes: disposing a workpiece in a processing container of a processing apparatus, and maintaining an inside of the processing container in a vacuum state; providing a cluster nozzle in the processing container; supplying a cluster generating gas to the cluster nozzle and adiabatically expanding the cluster generating gas in the cluster nozzle, thereby generating gas clusters; generating plasma in the cluster nozzle to ionize the gas clusters and injecting the ionized gas clusters onto the workpiece; supplying a reactive gas to the cluster nozzle and exposing the reactive gas to the plasma such that the reactive gas becomes monomer ions or radicals; and supplying the monomer ions or radicals to the processing container, thereby exerting a chemical reaction on a substance present on a surface of the workpiece.

Abstract: A silicon carbide single crystal manufacturing apparatus includes a crucible constituted by a crucible body and a crucible lid and a base having a crucible lid side surface supported by the lower surface of the crucible lid, and a seed crystal mounting surface on which the seed crystal is mounted and which is a surface on the opposite side of the crucible lid side surface, wherein the base is made of graphite material, the area of the seed crystal mounting surface is larger than the area of the crucible lid side surface, and the base has at least of a portion in which the cross-sectional area orthogonal to the vertical direction connecting the crucible lid side surface and the seed crystal mounting surface is gradually reduced, and a portion that is getting smaller gradually, from the surface of the seed crystal mounting surface toward the crucible lid side surface.

Abstract: A method of forming a device structure including a selectively-deposited gallium nitride layer is disclosed.

Abstract: A circuit board structure, including a circuit layer, a first dielectric layer, a first graphene layer, a first conductive via, and a first built-up circuit layer, is provided. The circuit layer includes multiple pads. The first dielectric layer is disposed on the circuit layer and has a first opening. The first opening exposes the pads. The first graphene layer is conformally disposed on the first dielectric layer and in the first opening, and has a first conductive seed layer region and a first non-conductive seed layer region. The first conductive via is disposed in the first opening. The first built-up circuit layer is disposed corresponding to the first conductive seed layer region. The first built-up circuit layer exposes the first non-conductive seed layer region and is electrically connected to the pads through the first conductive via and the first conductive seed layer region.

Abstract: In one embodiment, this hard mask for plasma etching is formed on a silicon-containing film. The hard mask is an amorphous film, and contains tungsten and silicon. The ratio of the concentration of tungsten and the concentration of silicon in the surface of the hard mask can be within the range between a ratio specifying that the concentration of tungsten is 35 at % and the concentration of silicon is 65 at % and a ratio specifying that the concentration of tungsten is 50 at % and the concentration of silicon is 50 at %.

Abstract: A process for epitaxying GaSe on a [111]-oriented silicon substrate, includes a step of selecting a [111]-oriented silicon substrate resulting from cutting a silicon bar in a miscut direction which is one of the three [11-2] crystallographic directions, the miscut angle (?) being smaller than or equal to 0.

Abstract: Systems and methods for forming semiconductor layers, including oxide-based layers, are disclosed in which a material deposition system has a rotation mechanism that rotates a substrate around a center axis of a substrate deposition plane of the substrate. A material source that supplies a material to the substrate has i) an exit aperture with an exit aperture plane and ii) a predetermined material ejection spatial distribution from the exit aperture plane. The exit aperture is positioned at an orthogonal distance, a lateral distance, and a tilt angle relative to the center axis of the substrate. The system can be configured for either i) minimum values for the orthogonal distance and the lateral distance to achieve a desired layer deposition uniformity using a set tilt angle, or ii) the tilt angle to achieve the desired layer deposition uniformity using a set orthogonal distance and a set lateral distance.

Abstract: Embodiments of the present disclosure provide a method of manufacturing an optoelectronic device epitaxial structure. The method includes forming a mask pattern on a base substrate, the mask pattern defining a plurality of growth regions on the base substrate, and the plurality of growth regions being separated from each other; and forming an optoelectronic device epitaxial structure in each of the plurality of growth regions; and removing the mask pattern.

Abstract: A crystal growth method of the present disclosure includes: preparing a substrate having a surface layer; forming a mask pattern including a plurality of strip bodies on the surface layer to separate the surface layer into segments by the plurality of strip bodies and expose part of the surface layer; and forming, on a plurality of growth regions constituted by the exposed part of the surface layer, a crystal growth-derived layer by causing a semiconductor crystal which differs in lattice constant from the substrate to grow by a vapor-phase growth process. Each of the plurality of strip bodies has side faces inclined so that a width between the side faces gradually decreases with distance from the surface layer.

Abstract: A first insulating layer is disposed on a second surface of a semiconductor substrate, and has an opening. A second insulating layer is disposed on the second surface and separated from the first insulating layer. A stack includes, in sequence on the second surface, a side n-type epitaxial layer and first and second p-type epitaxial layers that are made of a gallium-nitride-based material. The stack has an outer side wall having a portion formed of the second p-type epitaxial layer, an inner side wall extending from the second insulating layer, and a top surface. The n-type contact layer is disposed on the top surface. The source electrode portion is in contact with the n-type contact layer on the top surface, and is in contact with the second p-type epitaxial layer on the outer side wall. A gate insulating film is disposed on the inner side wall.

Abstract: A method for manufacturing a silicon epitaxial wafer includes: preparing a test silicon wafer in advance, forming the multilayer film on a surface of the test silicon wafer, and measuring a warp direction and a warp amount (Warp) W of the silicon wafer having the multilayer film formed thereon; and selecting a silicon wafer as a device formation substrate and conditions for forming an epitaxial layer which is formed on the silicon wafer as the device formation substrate in such a manner that a warp which cancels out the measured warp amount W is formed in a direction opposite to the measured warp direction, and forming the epitaxial layer on a surface of the selected silicon wafer as the device formation substrate where the multilayer film is formed under the selected conditions for forming the epitaxial layer.

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a base, a buffer layer, a mask layer and a first GaN layer. The buffer layer is disposed on the base, wherein doped regions are disposed in a portion of the surface of the buffer layer. The mask layer is disposed on the buffer layer and located on the doped regions. The first GaN layer is disposed on the buffer layer and covers the mask layer.

Abstract: A semiconductor device may include a semiconductor substrate having a front side and a back side opposite the front side, and a superlattice gettering layer on the front side of a semiconductor substrate. The superlattice gettering layer may include stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The device may further include an active semiconductor layer on the superlattice gettering layer opposite the semiconductor substrate, at least one semiconductor circuit in the active semiconductor layer, at least one metal interconnect layer on the active layer, and at least one metal through-via extending from the at least one metal interconnect layer to the back side of the semiconductor substrate. The superlattice gettering layer may further include gettered metal ions.

Abstract: A sapphire member containing sapphire as a main constituent has a main surface parallel to a c-plane of a sapphire crystal. The sapphire member includes a plurality of terrace structure layers in at least a part of the main surface. Each terrace structure layer includes a terrace surface parallel to the c-plane and a side surface in contact with an edge line of the terrace surface. When viewed in a plan in a direction perpendicular to the main surface, the part of the main surface includes a plurality of the edge lines that are curved and are not parallel to one another.

Abstract: A method of manufacturing an epitaxial wafer having an epitaxial layer on a silicon-based substrate, the method of manufacturing the epitaxial wafer including epitaxially growing a semiconductor layer on the silicon-based substrate after applying terrace processing to an outer peripheral portion of the silicon-based substrate. As a result, the method of manufacturing the epitaxial wafer having the epitaxial layer on the silicon-based substrate in which an epitaxial wafer which is completely free from cracks can be obtained, is provided.

Abstract: A semiconductor substrate, comprising a first semiconductor material, is provided and an insulating layer is formed thereon; an opening is formed in the insulating layer. Thereby, a seed surface of the substrate is exposed. The opening has sidewalls and a bottom and the bottom corresponds to the seed surface of the substrate. A cavity structure is formed above the insulating layer, including the opening and a lateral growth channel extending laterally over the substrate. A matching array is grown on the seed surface of the substrate, including at least a first semiconductor matching structure comprising a second semiconductor material and a second semiconductor matching structure comprising a third semiconductor material. The compound semiconductor structure comprising a fourth semiconductor material is grown on a seed surface of the second matching structure. The first through fourth semiconductor materials are different from each other. Corresponding semiconductor structures are also included.

Abstract: Methods are provided for fabricating semiconductor nanowires on a substrate. A nanowire template is formed on the substrate. The nanowire template defines an elongate tunnel which extends, laterally over the substrate, between an opening in the template and a seed surface. The seed surface is exposed to the tunnel and of an area up to about 2×104 nm2. The semiconductor nanowire is selectively grown, via said opening, in the template from the seed surface. The area of the seed surface is preferably such that growth of the nanowire proceeds from a single nucleation point on the seed surface. There is also provided a method for fabricating a plurality of semiconductor nanowires on a substrate and a semiconductor nanowire and substrate structure.

Abstract: The present invention provides a textured substrate for forming an epitaxial film, including a textured metal layer on at least one surface of the layer, the textured metal layer including a copper layer having a cube texture, the textured metal layer having, on a surface of the layer, palladium added in an amount of 10 to 300 ng/mm2 per unit area, the hydrogen content of the surface of the textured metal layer being 700 to 2000 ppm. This textured substrate is produced through a step of adding 10 to 300 ng/mm2 per unit area of palladium by strike plating to a surface of the copper layer having a cube texture.

Abstract: A group III nitride crystal substrate is provided, wherein, a uniform distortion at a surface layer of the crystal substrate is equal to or lower than 1.7×10?3, and wherein a plane orientation of the main surface has an inclination angle equal to or greater than ?10° and equal to or smaller than 10° in a [0001] direction with respect to a plane including a c axis of the crystal substrate. A group III nitride crystal substrate suitable for manufacturing a light emitting device with a blue shift of an emission suppressed, an epilayer-containing group III nitride crystal substrate, a semiconductor device and a method of manufacturing the same can thereby be provided.

Abstract: This disclosure provides systems, methods, and apparatus related to the growth of single crystal III-V semiconductors on amorphous substrates. In one aspect, a shape of a semiconductor structure to be formed on an amorphous substrate is defined in a resist disposed on the amorphous substrate. A boron group element is deposited over the amorphous substrate. A ceramic material is deposited on the boron group element. The resist is removed from the amorphous substrate. The ceramic material is deposited to cover the boron group element. The amorphous substrate and materials deposited thereon are heated in the presence of a gas including a nitrogen group element to grow a single crystal semiconductor structure comprising the boron group element and the nitrogen group element.

Abstract: This disclosure is directed to an improved process for making glass articles having optical coating and easy-to clean coating thereon, an apparatus for the process and a product made using the process. In particular, the disclosure is directed to a process in which the application of the optical coating and the easy-to-clean coating can be sequentially applied using a single apparatus. Using the combination of the coating apparatus and the substrate carrier described herein results in a glass article having both optical and easy-to-clean coating that have improved scratch resistance durability and optical performance, and in addition the resulting articles are “shadow free.

Abstract: A semiconductor single crystal structure may include a substrate; a defect trapping stack disposed on the substrate; and a semiconductor single crystal disposed on the defect trapping stack, and having a lattice mismatch with a crystal of the substrate, in which the defect trapping stack may include a first dielectric layer disposed on the substrate, and having at least one first opening, a second dielectric layer disposed on the first dielectric layer, and having at least one second opening, a third dielectric layer disposed on the second dielectric layer, and having at least one third opening, and a fourth dielectric layer disposed on the third dielectric layer, and having at least one fourth opening, and in which the semiconductor single crystal may extend to a region of the substrate defined in the at least one first opening through the at least one first to fourth opening.

Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing a support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the semiconductor substrate.

Abstract: A method of manufacturing an epitaxial wafer, including a silicon substrate having a surface sliced from single-crystalline silicon and a silicon epitaxial layer deposited on the surface of the silicon substrate, includes an oxygen concentration controlling heat treatment process in which a heat treatment of the epitaxial layer is performed under a non-oxidizing atmosphere after the epitaxial growth such that an oxygen concentration of the surface of the silicon epitaxial layer is set to 1.0×1017 to 12×1017 atoms/cm3 (ASTM F-121, 1979).

Abstract: A method of manufacturing an epitaxiable heat-dissipating substrate comprises the steps of (A) forming a roughened surface on a substrate made of a polycrystalline or amorphous material with a high thermal conductivity coefficient; (B) forming a flat layer on the roughened surface; and (C) forming a buffer layer on the flat layer. The flat layer reduces the surface roughness of the substrate, and then the buffer layer functions as a base for epitaxial growth, thereby being directly applicable to production of semiconductor devices which are flat and capable of isotropic epitaxial growth.

Abstract: A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiO2 having a predetermined thickness or pattern is deposited on the second surface of a semiconductor wafer having an undesirable warp or bow. The thickness or pattern of the deposited oxide layer is determined by the measured warp or bow of the semiconductor wafer. The compressive oxide layer induces an offsetting compressive force on the second surface of the semiconductor wafer to reduce the warp and bow across the major surface of the semiconductor wafer.

Abstract: A method and apparatus for removing deposition products from internal surfaces of a processing chamber, and for preventing or slowing growth of such deposition products. A halogen containing gas is provided to the chamber to etch away deposition products. A halogen scavenging gas is provided to the chamber to remove any residual halogen. The halogen scavenging gas is generally activated by exposure to electromagnetic energy, either inside the processing chamber by thermal energy, or in a remote chamber by electric field, UV, or microwave. A deposition precursor may be added to the halogen scavenging gas to form a deposition resistant film on the internal surfaces of the chamber. Additionally, or alternately, a deposition resistant film may be formed by sputtering a deposition resistant metal onto internal components of the processing chamber in a PVD process.

Abstract: A negative electrode and a lithium battery including the same, the negative electrode including nanotubes including a Group 14 metal/metalloid, disposed on a conductive substrate.

Abstract: A method for manufacturing a light-emitting diode, which includes the steps of: providing a substrate having a plurality of protruded portions on one main surface thereof wherein the protruded portion is made of a material different in type from that of the substrate and growing a first nitride-based III-V Group compound semiconductor layer on each recess portion of the substrate through a state of making a triangle in section wherein a bottom surface of the recess portion becomes a base of the triangle; laterally growing a second nitride-based III-V Group compound semiconductor layer on the substrate from the first nitride-based III-V Group compound semiconductor layer; and successively growing, on the second nitride-based III-V Group compound semiconductor layer, a third nitride-based III-V Group compound semiconductor layer of a first conduction type, an active layer, and a fourth nitride-based III-V compound semiconductor layer of a second conduction type.

Abstract: A method for producing a SiC single crystal substrate that can remove Cr impurity from the surface of a SiC single crystal that contains Cr as an impurity, is provided. This is achieved by a method for producing a SiC single crystal substrate, wherein the method includes a step of immersing a SiC single crystal substrate containing Cr as an impurity in hydrochloric acid at 50° C. to 80° C.

Abstract: To reduce warpage in at least one area of a wafer, a stress/warpage management layer (810) is formed to over-balance and change the direction of the existing warpage. For example, if the middle of the area was bulging up relative to the area's boundary, the middle of the area may become bulging downward, or vice versa. Then the stress/warpage management layer is processed to reduce the over-balancing. For example, the stress/management layer can be debonded from the wafer at selected locations, or recesses can be formed in the layer, or phase changes can be induced in the layer. In other embodiments, this layer is tantalum-aluminum that may or may not over-balance the warpage; this layer is believed to reduce warpage due to crystal-phase-dependent stresses which dynamically adjust to temperature changes so as to reduce the warpage (possibly keeping the wafer flat through thermal cycling). Other features are also provided.

Abstract: A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate.

Abstract: The invention provides highly transparent single crystalline AlN layers as device substrates for light emitting diodes in order to improve the output and operational degradation of light emitting devices. The highly transparent single crystalline AlN layers have a refractive index in the a-axis direction in the range of 2.250 to 2.400 and an absorption coefficient less than or equal to 15 cm-1 at a wavelength of 265 nm. The invention also provides a method for growing highly transparent single crystalline AlN layers, the method including the steps of maintaining the amount of Al contained in wall deposits formed in a flow channel of a reactor at a level lower than or equal to 30% of the total amount of aluminum fed into the reactor, and maintaining the wall temperature in the flow channel at less than or equal to 1200° C.

Abstract: Disclosed is a method of fabricating a single crystal colloidal monolayer on a substrate. The method includes preparing a pair of adhesive substrates, arranging powder particles between the substrates, and uniaxially rubbing one of the substrates in any one direction to allow the particles to be close-packed between the substrates, thereby forming a single crystal monolayer.

Abstract: A semiconductor light emitting device comprising a light emitting layer disposed between an n-type region and a p-type region is combined with a ceramic layer which is disposed in a path of light emitted by the light emitting layer. The ceramic layer is composed of or includes a wavelength converting material such as a phosphor. Luminescent ceramic layers according to embodiments of the invention may be more robust and less sensitive to temperature than prior art phosphor layers. In addition, luminescent ceramics may exhibit less scattering and may therefore increase the conversion efficiency over prior art phosphor layers.

Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.

Abstract: Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor.