With Pretreatment Or Preparation Of A Base (e.g., Annealing) Patents (Class 117/106)
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Publication number: 20110127581Abstract: The present invention relates to a support for the epitaxy of a layer of a material of composition AlxInyGa(1-x-y)N, where 0?x?1, 0?y?1 and x+y?1, having successively from its base to its surface; a support substrate, a bonding layer, a monocrystalline seed layer for the epitaxial growth of the layer of material AlxInyGa(1-x-y)N. The support substrate is made of a material that presents an electrical resistivity of less than 10?3 ohm·cm and a thermal conductivity of greater than 100 W·m?1·K?1. The seed layer is in a material of the composition AlxInyGa(1-x-y)N, where 0?x?1, 0?y?1 and x+y?1. The seed and bonding layers provide a specific contact resistance that is less than or equal to 0.1 ohm·cm?2, and the materials of the support substrate, the bonding layer and the seed layer are refractory at a temperature of greater than 750° C. or even greater than 1000° C. The invention also relates to methods for manufacturing the support.Type: ApplicationFiled: November 30, 2010Publication date: June 2, 2011Inventors: Jean-Marc Bethoux, Fabrice Letertre, Chris Werkhoven, Ionut Radu, Oleg Kononchuk
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Publication number: 20110117387Abstract: A method for fabricating metal nanodots on a substrate is provided. The method includes: preparing a nanoporous polysulfone membrane; applying the nanoporous polysulfone membrane onto a substrate; depositing a metal into the pores of the polysulfone membrane thereby forming metal nanodots on the substrate; and removing the nanoporous polysulfone membrane.Type: ApplicationFiled: November 16, 2010Publication date: May 19, 2011Inventors: Shivaraman Ramaswamy, Gopalakrishnan Chandasekaran
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Publication number: 20110114016Abstract: There is provided an AlGaN bulk crystal manufacturing method for manufacturing a high-quality AlGaN bulk crystal having a large thickness. Also, there is provided an AlGaN substrate manufacturing method for manufacturing a high-quality AlGaN substrate. The AlGaN bulk crystal manufacturing method includes the following steps: First, a support substrate composed of AlaGa(1-a)N (0<a?1) is prepared. Then, a bulk crystal composed of AlbGa(1-b)N (0<b<1) with a primary surface is grown on the support substrate. The composition ratio a of Al in the support substrate is larger than the composition ratio b of Al in the bulk crystal. The AlGaN substrate manufacturing method includes a step of cutting out at least one AlbGa(1-b)N substrate from the bulk crystal.Type: ApplicationFiled: July 16, 2009Publication date: May 19, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Michimasa Miyanaga, Naho Mizuhara, Keisuke Tanizaki, Issei Satoh, Hideaki Nakahata
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Publication number: 20110114965Abstract: Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to a substrate using a glass may be utilized to control the strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control the strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.Type: ApplicationFiled: September 24, 2010Publication date: May 19, 2011Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIESInventor: Fabrice Letertre
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Publication number: 20110110840Abstract: A method for producing a group III-nitride crystal having a large thickness and high quality and a group III-nitride crystal are provided. A method for producing a group III-nitride crystal 13 includes the following steps: A underlying substrate 11 having a major surface 11a tilted toward the <1-100> direction with respect to the (0001) plane is prepared. The group III-nitride crystal 13 is grown by vapor-phase epitaxy on the major surface 11a of the underlying substrate 11. The major surface 11a of the underlying substrate 11 is preferably a plane tilted at an angle of ?5° to 5° from the {01-10} plane.Type: ApplicationFiled: June 26, 2009Publication date: May 12, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTDInventors: Michimasa Miyanaga, Naho Mizuhara, Keisuke Tanizaki, Issei Satoh, Hideaki Nakahata, Satoshi Arakawa, Yoshiyuki Yamamoto, Takashi Sakurada
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Publication number: 20110109973Abstract: A method of producing an AlxGa(1-x)N (0<x?1) single crystal of the present invention is directed to growing an AlxGa(1-x)N single crystal by sublimation. The method includes the steps of preparing an underlying substrate, preparing a raw material of high purity, and growing an AlxGa(1-x)N single crystal on the underlying substrate by sublimating the raw material. At the AlxGa(1-x)N single crystal, the refractive index with respect to light at a wavelength greater than or equal to 250 nm and less than or equal to 300 nm is greater than or equal to 2.4, and the refractive index with respect to light at a wavelength greater than 300 nm and less than 350 nm is greater than or equal to 2.3, measured at 300K.Type: ApplicationFiled: June 25, 2009Publication date: May 12, 2011Applicant: Sumitomo Electric Industries, Ltd.Inventors: Satoshi Arakawa, Takashi Sakurada, Yoshiyuki Yamamoto, Issei Satoh, Keisuke Tanizaki, Hideaki Nakahata, Naho Mizuhara, Michimasa Miyanaga
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Publication number: 20110089431Abstract: A method for producing a compound single crystal includes a process (I) of growing the compound single crystal while causing an anti-phase boundary and a stacking fault to equivalently occur in a <110> direction parallel to the surface, the stacking fault being attributable to the elements A and B; a process (II) of merging and annihilating the stacking fault, attributable to the element A, and the anti-phase boundary, which occurs in the process (I); a process (III) of vanishing the stacking fault attributable to the element B, which occurs in the process (I); and a process (IV) of completely merging and annihilating the anti-phase boundary. The process (IV) is carried out simultaneously with the processes (II) and (III) or after the processes (II) and (III).Type: ApplicationFiled: October 15, 2010Publication date: April 21, 2011Applicant: HOYA CORPORATIONInventors: Kuniaki YAGI, Takahisa SUZUKI, Yasutaka YANAGISAWA, Masao HIROSE, Noriko SATO, Junya KOIZUMI, Hiroyuki NAGASAWA
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Patent number: 7896965Abstract: A method for the production of a plurality of optoelectronic semiconductor chips each having a plurality of structural elements with respectively at least one semiconductor layer. The method involves providing a chip composite base having a substrate and a growth surface. A non-closed mask material layer is grown onto the growth surface in such a way that the mask material layer has a plurality of statistically distributed windows having varying forms and/or opening areas, a mask material being chosen in such a way that a semiconductor material of the semiconductor layer that is to be grown in a later method step essentially cannot grow on said mask material or can grow in a substantially worse manner in comparison with the growth surface. Subsequently, semiconductor layers are deposited essentially simultaneously onto regions of the growth surface that lie within the windows. A further method step is singulation of the chip composite base with applied material to form semiconductor chips.Type: GrantFiled: July 22, 2004Date of Patent: March 1, 2011Assignee: OSRAM Opto Semiconductors GmbHInventor: Volker Härle
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Publication number: 20110031534Abstract: There are provided a Si(1-v-w-x)CwAlxNv substrate that achieves high crystallinity and low costs, an epitaxial wafer, and manufacturing methods thereof. A method for manufacturing a Si(1-v-w-x)CwAlxNv substrate according to the present invention includes the steps of preparing a different type of substrate 11 and growing a Si(1-v-w-xCwAlxNv layer having a main surface on the different type of substrate 11. The component ratio x+v at the main surface of the Si(1-v-w-x)CwAlxNv layer is 0<x+v<1. The component ratio x+v increases or decreases monotonically from the interface between the Si(1-v-w-x)CwAlxNv layer and the different type of substrate 11 to the main surface of the Si(1-v-w-x)CwAlxNv layer. The component ratio x+v at the interface between the Si(1-v-w-x)CwAlxNv layer and the different type of substrate 11 is closer to that of the material of the different type of substrate 11 than the component ratio x+v at the main surface of the Si(1-v-w-x)CwAlxNv layer.Type: ApplicationFiled: April 17, 2009Publication date: February 10, 2011Inventors: Issei Satoh, Michimasa Miyanaga, Shinsuke Fujiwara, HIdeaki Nakahata
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Patent number: 7858959Abstract: A laminated film structure, method of manufacturing, and a preferable electronic element using the structure. The effective polarization into the electric field can be realized in the direction of crystal axis by enhancing the crystal property and alignment property of the ferroelectric substance film formed through epitaxial growth with reference to the plane alignment of semiconductor substrate. After the yttrium stabilized zirconium film and a film of the rock salt structure are sequentially formed with epitaxial growth on a semiconductor substrate, the ferroelectric substance film of simple Perovskite structure is also formed with epitaxial growth. The ferroelectric substance film can improve the crystal property and alignment property thereof by rotating the plane for 45 degrees within the plane for the crystal axis of the yttrium stabilized zirconium.Type: GrantFiled: May 12, 2008Date of Patent: December 28, 2010Assignee: Fujitsu LimitedInventors: Masao Kondo, Kazuaki Kurihara
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Publication number: 20100319614Abstract: A compound semiconductor single-crystal manufacturing device (1) is furnished with: a laser light source (6) making it possible to sublime a source material by directing a laser beam onto the material; a reaction vessel (2) having a laser entry window (5) through which the laser beam output from the laser light source (6) can be transmitted to introduce the beam into the vessel interior, and that is capable of retaining a starting substrate (3) where sublimed source material is recrystallized; and a heater (7) making it possible to heat the starting substrate (3). The laser beam is shone on, to heat and thereby sublime, the source material within the reaction vessel (2), and compound semiconductor single crystal is grown by recrystallizing the sublimed source material onto the starting substrate (3); afterwards the laser beam is employed to separate the compound semiconductor single crystal from the starting substrate (3).Type: ApplicationFiled: March 6, 2009Publication date: December 23, 2010Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Issei Satoh, Naho Mizuhara, Keisuke Tanizaki, Michimasa Miyanaga, Takashi Sakurada, Hideaki Nakahata
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Publication number: 20100307405Abstract: Affords a method of growing large-scale, high-quality AlxGa1-xN single crystal. An AlxGa1-xN single crystal growth method is provided with: a step of preparing an AlyGa1-yN (0<y?1) seed crystal (4) whose crystal diameter D mm and thickness T mm satisfy the relation T<0.003D+0.15; and a step of growing AlxGa1-xN (0<x?1) single crystal (5) onto a major surface (4m) of the AlyGa1-yN seed crystal (4) by sublimation growth.Type: ApplicationFiled: December 24, 2008Publication date: December 9, 2010Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Michimasa Miyanaga, Naho Mizuhara, Keisuke Tanizaki, Tomohiro Kawase, Hideaki Nakahata
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Publication number: 20100301420Abstract: A method for preparing a multilayer substrate includes the step of deposing an epitaxial ?-Al2O3 Miller index (001) layer on a Si Miller index (001) substrate.Type: ApplicationFiled: August 28, 2007Publication date: December 2, 2010Inventors: Clément Merckling, Mario El-Kazzi, Guillaume Saint-Girons, Guy Hollinger
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Patent number: 7842134Abstract: The invention relates to a method of manufacture of a substrate for fabrication of semiconductor layers or devices, comprising the steps of providing a wafer of silicon including at least one first surface suitable for use as a substrate for CVD diamond synthesis, growing a layer of CVD diamond of predetermined thickness and having a growth face onto the first surface of the silicon wafer, reducing the thickness of the silicon wafer to a predetermined level, and providing a second surface on the silicon wafer that is suitable for further synthesis of at least one semiconductor layer suitable for use in electronic devices or synthesis of electronic devices on the second surface itself and to a substrate suitable for GaN device growth consisting of a CVD diamond layer intimately attached to a silicon surface.Type: GrantFiled: March 20, 2006Date of Patent: November 30, 2010Inventors: Andrew John Whitehead, Christopher John Howard Wort, Geoffrey Alan Scarsbrook
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Publication number: 20100294197Abstract: Epitaxially coated silicon wafers are produced by placing a wafer polished on its front side on a susceptor in an epitaxy reactor, first pretreating under a hydrogen atmosphere and in a second and a third step with addition of an etching medium to the hydrogen atmosphere, and subsequently providing an epitaxial layer, wherein during the first and second steps the hydrogen flow rate is 20-100 slm, during the second and third steps the flow rate of the etching medium is 0.5-1.5 slm, during the second step the average temperature in the reactor chamber is 950-1050° C., and the power of heating elements above and below the susceptor is regulated such that there is a temperature difference of 5-30° C. between a radially symmetrical region encompassing the central axis of and a part lying outside this region; and during the third step the hydrogen flow rate is reduced to 0.5-10 slm. In a second method, during the third pretreatment step the flow rate of the etching medium is increased to 1.Type: ApplicationFiled: April 23, 2010Publication date: November 25, 2010Applicant: Siltronic AGInventor: Joerg Haberecht
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Patent number: 7833348Abstract: An object of the invention is to calibrate an upper pyrometer for indirectly measuring a substrate temperature at the time of epitaxial growth in a comparatively short time and with accuracy to thereby improve the quality of an epitaxial substrate. After calibrating an upper pyrometer by a thermocouple mounted to a temperature calibrating susceptor, a measured value of a lower pyrometer is adjusted to a calibrated value of the upper pyrometer. Then, a correlation line between substrate temperature indirectly measured by the upper pyrometer at the time of epitaxial growth onto a sample substrate and haze of a sample substrate measured immediately after epitaxial growth is set to indirectly measure a substrate temperature by the upper pyrometer at the time of epitaxial growth onto a mass-production substrate.Type: GrantFiled: September 21, 2006Date of Patent: November 16, 2010Assignee: Sumco CorporationInventors: Naoyuki Wada, Hiroyuki Kishi
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Patent number: 7824493Abstract: A method for manufacturing a silicon wafer includes a step of annealing a silicon wafer which is sliced from a silicon single crystal ingot, thereby forming a DZ layer in a first surface and in a second surface of the silicon wafer and a step of removing either a portion of the DZ layer in the first surface or a portion of the DZ layer in the second surface.Type: GrantFiled: July 20, 2005Date of Patent: November 2, 2010Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toshiaki Ono, Wataru Sugimura, Masataka Hourai
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Patent number: 7820244Abstract: In a method of forming a layer, a titanium layer and a titanium nitride layer may be successively formed on a first wafer. By-products adhered to the inside of a chamber during the formation of the titanium nitride layer may be removed from the chamber. Processes of forming the titanium layer, forming the titanium nitride layer, and removing the by-products may be repeated relative to a second wafer.Type: GrantFiled: October 31, 2006Date of Patent: October 26, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hun Seo, Jin-Gi Hong, Yun-Ho Choi, Hyun-Chul Kwun, Eun-Taeck Lee, Jin-Ho Kim
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Patent number: 7815734Abstract: Provided are a thin film transistor and method of fabricating the same, in which an amorphous silicon layer is formed on a substrate, a capping layer containing a metal catalyst having a different concentration according to its thickness is formed on the amorphous silicon layer, the capping layer is patterned to form a capping layer pattern, and the amorphous silicon layer is crystallized, such that the density and position of seeds formed at an interface between the amorphous silicon layer and the capping layer pattern is controlled, thereby improving the size and uniformity of grains, and in which polycrystalline silicon of desired size and uniformity is selectively formed at a desired position by one crystallization process, resulting in a thin film transistor having excellent and desired properties.Type: GrantFiled: July 14, 2006Date of Patent: October 19, 2010Assignee: Samsung Mobile Display Co., Ltd.Inventors: Byoung-Keon Park, Jin-Wook Seo, Tae-Hoon Yang, Ki-Yong Lee
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Publication number: 20100229788Abstract: A manufacturing method for three-dimensional GaN epitaxial structure comprises a disposing step, in which a substrate of LiAlO2 and a source metal of Ga are disposed inside an vacuum chamber. An exposing step is importing N ions in plasma state and generated by a nitrogen source into the chamber. A heating step is heating up the source metal to generate Ga vapor. A growing step is forming a three-dimensional GaN epitaxial structure with hexagonal micropyramid or hexagonal rod having a broadened disk-like surface on the substrate by reaction between the Ga vapor and the plasma state of N ions.Type: ApplicationFiled: September 28, 2009Publication date: September 16, 2010Applicant: NATIONAL SUN YAT-SEN UNIVERSITYInventors: I-Kai LO, Chia-Ho HSIEH, Yu-Chi HSU, Wen-Yuan PANG, Ming-Chi CHOU
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Publication number: 20100233870Abstract: A method of fabricating a group III nitride semiconductor single crystal includes preparing a seed substrate which includes group III nitride semiconductor and has a crystal growth face of single index plane, and epitaxially growing the group III nitride semiconductor single crystal on the crystal growth face, wherein the group III nitride semiconductor single crystal is epitaxially grown while being surrounded by a plurality of crystal surfaces including low-index planes spontaneously formed, and the low-index planes have a structure that each of plane indices showing a crystal plane is not more than 3.Type: ApplicationFiled: June 15, 2009Publication date: September 16, 2010Applicant: Hitachi Cable, Ltd.Inventor: Yuichi Oshima
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Patent number: 7794540Abstract: Method of manufacturing a semiconductor device, in which on a region of silicon oxide (5) situated next to a region of monocrystalline silicon (4) at the surface (3) of a semiconductor body (1), a non-monocrystalline auxiliary layer (8) is formed. The auxiliary layer is formed in two steps. In the first step, the silicon body is heated in an atmosphere comprising a gaseous arsenic compound; in the second step it is heated in an atmosphere comprising a gaseous silicon compound instead of said arsenic compound. Thus, the regions of silicon oxide are provided with an amorphous or polycrystalline silicon seed layer in a self-aligned manner.Type: GrantFiled: December 16, 2003Date of Patent: September 14, 2010Assignee: NXP B.V.Inventors: Petrus Hubertus Cornelis Magnee, Johannes Josephus Theodorus Marinus Donkers, Xiaoping Shi
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Publication number: 20100206218Abstract: A method of making a group III nitride-based compound semiconductor includes providing a semiconductor substrate comprising group III nitride-based compound semiconductor, polishing a surface of said semiconductor substrate such that said polished surface includes an inclined surface that has an off-angle ? of 0.15 degrees or more and 0.6 degrees or less to one of an a-face, a c-face and an m-face of the semiconductor substrate, providing a stripe-shaped specific region on the polished surface, the specific region comprising a material that prevents the growth of the group III nitride-based compound semiconductor on its surface, and growing a semiconductor epitaxial growth layer of group III nitride-based compound semiconductor on the polished surface of the semiconductor substrate.Type: ApplicationFiled: March 2, 2010Publication date: August 19, 2010Applicants: Toyoda Gosei Co., Ltd., Sumitomo Electric Industries, Ltd.Inventor: Ryo Nakamura
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Patent number: 7776153Abstract: A method and apparatus for producing bulk single crystals of AlN having low dislocation densities of about 10,000 cm?2 or less includes a crystal growth enclosure with Al and N2 source material therein, capable of forming bulk crystals. The apparatus maintains the N2 partial pressure at greater than stoichiometric pressure relative to the Al within the crystal growth enclosure, while maintaining the total vapor pressure in the crystal growth enclosure at super-atmospheric pressure. At least one nucleation site is provided in the crystal growth enclosure, and provision is made for cooling the nucleation site relative to other locations in the crystal growth enclosure. The Al and N2 vapor is then deposited to grow single crystalline low dislocation density AlN at the nucleation site. High efficiency ultraviolet light emitting diodes and ultraviolet laser diodes are fabricated on low defect density AlN substrates, which are cut from the low dislocation density AlN crystals.Type: GrantFiled: November 3, 2005Date of Patent: August 17, 2010Assignee: Crystal IS, Inc.Inventors: Leo J. Schowalter, Glen A. Slack, J. Carlos Rojo
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Patent number: 7745315Abstract: A method for forming vertically oriented, crystallographically aligned nanowires (nanocolumns) using monolayer or submonolayer quantities of metal atoms to form uniformly sized metal islands that serve as catalysts for MOCVD growth of Group III nitride nanowires.Type: GrantFiled: October 3, 2007Date of Patent: June 29, 2010Assignee: Sandia CorporationInventors: George T. Wang, Qiming Li, J. Randall Creighton
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Publication number: 20100143748Abstract: Methods of growing and manufacturing aluminum nitride crystal, and aluminum nitride crystal produced by the methods. Preventing sublimation of the starting substrate allows aluminum nitride crystal of excellent crystallinity to be grown at improved growth rates. The aluminum nitride crystal growth method includes the following steps. Initially, a laminar baseplate is prepared, furnished with a starting substrate having a major surface and a back side, a first layer formed on the back side, and a second layer formed on the first layer. Aluminum nitride crystal is then grown onto the major surface of the starting substrate by vapor deposition. The first layer is made of a substance that at the temperatures at which the aluminum nitride crystal is grown is less liable to sublimate than the starting substrate. The second layer is made of a substance whose thermal conductivity is higher than that of the first layer.Type: ApplicationFiled: December 19, 2008Publication date: June 10, 2010Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Keisuke Tanizaki, Naho Mizuhara, Michimasa Miyanaga, Hideaki Nakahata, Yoshiyuki Yamamoto
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Publication number: 20100139555Abstract: Apparatus for vapour phase growing of crystals having a single multi-zone heater arranged to heat a heated zone to give a predetermined temperature profile along the length of the heated zone. A generally U-shaped tube having a first limb, a second limb, and a linkage connecting the first and second limbs is located on the heated zone. The first limb contains a source material. The second limb supports a seed such that the source material and seed are spaced longitudinally within the heated zone to provide a predetermined temperature differential between the source and seed. The crystal is grown on the seed.Type: ApplicationFiled: May 16, 2008Publication date: June 10, 2010Applicant: DURHAM SCIENTIFIC CRYSTALS LTDInventors: Arnab Basu, Ben Cantwell, Max Robinson
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Publication number: 20100111808Abstract: The present invention provides a method for growing group III-nitride crystals wherein the group III-nitride crystal growth occurs on an etched seed crystal. The etched seed is fabricated prior to growth using a temperature profile which produces a high solubility of the group III-nitride material in a seed crystals zone as compared to a source materials zone. The measured X-ray diffraction of the obtained crystals have significantly narrower Full Width at Half Maximum values as compared to crystals grown without etch back of the seed crystal surfaces prior to growth.Type: ApplicationFiled: November 4, 2009Publication date: May 6, 2010Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Siddha Pimputkar, Derrick S. Kamber, Makoto Saito, Steven P. DenBaars, James S. Speck, Shuji Nakamura
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Patent number: 7687798Abstract: The present invention relates a method for epitaxial growth of a second group III-V crystal having a second lattice constant over a first group III-V crystal having a first lattice constant, wherein strain relaxation associated with lattice-mismatched epitaxy is suppressed and thus dislocation defects do not form. In the first step, the surface of the first group III-V crystal (substrate) is cleansed by desorption of surface oxides. In the second step, a layer of condensed group-V species is condensed on the surface of the first group III-V crystal. In the third step, a mono-layer of constituent group-III atoms is deposited over the layer of condensed group-V species in order for the layer of constituent group-III atoms to retain the condensed group-V layer. Subsequently, the mono-layer of group-III atoms is annealed at a higher temperature.Type: GrantFiled: March 28, 2006Date of Patent: March 30, 2010Assignee: HRL Laboratories, LLCInventor: Binqiang Shi
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Patent number: 7686886Abstract: A method for forming a structure of a desired cross-section on a substrate is provided. The method provides a seed structure comprising at least one support layer on the substrate. The support layer has a geometric shape related to the desired cross-section of the structure and is diffusive to a precursor constituent. The method further includes growing the structure by supplying at least one precursor constituent on the substrate. The desired cross-section of the structure is defined by the geometric shape of at least one support layer.Type: GrantFiled: September 26, 2006Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: Walter H Riess, Heike E Riel, Siegfried F Karg, Heinz Schmid
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Patent number: 7678195Abstract: A method of growing bulk single crystals of an AlN on a single crystal seed is provided, wherein an AlN source material is placed within a crucible chamber in spacial relationship to a seed fused to the cap of the crucible. The crucible is heated in a manner sufficient to establish a temperature gradient between the source material and the seed with the seed at a higher temperature than the source material such that the outer layer of the seed is evaporated, thereby cleaning the seed of contaminants and removing any damage to the seed incurred during seed preparation. Thereafter, the temperature gradient between the source material and the seed is inverted so that the source material is sublimed and deposited on the seed, thereby growing a bulk single crystal of AlN.Type: GrantFiled: April 6, 2006Date of Patent: March 16, 2010Assignee: North Carolina State UniversityInventors: Raoul Schlesser, Vladimir Noveski, Zlatko Sitar
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Patent number: 7651927Abstract: A semiconductor device includes a substrate and a semiconductor layer formed on the substrate. The substrate has: a flat region provided in a main surface thereof; a first indentation region provided in a portion of the main surface different from the flat region and formed with first recesses; and a second indentation region provided between the first indentation region and the flat region, formed with second recesses, and having a lower probability of occurrence of growth nuclei than the first indentation region and a higher probability than the flat region in the case where a crystal of a semiconductor is grown on the main surface.Type: GrantFiled: November 28, 2006Date of Patent: January 26, 2010Assignee: Panasonic CorporationInventor: Yuji Takase
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Publication number: 20100003462Abstract: A method for forming a graphene layer is disclosed herein. The method includes establishing an insulating layer on a substrate such that at least one seed region, which exposes a surface of the substrate, is formed. A seed material in the seed region is exposed to a carbon-containing precursor gas, thereby initiating nucleation of the graphene layer on the seed material and enabling lateral growth of the graphene layer along at least a portion of a surface of the insulating layer.Type: ApplicationFiled: October 16, 2008Publication date: January 7, 2010Inventors: Theodore I. Kamins, R. Stanley Williams, Nathaniel Quitoriano
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Publication number: 20090309127Abstract: A gallium containing crystalline material. The material comprises a bulk semi-polar gallium indium containing crystalline material having a thickness of about 20 nanometers to about 1000 nanometers. The material includes a spatial width dimension of no greater than about 10 microns characterizing the thickness of the bulk semi-polar gallium indium containing crystalline material. The material includes a photoluminescent characteristic of the crystalline material having a first wavelength, which is at least five nanometers greater than a second wavelength, which is derived from an indium gallium containing crystalline material grown on a growth region of greater than about 15 microns.Type: ApplicationFiled: June 10, 2009Publication date: December 17, 2009Applicants: SORAA, INC., KAAI, INC.Inventors: JAMES W. RARING, Daniel F. Feezell, SHUJI NAKAMURA
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Patent number: 7625447Abstract: SiC is a very stable substance, and it is difficult to control the condition of a SiC surface to be suitable for crystal growth in conventional Group III nitride crystal growing apparatuses. This problem is solved as follows. The surface of a SiC substrate 1 is rendered into a step-terrace structure by performing a heating process in an atmosphere of HCl gas. The surface of the SiC substrate 1 is then treated sequentially with aqua regia, hydrochloric acid, and hydrofluoric acid. A small amount of silicon oxide film formed on the surface of the SiC substrate 1 is etched so as to form a clean SiC surface 3 on the substrate surface. The SiC substrate 1 is then installed in a high-vacuum apparatus and the pressure inside is maintained at ultrahigh vacuum (such as 10?6 to 10?8 Pa). In the ultrahigh vacuum state, a process of irradiating the surface with a Ga atomic beam 5 at time t1 at temperature of 800° C. or lower and performing a heating treatment at 800° C. or higher is repeated at least once.Type: GrantFiled: March 18, 2004Date of Patent: December 1, 2009Assignee: Japan Science and Technology AgencyInventors: Jun Suda, Hiroyuki Matsunami, Norio Onojima
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Publication number: 20090273839Abstract: A method that provides for a phase conjugate mirror 10 having a gallium-arsenide substrate 11 with a generally cubic crystalline lattice and a number of gallium-arsenide crystal projections 14 extending from said substrate 11, the projections each having three generally planar surfaces 15, 16, 17, where the surfaces each being generally obliquely oriented with respect to a plane of said substrate 11, the plane substantially corresponding to a (111) crystal face, the projections 14 being oriented along the plane 13 to provide a predetermined corner-cube array pattern 10, the device including a number of implant sites 25 spaced apart from one another along the substrate 11 to define a pattern 40, and forming a number of corner-cubes articles having a shape substantially corresponding to the corner-cube array 10 pattern 40, wherein the articles each have a number of cube-corner projections 14 spaced apart from each other by a minimum distance of 1 micron.Type: ApplicationFiled: April 30, 2008Publication date: November 5, 2009Inventor: Joseph Reid Henrichs
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Patent number: 7611579Abstract: A system for synthesizing nanostructures using chemical vapor deposition (CVD) is provided. The system includes a housing, a porous substrate within the housing, and on a downstream surface of the substrate, a plurality of catalyst particles from which nanostructures can be synthesized upon interaction with a reaction gas moving through the porous substrate. Electrodes may be provided to generate an electric field to support the nanostructures during growth. A method for synthesizing extended length nanostructures is also provided. The nanostructures are useful as heat conductors, heat sinks, windings for electric motors, solenoid, transformers, for making fabric, protective armor, as well as other applications.Type: GrantFiled: January 14, 2005Date of Patent: November 3, 2009Assignee: Nanocomp Technologies, Inc.Inventors: David Lashmore, Joseph J. Brown, Robert C. Dean, Jr., Peter L. Antoinette
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Patent number: 7594967Abstract: A semiconductor structure including a cap layer formed over a semiconductor substrate having a rough edge, which discourages formation of dislocation pile-up defects.Type: GrantFiled: October 10, 2002Date of Patent: September 29, 2009Assignee: AmberWave Systems CorporationInventors: Christopher J. Vineis, Richard Westhoff, Mayank Bulsara
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Patent number: 7594968Abstract: The invention relates to a single-crystal diamond grown by microwave plasma chemical vapor deposition that has a toughness of at least about 30 MPa m1/2. The invention also relates to a method of producing a single-crystal diamond with a toughness of at least about 30 MPa m1/2. The invention further relates to a process for producing a single crystal CVD diamond in three dimensions on a single crystal diamond substrate.Type: GrantFiled: September 9, 2005Date of Patent: September 29, 2009Assignee: Carnegie Institution of WashingtonInventors: Russell J. Hemley, Ho-kwang Mao, Chih-shiue Yan
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Publication number: 20090197118Abstract: Provided is a method for producing a Group III nitride-based compound semiconductor having an M-plane main surface. The method employs a sapphire substrate having a main surface which is inclined by 30° with respect to R-plane about a line of intersection Lsapph-AM formed by R-plane and A-plane perpendicular thereto. R-plane surfaces of the sapphire substrate are exposed, and a silicon dioxide mask is formed on the main surface of the substrate. AlN buffer layers are formed on the exposed R-plane surfaces. A GaN layer is formed on the AlN buffer layers. At an initial stage of GaN growth, the top surface of the sapphire substrate is entirely covered with the GaN layer through lateral growth.Type: ApplicationFiled: January 30, 2009Publication date: August 6, 2009Applicant: TOYODA GOSEI CO.,LTD.Inventors: Seiji NAGAI, Shiro YAMAZAKI, Takayuki SATO, Yasuhide YAKUSHI, Koji OKUNO, Koichi GOSHONOO
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Patent number: 7553370Abstract: Methods of crystal growth for semiconductor materials, such as nitride semiconductors, and methods of manufacturing semiconductor devices are provided. The method of crystal growth includes forming a number of island crystal regions during a first crystal growth phase and continuing growth of the island crystal regions during a second crystal growth phase while bonding of boundaries of the island crystal regions occurs. The second crystal growth phase can include a crystal growth rate that is higher than the crystal growth rate of the first crystal growth phase and/or a temperature that is lower than the first crystal growth phase. This can reduce the density of dislocations, thereby improving the performance and service life of a semiconductor device which is formed on a nitride semiconductor made in accordance with an embodiment of the present invention.Type: GrantFiled: December 19, 2005Date of Patent: June 30, 2009Assignee: Sony CorporationInventors: Goshi Biwa, Hiroyuki Okuyama, Masato Doi, Toyoharu Oohata
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Publication number: 20090139401Abstract: A large single crystal of a complex such as an organic carboxylic acid metal complex, which crystal is useful as an adsorbent of various gases and vapors of organic solvents and as a hydrogen-absorbing material, as well as a process for producing the crystal, is disclosed. Two layers wherein an upper layer thereof is constituted by a solution containing a metal salt and an organic carboxylic acid having a conjugated system, or a solution containing a metal salt of the organic carboxylic acid having a conjugated system, and wherein a lower layer of the two layers is constituted by a solvent which is not miscible with the solvent of the solution, is formed. Vapor of pyrazine or a substituted pyrazine from a solution of pyrazine or the substituted pyrazine is introduced into the upper layer to allow reaction, thereby forming a large single crystal(s) of the organic carboxylic acid metal complex at the interface between the two layers, which crystal(s) has (have) a longer side with a size of not less than 0.8 mm.Type: ApplicationFiled: May 10, 2006Publication date: June 4, 2009Applicant: YOKOHAMA CITY UNIVERSITYInventor: Satoshi Takamizawa
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Publication number: 20090114146Abstract: To provide a method for manufacturing a semiconductor device and a substrate processing apparatus which contribute to forming high-density nuclei. The method for manufacturing a semiconductor device according to the invention includes the steps of: carrying a wafer 200 having an insulator film on the surface into a reaction tube 203; introducing silicon-based gas into the reaction tube 203 to form silicon grains on the insulator film formed on the surface of the wafer 200; and carrying the processed wafer 200 out from the reaction tube 203. Before the introduction of the silicon-based gas, dopant gas is introduced into the reaction tube 203.Type: ApplicationFiled: December 28, 2006Publication date: May 7, 2009Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Yushin Takasawa, Naonori Akae
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Patent number: 7501023Abstract: A method and apparatus for growing low defect, optically transparent, colorless, crack-free, substantially flat, single crystal Group III nitride epitaxial layers with a thickness of at least 10 microns is provided. These layers can be grown on large area substrates comprised of Si, SiC, sapphire, GaN, AlN, GaAs, AlGaN and others. In one aspect, the crack-free Group III nitride layers are grown using a modified HVPE technique. If desired, the shape and the stress of Group III nitride layers can be controlled, thus allowing concave, convex and flat layers to be controllably grown. After the growth of the Group III nitride layer is complete, the substrate can be removed and the freestanding Group III nitride layer used as a seed for the growth of a boule of Group III nitride material. The boule can be sliced into individual wafers for use in the fabrication of a variety of semiconductor structures (e.g., HEMTs, LEDs, etc.).Type: GrantFiled: February 13, 2004Date of Patent: March 10, 2009Assignee: Technologies and Devices, International, Inc.Inventors: Vladimir A. Dmitriev, Yuri V. Melnik
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Publication number: 20080197358Abstract: A device 100 comprising a substrate 115 having crystal-support-structures 110 thereon, and a III-V crystal 210. The III-V crystal is on a single contact region 140 of one of the crystal-support-structures. An area of the contact region is no more than about 50 percent of a surface area 320 of the III-V crystal.Type: ApplicationFiled: February 19, 2007Publication date: August 21, 2008Applicant: Alcatel-LucentInventors: Robert Frahm, Hock Min Ng, Brijesh Vyas
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Publication number: 20080182092Abstract: Bulk single crystal of aluminum nitride (AlN) having an a real planar defect density?100 cm?2 Methods for growing single crystal aluminum nitride include melting an aluminum foil to uniformly wet a foundation with a layer of aluminum, the foundation forming a portion of an AlN seed holder, for an AlN seed to be used for the AlN growth. The holder may consist essentially of a substantially impervious backing plate.Type: ApplicationFiled: January 17, 2008Publication date: July 31, 2008Applicant: Crystal IS, Inc.Inventors: Robert T. Bondokov, Kenneth E. Morgan, Leo J. Schowalter, Glen A. Slack
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Patent number: 7393410Abstract: There is provided a method of manufacturing a nano-wire using a crystal structure. In the method of manufacturing a nano-wire, a crystal grain having a plurality of crystal faces is used as a seed, and a crystal growing material having a lattice constant difference within a predetermined range is deposited on the crystal grain, thereby allowing the nano-wire to grow from at least one of the crystal faces. Therefore, it is possible to give the positional selectivity with a simple process using a principle of crystal growth and to generate a nano-structure such as a nano-wire, etc. having good crystallinity. Further, it is possible to generate a different-kind junction structure having various shapes by adjusting a feature of a crystal used as a seed.Type: GrantFiled: April 26, 2005Date of Patent: July 1, 2008Assignee: Samsung SDI Co., Ltd.Inventors: Sang-Hyun Lee, Tae-Won Jeong, Jeong-Na Huh
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Publication number: 20080127884Abstract: A single crystal M*N article, which may be made by a process including the steps of: providing a substrate of material having a crystalline surface which is epitaxially compatible with M*N; depositing a layer of single crystal M*N over the surface of the substrate; and removing the substrate from the layer of single crystal M*N, e.g., with an etching agent which is applied to the substrate to remove same, to yield the layer of single crystal M*N as said single crystal M*N article. The bulk single crystal M*N article is suitable for use as a substrate for the fabrication of microelectronic structures thereon, to produce microelectronic devices comprising bulk single crystal M*N substrates, or precursor structures thereof.Type: ApplicationFiled: February 12, 2008Publication date: June 5, 2008Applicant: CREE, INC.Inventors: Michael A. Tischler, Thomas F. Kuech, Robert P. Vaudo
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Patent number: 7377978Abstract: It is to provide a method for producing a silicon epitaxial wafer, which can prevent fine unevenness from occurring on a rear main surface of a silicon epitaxial wafer and which suppresses the haze level of the whole rear main surface to 50 ppm or less. A method for producing a silicon epitaxial wafer, includes: a hydrogen heat treatment step of arranging within a reactor a susceptor capable of mounting a silicon single crystal substrate and subjecting the silicon single crystal substrate mounted on the susceptor to heat treatment in a hydrogen atmosphere, and a vapor phase epitaxy step of epitaxially growing a silicon epitaxial layer after the hydrogen heat treatment step, wherein the silicon single crystal substrate is separated from the susceptor during the hydrogen heat treatment step, and the silicon single crystal substrate is mounted on the susceptor during the vapor phase epitaxy step.Type: GrantFiled: June 21, 2004Date of Patent: May 27, 2008Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Tsuyoshi Nishizawa
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Publication number: 20080107876Abstract: Disclosed herein is a method of selectively growing zinc oxide microstructures and the zinc oxide microstructures prepared using the method. The method includes the steps of applying an organic material or an inorganic material on a substrate, forming a pattern having a predetermined specific location and a predetermined interval on the substrate using a physical or chemical etching method, and selectively growing zinc oxide microstructures at the location where the pattern is formed using various growth methods such as hydro-thermal synthesis, physical vapor deposition, chemical vapor deposition method or the like.Type: ApplicationFiled: March 27, 2007Publication date: May 8, 2008Applicants: POSTECH FOUNDATION, POSTECH ACADEMY-INDUSTRY FOUNDATIONInventors: Gyu-chul Yi, Yong-jin Kim, Chul-ho Lee