With Pretreatment Or Preparation Of A Base (e.g., Annealing) Patents (Class 117/106)
  • Patent number: 5885346
    Abstract: Organic protective film 4 is directly adhered on the surface of silicon semiconductor crystal 1. Silicon semiconductor crystal 1 with organic protective film 4 is prepared by adhering organic protective film 4 on the surface of silicon semiconductor crystal substrate 1 on which oxide film 8 is formed, removing oxide film 8 to directly adhere organic protective film 4 on the surface of silicon semiconductor crystal 1, removing organic protective film 4 and then treating silicon semiconductor crystal 1.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: March 23, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Habuka, Toru Otsuka
  • Patent number: 5882401
    Abstract: A method for manufacturing a silicon single crystal substrate for use of an epitaxial layer growth. The method comprises the steps of: growing a CVD film on a rear surface and a peripheral side portion, of the silicon single crystal substrate; removing a portion of the CVD film on the peripheral side portion in the vicinity of a main surface of the silicon single crystal substrate, which was grown over an end of the peripheral side portion, by an abrasive tape grinding; and thereafter mirror-polishing the main surface of the silicon single crystal substrate.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: March 16, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tamotsu Maruyama, Hiroki Ose
  • Patent number: 5882400
    Abstract: The invention concerns a method of producing a surface layer structure by doping a matrix with metal ions. The aim of the invention is to provide a method of this kind in which the depth distribution of the metal ions in the substrate can be regulated, thus optimumizing the doping without incurring any of the disadvantages inherent in the prior art methods. This is achieved by first depositing matrix material on a suitable substrate by laser ablation in an atmosphere of oxygen, thus forming a on surface of the substrate a first layer a matrix material. Dopant is then deposited on the surface of the first layer, followed by more matrix material. The result is a uniform doping of the deposited matrix at a defined depth in the surface layer structure.
    Type: Grant
    Filed: May 10, 1996
    Date of Patent: March 16, 1999
    Assignee: Forschungszentrum Julich GmbH
    Inventors: Stefanie Bauer, Martin Fleuster, Willi Zander, Jurgen Schubert, Christoph Buchal
  • Patent number: 5861337
    Abstract: A method for manufacturing a semiconductor device including preparing a multi-chamber system having at least first and second chambers, the first chamber for forming a film and the second chamber for processing an object with a laser light; processing a substrate in one of the first and second chambers; transferring the substrate to the other one of the first and second chambers; and processing the substrate in the other one of the chambers, wherein the first and second chambers can be isolated from one another by using a gate valve.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: January 19, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Naoto Kusumoto
  • Patent number: 5853478
    Abstract: A method for forming a crystal, which comprises applying a crystal forming treatment on a substrate having a free surface on which a deposition surface (S.sub.NDS) with a small nucleation density and a deposition surface (S.sub.NDL) having a sufficiently small area for crystal growth only from a single nucleus and having a greater nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said deposition surface (S.sub.NDS) are arranged adjacent to each other, thereby growing a single crystal from said single nucleus.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: December 29, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Yasuhiro Naruse
  • Patent number: 5830270
    Abstract: A structure including a film of a desired perovskite oxide which overlies and is fully commensurate with the material surface of a semiconductor-based substrate and an associated process for constructing the structure involves the build up of an interfacial template film of perovskite between the material surface and the desired perovskite film. The lattice parameters of the material surface and the perovskite of the template film are taken into account so that during the growth of the perovskite template film upon the material surface, the orientation of the perovskite of the template is rotated 45.degree. with respect to the orientation of the underlying material surface and thereby effects a transition in the lattice structure from fcc (of the semiconductor-based material) to the simple cubic lattice structure of perovskite while the fully commensurate periodicity between the perovskite template film and the underlying material surface is maintained.
    Type: Grant
    Filed: August 5, 1996
    Date of Patent: November 3, 1998
    Assignee: Lockheed Martin Energy Systems, Inc.
    Inventors: Rodney Allen McKee, Frederick Joseph Walker
  • Patent number: 5821200
    Abstract: A lattice matching device includes a substrate having thereon monocrystal regions having different lattice mismatches with respect to a LnBa.sub.2 Cu.sub.3 O.sub.x superconductor. A superconducting thin film is formed on the substrate, which film consists essentially of a superconductor of LnBa.sub.2 Cu.sub.3 O.sub.x wherein Ln represents yttrium or a lanthanide, and 6<x<7. The first and second superconducting thin film portions have different axes of orientation perpendicular to a main surface of the substrate, and arranged in contact with each other or at a distance which allows transmission of electron pairs from one to another.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 13, 1998
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Masashi Mukaida, Shintaro Miyazawa, Junya Kobayashi
  • Patent number: 5817174
    Abstract: A method of treating a semiconductor substrate, which comprises the steps of subjecting a surface of the semiconductor substrate to an annealing treatment, performing an etching treatment of the surface of the semiconductor substrate under a condition where the semiconductor substrate is substantially prevented from being etched and a precipitate exposed from the surface of the semiconductor substrate is selectively etched away, and forming a monocrystalline film of a semiconductor material constituting the semiconductor substrate on the surface of the semiconductor substrate.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: October 6, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Tomita, Mami Takahashi
  • Patent number: 5811375
    Abstract: A superconducting multilayer interconnection comprises a substrate having a principal surface, a first superconducting current path of a c-axis orientated oxide superconductor thin film formed on the principal surface of the substrate, an insulating layer on the first superconducting current path, and a second superconducting current path of a c-axis orientated oxide superconductor thin film formed on the insulating layer so that the first and second superconducting current paths are insulated by the insulating layer. The superconducting multilayer interconnection further comprises a superconducting interconnect current path of an a-axis orientated oxide superconductor thin film, through which the first and second superconducting current paths are electrically connected each other.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: September 22, 1998
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5795795
    Abstract: A method of fabricating a semiconductor device by the use of laser crystallization steps is provided. During these crystallization steps, an amorphous or polycrystalline semiconductor is crystallized by laser irradiation in such a way that generation of ridges is suppressed. Two separate laser crystallization steps are carried out. First, a laser irradiation step is performed in a vacuum, using somewhat weak laser light. Then, another laser irradiation step is performed in a vacuum, in the atmosphere, or in an oxygen ambient with intenser laser light. The first laser irradiation conducted in a vacuum does not result in satisfactory crystallization. However, this irradiation can suppress generation of ridges. The second laser irradiation step is performed in a vacuum, in the atmosphere, or in an oxygen ambient to achieve sufficient crystallization, but no ridges are produced.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: August 18, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takamasa Kousai, Hongyong Zhang, Akiharu Miyanaga
  • Patent number: 5792270
    Abstract: A method and apparatus for producing a pattern of nucleation sites is disclosed. The method enables the growth of single crystal layers of a desired orientation on a suitable amorphous and/or non-single crystal surface. The method can be used to produce single crystal Si layers of a desired orientation on an amorphous layer, e.g. of SiO.sub.2 or Si.sub.3 N.sub.4. The method can provide for growth of (100) crystal orientation on SiO.sub.2. Semiconductor films may be accordingly grown on amorphous glass substrates for producing solar cells of high efficiency. A pattern of nucleation sites is created in amorphous layers, e.g. SiO.sub.2 on an IC wafer, by high-dose implantation through a single crystal mask having appropriate channeling directions at the desired lattice constants. Such implantation may be performed in a conventional ion implanter. Subsequent to creation of spaced-apart nucleation sites, epitaxial Si may be grown on such an SiO.sub.2 surface by CVD of Si.
    Type: Grant
    Filed: October 21, 1993
    Date of Patent: August 11, 1998
    Inventor: Arjun Saxena
  • Patent number: 5785756
    Abstract: A novel molecular beam epitaxy deposition process for precisely growing structurally robust films and coatings containing germanium and various fluoride compounds for use as an optical filter. The process comprises depositing two (2) materials having different indices of refraction via molecular beam epitaxy at a temperature significantly lower than the optimal growth temperature. At such lower temperature, layers of the respective compounds are grown, via molecular beam epitaxy, such that the layers contain large concentrations of dislocations. Once the film or coating has been grown to the desired thickness, the material deposited is allowed to cool to room temperature and may then be used in a wide range of applications.
    Type: Grant
    Filed: March 6, 1997
    Date of Patent: July 28, 1998
    Assignee: Northrop Grumman Corporation
    Inventor: Myung B. Lee
  • Patent number: 5753040
    Abstract: In one form of the invention, a method for the growth of an epitaxial insulator-metal structure on a semiconductor surface comprising the steps of maintaining the semiconductor surface at a pressure below approximately 1.times.10.sup.-7 mbar, maintaining the semiconductor surface at a substantially fixed first temperature between approximately 25.degree. C. and 400.degree. C., depositing an epitaxial metal layer on the semiconductor surface, adjusting the semiconductor surface to a substantially fixed second temperature between approximately 25.degree. C. and 200.degree. C., starting a deposition of epitaxial CaF.sub.2 on the first metal layer, ramping the second temperature to a third substantially fixed temperature between 200.degree. C. and 500.degree. C. over a time period, maintaining the third temperature until the epitaxial CaF.sub.2 has deposited to a desired thickness, and stopping the deposition of epitaxial CaF.sub.2 on the first metal layer.Other devices, systems and methods are also disclosed.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 19, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Chih-Chen Cho
  • Patent number: 5746826
    Abstract: Utilizing rugged pattern of atomic size present on a crystalline substrate of a semiconductor such as silicon or selenium or the like, a microstructure body is produced on the substrate by forming a layer of a first element of one monolayer or less by arranging at the position of the substrate most stable in energy formed by ruggedness the atoms of the first element such as gold, silver, copper, nickel, palladium, platinum or an element of group IV and then depositing successively atoms of at least one second element of group III, group IV and group V on only at a part of the surface of the substrate on which said layer of one monolayer or less by vapor deposition, sputtering or the like.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: May 5, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Tsuyoshi Hasegawa, Shigeyuki Hosoki, Makiko Kohno, Masakazu Ichikawa, Hitoshi Nakahara, Toshiyuki Usagawa
  • Patent number: 5741360
    Abstract: In a method of selectively growing a crystal of a compound semiconductor layer which is composed of gallium and arsenic, a selective growth is selectively carried out on a substrate by using a combination of metallic gallium and a reactive gas, such as trisdimethylminoarsine, which includes a metallic compound of arsenic specified by at least one amine. The combination may includes organometallic gallium, such as trimethylgallium, triethylgallium instead of the metallic gallium. Such a combination serves to selectively deposit the compound semiconductor layer only on an exposed portion uncovered with a mask. Any other compound semiconductor layer may be selectively deposited on the exposed portion. The exposed portion may be composed of GaAs, AlGaAs, or InGaAs.
    Type: Grant
    Filed: August 11, 1995
    Date of Patent: April 21, 1998
    Assignee: Optoelectronics Technology Research Corporation
    Inventors: Shigeo Goto, Yasuhiko Nomura, Yoshitaka Morishita, Seikoh Yoshida, Masahiro Sasaki
  • Patent number: 5738720
    Abstract: The present invention aims to provide a method of manufacturing a microstructure pattern of a high orientation aggregate of organic molecular material by forming a fine pattern made by single crystal growing ionic material of another property on an ionic substrate by lithography and epitaxial growth, and forming a pattern made by organic molecular material having functionability to light on the fine pattern by utilizing dependence of substrate material of crystal growth rate in epitaxial growth, and is applied to the formation of a microstructure pattern of organic molecular material which can be utilized for optical waveguide, optical integrated circuit, non-linear optical element and laser resonator.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: April 14, 1998
    Assignee: The University of Tokyo
    Inventors: Toshihiro Shimada, Atsushi Koma
  • Patent number: 5739086
    Abstract: A biaxially textured article includes a rolled and annealed, biaxially textured substrate of a metal having a face-centered cubic, body-centered cubic, or hexagonal close-packed crystalline structure; and an epitaxial superconductor or other device epitaxially deposited thereon.
    Type: Grant
    Filed: May 22, 1996
    Date of Patent: April 14, 1998
    Assignee: Lockheed Martin Energy Systems, Inc.
    Inventors: Amit Goyal, John D. Budai, Donald M. Kroeger, David P. Norton, Eliot D. Specht, David K. Christen
  • Patent number: 5733369
    Abstract: A method for forming a crystal, which comprises applying a crystal forming treatment on a substrate having a free surface on which a deposition surface (S.sub.NDS) with a small nucleation density and a deposition surface (S.sub.NDL) having a sufficiently small area for crystal growth only from a single nucleus and having a greater nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said deposition surface (S.sub.NDS) are arranged adjacent to each other, thereby growing a single crystal from said single nucleus.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 31, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Yasuhiro Naruse
  • Patent number: 5679153
    Abstract: A method is disclosed for producing epitaxial layers of silicon carbide that are substantially free of micropipe defects. The method comprises growing an epitaxial layer of silicon carbide on a silicon carbide substrate by liquid phase epitaxy from a melt of silicon carbide in silicon and an element that enhances the solubility of silicon carbide in the melt. The atomic percentage of that element predominates over the atomic percentage of silicon in the melt. Micropipe defects propagated by the substrate into the epitaxial layer are closed by continuing to grow the epitaxial layer under the proper conditions until the epitaxial layer has a thickness at which micropipe defects present in the substrate are substantially no longer reproduced in the epitaxial layer, and the number of micropipe defects in the epitaxial layer is substantially reduced.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: October 21, 1997
    Assignee: Cree Research, Inc.
    Inventors: Vladimir A. Dmitriev, Svetlana V. Rendakova, Vladimir A. Ivantsov, Calvin H. Carter, Jr.
  • Patent number: 5654229
    Abstract: A method for providing an nonlinear, frequency converting optical QPM waveguide device by growing a first ferroelectric oxide film or layer on a second ferroelectric layer or medium wherein, in first and second embodiments, respectively, the second layer is initially provided with a periodic nonlinear coefficient pattern or a periodic pattern comprising a seed layer. During the growth of the first layer, the periodic pattern formed in the second layer, is replicated, transformed or induced into the first layer resulting in a plurality of substantially rectangular prismatic-shaped domains in the first layer having the periodic nonlinear coefficient pattern status based upon the periodic patterning of the second layer.
    Type: Grant
    Filed: April 26, 1995
    Date of Patent: August 5, 1997
    Assignee: Xerox Corporation
    Inventors: Florence E. Leplingard, John J. Kingston, Ross D. Bringans, David K. Fork, Robert G. Waarts, David F. Welch, Randall S. Geels
  • Patent number: 5603765
    Abstract: High breakdown voltages for AlInAs layers in InP-based devices, such as a gate layer in an InP HEMT or a collector layer in a heterojunction bipolar transistor, are achieved by growing the AlInAs layer by MBE at a substrate temperature about 70.degree.-125.degree. C. below the temperature at which a 2.times.4 reflective high energy diffraction pattern is observed. This corresponds to a growth temperature range of about 415.degree.-470.degree. C. for a 540.degree. 2.times.4 reconstruction temperature. Preferred growth temperatures within these ranges are 80.degree. C. below the 2.times.4 reconstruction temperature, or about 460.degree. C. Higher breakdown voltages are obtained than when the AlInAs layer is grown at either higher or lower temperatures.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: February 18, 1997
    Assignee: Hughes Aircraft Company
    Inventors: Mehran Matloubian, Linda M. Jelloian, Mark Lui, Takyiu Liu
  • Patent number: 5593497
    Abstract: A method for forming a deposited film comprises the step of introducing a starting material (A) which is either one of a gaseous starting material for formation of a deposited film and a gaseous halogenic oxidizing agent having the property of oxidative action on said starting material into a film forming space in which a substrate having a material which becomes crystal neclei for a deposited film to be formed or a material capable of forming crystal nuclei selectively scatteringly on its surface is previously arranged to have said starting material (A) adsorbed onto the surface of said substrate to form an adsorbed layer (I) and the step of introducing a starting material (B) which is the other one into said film forming space, thereby causing surface reaction on said adsorption layer (I) to form a crystalline deposited film (I).
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: January 14, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Jinsho Matsuyama, Yutaka Hirai, Masao Ueki, Akira Sakai
  • Patent number: 5588995
    Abstract: A system for monitoring the growth of crystalline films on stationary or rotating substrates includes a combination of some or all of the elements including a photodiode sensor for detecting the intensity of incoming light and converting it to a measurable current, a lens for focusing the RHEED pattern emanating from the phosphor screen onto the photodiode, an interference filter for filtering out light other than that which emanates from the phosphor screen, a current amplifier for amplifying and convening the current produced by the photodiode into a voltage, a computer for receiving the amplified photodiode current for RHEED data analysis, and a graphite impregnated triax cable for improving the signal to noise ratio obtained while sampling a stationary or rotating substrate. A rotating stage for supporting the substrate with diametrically positioned electron beam apertures and an optically encoded shaft can also be used to accommodate rotation of the substrate during measurement.
    Type: Grant
    Filed: May 3, 1995
    Date of Patent: December 31, 1996
    Assignee: Midwest Research Institute
    Inventor: Peter Sheldon
  • Patent number: 5587014
    Abstract: There is provided a method for manufacturing group III-V compound semiconductors including at least Ga as the group III element and at least N as the group V element by using metal-organic compounds of group III elements having at least Ga in the molecules thereof and compounds having at least N in the molecules thereof as the raw materials, and the group III-V compound semiconductor crystals are grown in a reaction tube, and epitaxial layer of crystals are grown on a substrate made of a material different from that of the crystals to be grown, wherein at least one kind of gas, selected from a group consisting of compounds including halogen elements and group V elements and hydrogen halide, is introduced before the growth of the compound semiconductor crystal begins, thereby to carry out gas-phase etching of the inner wall surface of a reaction tube.
    Type: Grant
    Filed: December 21, 1994
    Date of Patent: December 24, 1996
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Yasushi Iyechika, Tomoyuki Takada
  • Patent number: 5582641
    Abstract: A crystal article comprises a substrate and single crystals provided on said substrate, with the shape of the contacted surface of said single crystals with said substrate being n-gonal (provided that n.gtoreq.5) or circular.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: December 10, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nobuhiko Sato
  • Patent number: 5562770
    Abstract: The present invention provides a method of global stress modification which results in reducing number of dislocations in an epitaxially grown semiconducting device layer on a semiconductor substrate where the device layer and the substrate have a lattice mismatch. The invention teaches a method of imparting a convex curvature to the substrate by removing layer(s) of thin film from or adding layers of thin film to the back side of the substrate, so as to achieve a reduced dislocation density in the device layer.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: October 8, 1996
    Assignee: International Business Machines Corporation
    Inventors: Bomy A. Chen, Terence B. Hook, Subhash B. Kulkarni
  • Patent number: 5556464
    Abstract: The present invention relates to a diamond vibration plate for a speaker having high sound velocity or E/.rho. and which is superior in high-pitched tone performance. Conventional diamond vibration plates which are made overall from crystalline diamond were apt to split or break at a flange due to the high rigidity. According to the present invention periphery of the flange is circularly cut by laser beams to eliminate rugged circumference. The laser treatment also converts the crystalline diamond of the flange into non-diamond carbon. The resulting vibration plate with a central spherical part of crystalline diamond and a periphery of a flange of non-diamond carbon excels both in high frequency property and mechanical strength.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: September 17, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiichiro Tanabe, Naoji Fujimori
  • Patent number: 5549749
    Abstract: The invention provides a semiconductor substrate comprising a substrate of a first material and a crystal growth layer formed on the substrate, the crystal growth layer being made of compound semiconductors different from the first material wherein the substrate has a surface diffusion region being heavily doped with one or more elements of the compound semiconductors. A silicon substrate receives an ion-implantation of one or more elements constituting a compound semiconductor different except for silicon at a high impurity concentration for a heat treatment at a higher temperature than a growth temperature of the compound semiconductor and subsequent cooling down to the growth temperature of the compound semiconductor followed by crystal growth of the compound semiconductor on the substrate.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: August 27, 1996
    Assignee: NEC Corporation
    Inventor: Shuji Asai
  • Patent number: 5512375
    Abstract: High quality epitaxial layers can be grown on a multi-layer substrate which has a crystalline pseudomorphic layer with an exposed surface used for the epitaxial growth. The pseudomorphic layer of the substrate has a thickness at or below the pseudomorphic limit so it will be deformed as stress forces are developed during epitaxial growth of heteroepitaxial structures. A plastically deformable layer is bonded to the pseudomorphic layer, This plastically deformable layer is made of material that plastically flows at epitaxial growth temperatures.
    Type: Grant
    Filed: October 14, 1993
    Date of Patent: April 30, 1996
    Assignee: Intevac, Inc.
    Inventors: Roger T. Green, Gary A. Davis, Verle W. Aebi
  • Patent number: 5492843
    Abstract: Method of fabricating a semiconductor device. A glass substrate such as Corning 7059 is used as a substrate. A bottom film is formed. Then, the substrate is annealed above the strain point of the glass substrate. The substrate is then slowly cooled below the strain point. Thereafter, a silicon film is formed, and a TFT is formed. The aforementioned anneal and slow cooling reduce shrinkage of the substrate created in later thermal treatment steps. This makes it easy to perform mask alignments. Furthermore, defects due to misalignment of masks are reduced, and the production yield is enhanced. In another method, a glass substrate made of Corning 7059 is also used as a substrate. The substrate is annealed above the strain point. Then, the substrate is rapidly cooled below the strain point. Thereafter, a bottom film is formed, and a TFT is fabricated. The aforementioned anneal and slow cooling reduce shrinkage of the substrate created in later thermal treatment steps.
    Type: Grant
    Filed: July 29, 1994
    Date of Patent: February 20, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Adachi, Yuugo Goto, Hongyong Zhang, Toru Takayama
  • Patent number: 5491106
    Abstract: A method for growing a compound semiconductor layer of Al.sub.x Ga.sub.1-x As (0.ltoreq.x.ltoreq.1) on a compound semiconductor substrate uses a molecular beam epitaxial apparatus, the method including the steps of providing the substrate having a GaAs layer on an upper surface thereof, thermally etching the GaAs layer by heating the substrate at a temperature and irradiating the GaAs layer with a gallium molecular beam and an arsenic molecular beam to expose the upper surface of the substrate, and growing the Al.sub.x Ga.sub.1-x As (0.ltoreq.x.ltoreq.1) layer on the upper surface of the substrate.
    Type: Grant
    Filed: July 23, 1993
    Date of Patent: February 13, 1996
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akinori Seki, Hiroyuki Hosoba, Toshio Hata, Masafumi Kondo, Takahiro Suyama, Sadayoshi Matsui
  • Patent number: 5485804
    Abstract: A method for creating a uniform thin film of a high surface energy material on a substrate comprising the steps of providing an oppositely charged surface on the substrate, if such does not exist, from that of particles of the high surface energy material, exposing the substrate to an aqueous colloidal suspension of particles composed of the high surface energy material to adsorb seed particles onto the surface of the substrate, and then depositing a uniform thin film of the high surface energy material by chemical vapor deposition onto the seeded substrate.
    Type: Grant
    Filed: May 17, 1994
    Date of Patent: January 23, 1996
    Assignee: University of Florida
    Inventors: James J. Adair, Rajiv K. Singh
  • Patent number: 5483920
    Abstract: A novel method of forming large area single crystal cubic boron nitride films on a silicon substrate by first treating the surface of the substrate with atomic hydrogen and then depositing a cubic boron nitride film by a reactive biased laser ablation technique.
    Type: Grant
    Filed: August 5, 1993
    Date of Patent: January 16, 1996
    Assignee: Board of Governors of Wayne State University
    Inventor: Roger W. Pryor
  • Patent number: 5462012
    Abstract: A novel substrate for growth of material by chemical phase deposition includes a temperature monitoring zone formed by applying a coating of growth preventing material (e.g., SiO.sub.x or SiN.sub.x) to a portion of the substrate. The temperature of the substrate can be monitored during growth of a desired material using an optical pyrometer having its field of view directed at the temperature monitoring zone.
    Type: Grant
    Filed: November 29, 1994
    Date of Patent: October 31, 1995
    Assignee: AT&T Corp.
    Inventor: Tien-Heng Chiu
  • Patent number: 5425808
    Abstract: A process for selective formation of a III-V group compound film comprises applying a compound film forming treatment, in a gas phase including a starting material for supplying the group III atoms of Periodic Table and a starting material for supplying the group V atoms of Periodic Table, on a substrate having a non-nucleation surface (S.sub.NDS) with small nucleation density and a nucleation surface (S.sub.NDL) with a larger nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said non-nucleation surface (S.sub.NDS) and a large area sufficient for a number of nuclei to be formed, and forming selectively a III-V group compound film only on said nucleation surface (S.sub.NDL).
    Type: Grant
    Filed: October 29, 1993
    Date of Patent: June 20, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroyuki Tokunaga, Takao Yonehara
  • Patent number: 5423286
    Abstract: A method for forming a crystal comprises applying a crystal growth treatment to a substrate comprising:a non-nucleation surface; anda nucleation surface constituted of an amorphous material with a higher nucleation density than said non-nucleation surface, having a sufficiently small area so as to form only a single nucleus from which a single crystal is grown, and having regular anisotropy.Also a crystal article is formed by said method for forming a crystal.
    Type: Grant
    Filed: May 19, 1994
    Date of Patent: June 13, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takao Yonehara
  • Patent number: 5422306
    Abstract: A method is disclosed of forming semiconductor hetero interfaces that will contribute to the performance improvement of devices having semiconductor hetero interfaces such as MOS transistors, quantum devices, capacitors and the like. The method comprises the steps of making the surface of a semiconductor substrate clean and flat in terms of atomic level by heating said semiconductor substrate in vacuum to a temperature at which reconstruction of the surface atoms of said semiconductor substrate takes place, then forming a structural buffer layer such as a native oxide layer and the like on said semiconductor substrate surface after the temperature of said semiconductor substrate was lowered to room temperature and finally subjecting the semiconductor substrate with said structural buffer layer formed on its surface to a thermal treatment performed in certain specified temperature and atmosphere.
    Type: Grant
    Filed: December 15, 1992
    Date of Patent: June 6, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaaki Niwa, Masaharu Udagawa, Yoshihiko Hirai, Juurou Yasui
  • Patent number: 5396862
    Abstract: A compound semiconductor thin film is grown on a compound semiconductor surface, which is cleaned by irradiating the surface with gas containing at least hydrogen molecules and by efficiently removing contaminant on the surface at low temperature. A beam containing at least hydrogen molecules is irradiated from a plasma generating room attached to a MBE chamber, and cleans the surface of a compound semiconductor at low temperature. By an additional mechanism attached to the MBE chamber, a compound semiconductor thin film of high quality is grown on the cleaned surface of the compound semiconductor.
    Type: Grant
    Filed: November 15, 1993
    Date of Patent: March 14, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiro Okawa, Shigeo Hayashi, Takeshi Karasawa, Tsuneo Mitsuyu
  • Patent number: 5373806
    Abstract: Particles and particle-generated defects during gas phase processing such as during epitaxial deposition are substantially decreased by the process of controlling the various particle transport mechanisms, for example, by applying low level radiant energy during cold purge cycles in barrel reactors.
    Type: Grant
    Filed: March 14, 1994
    Date of Patent: December 20, 1994
    Assignee: Applied Materials, Inc.
    Inventor: Roger E. Logar
  • Patent number: 5363800
    Abstract: This invention is a method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.
    Type: Grant
    Filed: November 9, 1992
    Date of Patent: November 15, 1994
    Assignee: The United States of America as represented by the United States National Aeronautics and Space Administration
    Inventors: David J. Larkin, Powell, J. Anthony
  • Patent number: 5364815
    Abstract: A crystal article comprises;a substrate having i) a nonnucleation surface (S.sub.NDS) having a small nucleation density, ii) at least one single-nucleation surface (S.sub.NDL -S) provided adjacent to said nonnucleation surface (S.sub.NDS), having an area small enough for a crystal to grow from only a single nucleus and having a larger nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said nonnucleation surface (S.sub.NDS), and iii) at least one multiple-nucleation surface (S.sub.NDL -M) having an area large enough for crystals to grow from plural nuclei and having a larger nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said nonnucleation surface (S.sub.NDS);at least one monocrystal grown from said single nucleus and extending over said single-nucleation surface (S.sub.NDL -S) to cover part of said nonnucleation surface (S.sub.NDS); anda polycrystalline film grown from said plural nuclei to cover said multiple-nucleation surface.
    Type: Grant
    Filed: February 17, 1993
    Date of Patent: November 15, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoshiyuki Osada
  • Patent number: 5363799
    Abstract: A method for growth of a crystal wherein a monocrystalline seed is arranged on a substrate and a monocrystal is permitted to grow with the seed as the originating point, comprises the step of:(1) providing a substrate having a surface of smaller nucleation density;(2) arranging on the surface of the substrate primary seeds having sufficiently fine surface area to be agglomerated;(3) applying heat treatment to the primary seeds to cause agglomeration to occur, thereby forming a monocrystalline seed with a controlled face orientation; and(4) applying crystal growth treatment to permit a monocrystal to grow with the monocrystalline seed as the originating point.
    Type: Grant
    Filed: November 19, 1992
    Date of Patent: November 15, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Yuji Nishigaki, Kenji Yamagata
  • Patent number: 5316615
    Abstract: The present invention broadly concerns layered structures of substantially-crystalline materials and processes for making such structures. More particularly, the invention concerns epitaxial growth of a substantially-crystalline layer of a first material on a substantially-crystalline second material different from the first material.
    Type: Grant
    Filed: March 9, 1993
    Date of Patent: May 31, 1994
    Assignee: International Business Machines Corporation
    Inventors: Matthew W. Copel, Rudolf M. Tromp
  • Patent number: 5308444
    Abstract: The invention is predicated upon the discovery by applicants that exposure of a Ge surface to arsenic produces a drastic change in the step structure of the Ge surface. Subsequent exposure to Ga and growth of GaAs produces three-dimensional growth and a high threading dislocation density at the GaAs/Ge interface. However exposure of the Ge surface to Ga does not substantially change the Ge step structure, and subsequent growth of GaAs is two-dimensional with little increase in threading dislocation density. Thus a high quality semiconductor heterostructure of gallium arsenide on germanium can be made by exposing a germanium surface in an environment substantially free of arsenic, depositing a layer of gallium on the surface and then growing a layer of gallium arsenide. The improved method can be employed to make a variety of optoelectronic devices such as light-emitting diodes.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: May 3, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Eugene A. Fitzgerald, Jr., Jenn-Ming Kuo, Paul J. Silverman, Ya-Hong Xie