Epitaxy Formation Patents (Class 117/9)
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Patent number: 11923466Abstract: A photodetector with an integrated reflective grating structure includes a substrate, an active layer disposed on the substrate, and a grating structure disposed between the substrate and the active layer. A first doped region is formed on the substrate at a location near the grating structure. A second doped region is formed on a surface of the active layer away from the grating structure. The doping type of the second doped region is different from that of the first doped region.Type: GrantFiled: March 3, 2020Date of Patent: March 5, 2024Assignee: INNOLIGHT TECHNOLOGY (SUZHOU) LTD.Inventors: Chih-Kuo Tseng, Guoliang Chen, Xiaoyao Li, Yuzhou Sun, Yue Xiao
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Patent number: 11827525Abstract: The method of fabricating metal oxide nanomaterials using a thermally decomposable substrate can include combining an aqueous solution including a metal salt with a thermally decomposable solid substrate. In an embodiment, the aqueous solution can be nebulized and applied directly on the solid substrate. In an embodiment, the solid substrate can be macerated in the aqueous solution. The solid material, once combined with the aqueous solution, can then be calcined at a temperature ranging from about 400° C. to about 900° C. Calcination produces metal oxide nanoparticles and transforms the solid material into capping substrate molecules that are separated by the metal oxide ions. Thus, the metal oxide nanomaterials include capping substrate molecules separated by metal oxide nanoparticles. The present method reverses the conventional capping process by placing the metal oxide ions between the molecules of the capping substrate, which stay in place (keeping distance between ions), even during calcination.Type: GrantFiled: September 7, 2022Date of Patent: November 28, 2023Assignee: IMAM MOHAMMAD IBN SAUD ISLAMIC UNIVERSITYInventors: Babiker Yagoub Elhadi Abdulkhair, Mohamed Rahamtalla Elamin
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Patent number: 11774914Abstract: A one-piece silicon device with flexible blades (2, 3), in particular for timepieces, for example a pivot with crossed blades, and to a method for manufacturing the device (1). The method includes: forming (21) a one-piece silicon device (1) blank from a wafer of the SOI type, the device (1) including two flexible blades (2, 3), each formed in a different layer of the SOI wafer, the blades (2, 3) being arranged in two different substantially parallel planes, the blades (2, 3) being separated by a clearance (7); growing a first silicon oxide layer on the surface of at least one of the blades (2, 3) bordering the clearance, the first silicon oxide layer being formed from a first sub-layer of silicon of the one or more blades (2, 3); and removing the first silicon oxide layer to increase the clearance (7) between the two blades (2, 3).Type: GrantFiled: January 14, 2021Date of Patent: October 3, 2023Assignee: Nivarox-FAR S.A.Inventors: Pierre Cusin, Alex Gandelhman
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Patent number: 11454933Abstract: A timepiece regulating mechanism including primary resonators each with an inertial weight suspended by flexible strips to a fixed structure with respect to which this weight pivots, and mechanical device of synchronizing the primary resonators which include, between the inertial weights, an articulated connection which, under normal conditions, allows pivoting of the inertial weights in opposite directions of rotation and with close rotation angles, and during a shock, prevents pivoting thereof in the same direction of rotation, the mechanism including an oscillator with a frictional rest escapement mechanism arranged to cooperate alternately with the primary resonators, on pallet stones of the inertial weights.Type: GrantFiled: March 26, 2019Date of Patent: September 27, 2022Assignee: The Swatch Group Research and Development LtdInventors: Jean-Jacques Born, Pascal Winkler, Gianni Di Domenico
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Patent number: 11286543Abstract: Some variations provide an additively manufactured aluminum alloy comprising from 84.5 wt % to 92.1 wt % aluminum; from 1.1 wt % to 2.1 wt % copper; from 1.8 wt % to 2.9 wt % magnesium; from 4.5 wt % to 6.1 wt % zinc; and from 0.5 wt % to 2.8 wt % zirconium. The additively manufactured aluminum alloy is in the form of a three-dimensional component. The zirconium functions as a grain-refiner element within the additively manufactured aluminum alloy. The additively manufactured aluminum alloy may be characterized by an average grain size of less than 10 microns. The additively manufactured aluminum alloy may have a substantially crack-free microstructure with equiaxed grains.Type: GrantFiled: January 30, 2019Date of Patent: March 29, 2022Assignee: HRL Laboratories, LLCInventors: John H. Martin, Brennan Yahata
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Patent number: 11141809Abstract: A method and apparatus particularly for additively manufacturing materials that are susceptible to hot cracking. The additive manufacturing process may include a leading energy beam (16) for liquefying a raw material to form a melt pool (20), and a trailing energy beam (17) directed toward a trailing region of the melt pool. The trailing energy beam may be configured to enhance agitation and/or redistribution of liquid in the melt pool to prevent hot cracking, reduce porosity, or improve other characteristics of the solidified part. The method and apparatus also may improve processing parameters, such as adjusting vacuum level to prevent volatilization of alloying agents, or providing a chill plate to control interpass temperature. The process may be used to form new articles, and also may be used to enhance tailorability and flexibility in design or repair of pre-existing articles, among other considerations.Type: GrantFiled: December 1, 2016Date of Patent: October 12, 2021Assignee: Raytheon CompanyInventors: Norman Dana Nelson, Curtis B. Carlsten, Mark J. Pistorino
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Patent number: 10607589Abstract: The application relates to a nonwoven composite containing a lofty nonwoven layer and a film. The lofty nonwoven layer contains a plurality of primary fibers and defines a plurality of peak regions and a plurality of valley regions. The film contains a thermoplastic polymer and has a peak film thickness in the peak regions of the layer. The film is present on at least a majority of the second surface of the nonwoven layer. Within the valley regions, the film encapsulates a plurality of fibers from the nonwoven layer. The cross-sectional area fraction of total fibers in the film within the valley regions is at least about 8% and the cross-sectional area fraction of total fibers in the film within the peak regions is less than about 5%.Type: GrantFiled: November 29, 2016Date of Patent: March 31, 2020Assignee: Milliken & CompanyInventors: Sara A. Arvidson, Ryan W. Johnson, Randolph S. Kohlman, Patrick A. Petri
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Patent number: 10068981Abstract: Methods of doping semiconductor substrates using deposition of a rare earth metal-containing film such as an yttrium-containing film, and annealing techniques are provided herein. Rare earth metal-containing films are deposited using gas, liquid, or solid precursors without a bias and may be deposited conformally. Some embodiments may involve deposition using a plasma. Substrates may be annealed at temperatures less than about 500° C.Type: GrantFiled: March 2, 2016Date of Patent: September 4, 2018Assignee: Lam Research CorporationInventors: Yunsang Kim, Reza Arghavani
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Patent number: 9899211Abstract: A method of manufacturing a semiconductor device, includes: forming a film on a substrate by performing a cycle a predetermined number of times, the cycle including: supplying a raw material gas to a substrate in a process chamber, exhausting the raw material gas remaining in the process chamber through an exhaust line, supplying an amine-based gas; and exhausting the amine-based gas through the exhaust line with the supply of the amine-based gas stopped. A degree of valve opening of an exhaust valve disposed in the exhaust line is changed in multiple steps in the process of exhausting the amine-based gas.Type: GrantFiled: February 4, 2015Date of Patent: February 20, 2018Assignee: HITACHI KOKUSAI ELECTRIC, INC.Inventors: Kaori Kirikihira, Yugo Orihashi, Satoshi Shimamoto
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Patent number: 9435222Abstract: Known protective layers having high Cr content and additional silicon form brittle phases, which additionally become brittle under the effect of carbon during use. The protective layer according to the invention comprises a two-part metal layer, which contains tantalum on the outside.Type: GrantFiled: July 8, 2011Date of Patent: September 6, 2016Assignee: SIEMENS AKTIENGESELLSCHAFTInventors: Georg Bostanjoglo, Axel Kaiser, Werner Stamm, Jan Steinbach, Dimitrios Thomaidis
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Patent number: 9242433Abstract: The present invention relates to a textured substrate for epitaxial film formation, comprising a textured metal layer at least on one side, wherein the textured metal layer includes a copper layer having a cube texture and a nickel layer having a thickness of 100 to 20000 nm formed on the copper layer; the nickel layer has a nickel oxide layer formed on a surface thereof, having a thickness of 1 to 30 nm, and including a nickel oxide; and the nickel layer further includes a palladium-containing region formed of palladium-containing nickel at an interface with the nickel oxide layer. The top layer of the textured substrate, i.e. the nickel oxide layer, has a surface roughness of preferably 10 nm or less.Type: GrantFiled: March 21, 2013Date of Patent: January 26, 2016Assignee: TANAKA KIKINZOKU KOGYO K.K.Inventors: Naoji Kashima, Tomonori Watanabe, Shigeo Nagaya, Kunihiro Shima, Shuichi Kubota
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Patent number: 9034104Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A single-component oxide semiconductor layer is formed over a substrate; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a single-component oxide semiconductor layer including single crystal regions is formed; and a multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.Type: GrantFiled: December 15, 2010Date of Patent: May 19, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takuya Hirohashi, Masahiro Takahashi, Takashi Shimazu
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Patent number: 9034102Abstract: A method of fabricating a hybrid orientation substrate is described. A silicon substrate with a first orientation having a silicon layer with a second orientation directly thereon is provided, and then a stress layer is formed on the silicon layer. A trench is formed between a first portion and a second portion of the silicon layer through the stress layer and into the substrate. The first portion of the silicon layer is amorphized. A SPE process is performed to recrystallize the amorphized first portion of the silicon layer to be a recrystallized layer with the first orientation. An annealing process is performed at a temperature lower than 1200° C. to convert a surface layer of the second portion of the silicon layer to a strained layer. The trench is filled with an insulating material after the SPE process or the annealing process, and the stress layer is removed.Type: GrantFiled: March 29, 2007Date of Patent: May 19, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yao-Tsung Huang, Chien-Ting Lin, Che-Hua Hsu, Guang-Hwa Ma
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Patent number: 8956453Abstract: The present invention provides a method for providing a crystalline germanium layer on a crystalline base substrate having a crystalline surface. The method comprises cleaning the base substrate for removing contaminants and/or native oxides from the surface, providing an amorphous germanium layer on the surface of the base substrate while exposing to the base substrate to a hydrogen source such as e.g. a hydrogen plasma, a H2 flux or hydrogen originating from dissociation of GeH4 and/or to a non-reactive gas source such as N2, He, Ne, Ar, Kr, Xe, Rn or mixtures thereof, and crystallizing the amorphous germanium layer by annealing the base substrate so as to provide a crystalline germanium layer.Type: GrantFiled: July 18, 2008Date of Patent: February 17, 2015Assignees: IMEC, Vrije Universiteit BrusselInventors: Ruben Lieten, Stefan Degroote
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Patent number: 8956960Abstract: According to an embodiment, a method for stress-reduced forming a semiconductor device includes: providing a semiconductor wafer including an upper side and a first semiconductor layer of a first semiconductor material at the upper side; forming, in a vertical cross-section which is substantially orthogonal to the upper side, at the upper side a plurality of first vertical trenches and a plurality of second vertical trenches between adjacent first vertical trenches so that the first vertical trenches have, in the vertical cross-section, a larger horizontal extension than the second vertical trenches; and forming a plurality of third semiconductor layers at the upper side which are, in the vertical cross-section, spaced apart from each other by gaps each of which overlaps, in the vertical cross-section, with a respective first vertical trench when seen from above. At least one of the third semiconductor layers includes a semiconductor material which is different to the first semiconductor material.Type: GrantFiled: November 16, 2012Date of Patent: February 17, 2015Assignee: Infineon Technologies AGInventors: Peter Irsigler, Hans-Joachim Schulze
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Patent number: 8945301Abstract: A method for producing a diamond material by contacting a fluorinated precursor with a hydrocarbon in a reactor and forming a combination in the absence of a metal catalyst; increasing the pressure of the reactor to a first pressure; heating the combination under pressure to form a material precursor; cooling the material precursor; and forming a diamond material.Type: GrantFiled: August 5, 2011Date of Patent: February 3, 2015Assignee: University of Houston SystemInventors: Valery N. Khabashesku, Valery A. Davydov, Alexandra V. Rakhmanina
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Patent number: 8894765Abstract: A PIN-PMN-PT ferroelectric single crystal and a method of manufacture are disclosed. The PIN-PMN-PT ferroelectric single crystal is oriented and polarized along a single crystallographic direction. The PIN-PMN-PT ferroelectric single crystal ferroelectric has increased remnant polarization.Type: GrantFiled: November 12, 2010Date of Patent: November 25, 2014Assignee: TRS Technologies, Inc.Inventors: Wesley S. Hackenberger, Edward F. Alberta
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Publication number: 20140338586Abstract: The present invention provides a method capable of stably producing a zinc oxide single crystal in which a large amount of dopant forms a solid solution at a high level of productivity and reproducibility without using a harmful substance. The method of the present invention comprises providing a raw material powder that is mainly composed of zinc oxide, comprises at least one dopant element selected from B, Al, Ga, In, C, F, Cl, Br, I, H, Li, Na, K, N, P, As, Cu, and Ag in a total amount of 0.01 to 1 at %, and is substantially free of a crystal phase other than zinc oxide, and injecting the raw material powder to form a film mainly composed of zinc oxide on a seed substrate comprising a zinc oxide single crystal and also to crystallize the formed film in a solid phase state.Type: ApplicationFiled: August 7, 2014Publication date: November 20, 2014Inventors: Jun YOSHIKAWA, Katsuhiro IMAI
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Patent number: 8871022Abstract: The disclosed subject matter relates to the use of laser crystallization of thin films to create epitaxially textured crystalline thick films. In one or more embodiments, a method for preparing a thick crystalline film includes providing a film for crystallization on a substrate, wherein at least a portion of the substrate is substantially transparent to laser irradiation, said film including a seed layer having a predominant surface crystallographic orientation; and a top layer disposed above the seed layer; irradiating the film from the back side of the substrate using a pulsed laser to melt a first portion of the top layer at an interface with the seed layer while a second portion of the top layer remains solid; and re-solidifying the first portion of the top layer to form a crystalline laser epitaxial with the seed layer thereby releasing heat to melt an adjacent portion of the top layer.Type: GrantFiled: October 14, 2013Date of Patent: October 28, 2014Assignee: The Trustees of Columbia University in the City of New YorkInventor: James S. Im
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Publication number: 20140284547Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.Type: ApplicationFiled: March 21, 2013Publication date: September 25, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
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Patent number: 8840720Abstract: An apparatus for manufacturing a polycrystalline silicon thin film, including a crystallization container filled with silicon oil, crystallization electrodes spaced apart from the crystallization container, and a conductive plate positioned between the crystallization electrodes and connected with the crystallization electrodes. Because an insulating layer between the amorphous silicon thin film and the conductive plate is formed by using silicon oil filled within the crystallization container, Joule-heating induced crystallization (JIC) can be performed through a simpler manufacturing process.Type: GrantFiled: December 8, 2010Date of Patent: September 23, 2014Assignee: Samsung Display Co., Ltd.Inventor: Cheol-Su Kim
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Patent number: 8747982Abstract: A method is used for producing an SiC volume monocrystal by sublimation growth. Before the beginning of growth, an SiC seed crystal is arranged in a crystal growth region of a growth crucible and powdery SiC source material is introduced into an SiC storage region of the growth crucible. During the growth, by sublimation of the powdery SiC source material and by transport of the sublimated gaseous components into the crystal growth region, an SiC growth gas phase is produced there. The SiC volume monocrystal having a central center longitudinal axis grows by deposition from the SiC growth gas phase on the SiC seed crystal. The SiC seed crystal is heated substantially without bending during a heating phase before the beginning of growth, so that an SiC crystal structure with a substantially homogeneous course of lattice planes is provided in the SiC seed crystal.Type: GrantFiled: December 28, 2011Date of Patent: June 10, 2014Assignee: SiCrystal AktiengesellschaftInventors: Thomas Straubinger, Michael Vogel, Andreas Wohlfart
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Patent number: 8734583Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (SPE) process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The fin has a cross-sectional thickness in at least one direction less than a minimum feature size. The transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.Type: GrantFiled: April 4, 2006Date of Patent: May 27, 2014Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 8696808Abstract: Each region, which should be left on a substrate after patterning, of a semiconductor film is grasped in accordance with a mask. Then, each region to be scanned with laser light is determined so that at least the region to be obtained through the patterning is crystallized, and a beam spot is made to hit the region to be scanned, thereby partially crystallizing the semiconductor film. Each portion with low output energy of the beam spot is shielded by a slit. In the present invention, the laser light is not scanned and irradiated onto the entire surface of the semiconductor film but is scanned such that at least each indispensable portion is crystallized to a minimum. With the construction described above, it becomes possible to save time taken to irradiate the laser light onto each portion to be removed through the patterning after the crystallization of the semiconductor film.Type: GrantFiled: September 5, 2006Date of Patent: April 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Masaaki Hiroki, Koichiro Tanaka, Aiko Shiga, Satoshi Murakami, Mai Akiba
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Patent number: 8663387Abstract: A method and system for processing at least one portion of a thin film sample on a substrate, with such portion of the film sample having a first boundary and a second boundary. One or more first areas of the film sample are successively irradiated by first beamlets of an irradiation beam pulse so that the first areas are melted throughout their thickness and allowed to re-solidify and crystallize thereby having grains grown therein. Thereafter, one or more second areas of the film sample are irradiated by second beamlets so that the second areas are melted throughout their thickness. At least two of the second areas partially overlap a particular area of the re-solidified and crystallized first areas such that the grains provided in the particular area grow into each of the at least two second areas upon re-solidification thereof.Type: GrantFiled: March 9, 2006Date of Patent: March 4, 2014Assignee: The Trustees of Columbia University in the City of New YorkInventor: James S. Im
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Publication number: 20140017883Abstract: A system and method for manufacturing a carbon layer is provided. An embodiment comprises depositing a first metal layer on a substrate, the substrate comprising carbon. A silicide is eptiaxially grown on the substrate, the epitaxially growing the silicide also forming a layer of carbon over the silicide. In an embodiment the carbon layer is graphene, and may be transferred to a semiconductor substrate for further processing to form a channel within the graphene.Type: ApplicationFiled: July 11, 2012Publication date: January 16, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Markvan Dal
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Patent number: 8617313Abstract: A system for preparing a semiconductor film, the system including: a laser source; optics to form a line beam, a stage to support a sample capable of translation; memory for storing a set of instructions, the instructions including irradiating a first region of the film with a first laser pulse to form a first molten zone, said first molten zone having a maximum width (Wmax) and a minimum width (Wmin), wherein the first molten zone crystallizes to form laterally grown crystals; laterally moving the film in the direction of lateral growth a distance greater than about one-half Wmax and less than Wmin; and irradiating a second region of the film with a second laser pulse to form a second molten zone, wherein the second molten zone crystallizes to form laterally grown crystals that are elongations of the crystals in the first region, wherein laser optics provide Wmax less than 2×Wmin.Type: GrantFiled: July 12, 2012Date of Patent: December 31, 2013Assignee: The Trustees of Columbia University in the City of New YorkInventors: James S. Im, Paul C. Van Der Wilt
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Publication number: 20130333611Abstract: A lattice matching layer for use in a multilayer substrate structure comprises a lattice matching layer. The lattice matching layer includes a first chemical element and a second chemical element. Each of the first and second chemical elements has a hexagonal close-packed structure at room temperature that transforms to a body-centered cubic structure at an ?-? phase transition temperature higher than the room temperature. The hexagonal close-packed structure of the first chemical element has a first lattice parameter. The hexagonal close-packed structure of the second chemical element has a second lattice parameter. The second chemical element is miscible with the first chemical element to form an alloy with a hexagonal close-packed structure at the room temperature. A lattice constant of the alloy is approximately equal to a lattice constant of a member of group III-V compound semiconductors.Type: ApplicationFiled: March 11, 2013Publication date: December 19, 2013Applicant: Tivra CorporationInventors: Indranil De, Francisco Machuca
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Patent number: 8580031Abstract: A method of producing a three-dimensional photonic crystal by laminating a layer having a periodic structure, the method including the steps of forming a first structure and a second structure each including the layer having the periodic structure; and bonding a first bonding layer of the first structure and a second bonding layer of the second structure. The first bonding layer is one layer obtained by dividing a layer constituting the three-dimensional photonic crystal at a cross section perpendicular to a lamination direction, and the second bonding layer is the other layer obtained by dividing the layer constituting the three-dimensional photonic crystal at the cross section perpendicular to the lamination direction.Type: GrantFiled: April 6, 2010Date of Patent: November 12, 2013Assignee: Canon Kabushiki KaishaInventors: Aihiko Numata, Hikaru Hoshi, Kenji Tamamori
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Patent number: 8557040Abstract: The disclosed subject matter relates to the use of laser crystallization of thin films to create epitaxially textured crystalline thick films. In one or more embodiments, a method for preparing a thick crystalline film includes providing a film for crystallization on a substrate, wherein at least a portion of the substrate is substantially transparent to laser irradiation, said film including a seed layer having a predominant surface crystallographic orientation; and a top layer disposed above the seed layer; irradiating the film from the back side of the substrate using a pulsed laser to melt a first portion of the top layer at an interface with the seed layer while a second portion of the top layer remains solid; and re-solidifying the first portion of the top layer to form a crystalline laser epitaxial with the seed layer thereby releasing heat to melt an adjacent portion of the top layer.Type: GrantFiled: November 21, 2008Date of Patent: October 15, 2013Assignee: The Trustees of Columbia University in the City of New YorkInventor: James S. Im
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Publication number: 20130263771Abstract: A crystal production method according to the present invention includes a film formation and crystallization step of spraying a raw material powder containing a raw material component to form a film containing the raw material component on a seed substrate containing a single crystal at a predetermined single crystallization temperature at which single crystallization of the raw material component occurs, and crystallizing the film containing the raw material while maintaining the single crystallization temperature. In the film formation and crystallization step, preferably, the single crystallization temperature is 900° C. or higher. Furthermore, in the film formation and crystallization step, preferably, the raw material powder and the seed substrate are each a nitride or an oxide.Type: ApplicationFiled: April 19, 2013Publication date: October 10, 2013Inventors: Nobuyuki KOBAYASHI, Kazuki MAEDA, Koichi KONDO, Tsutomu NANATAKI, Katsuhiro IMAI, Jun YOSHIKAWA
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Patent number: 8551246Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.Type: GrantFiled: May 7, 2009Date of Patent: October 8, 2013Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
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Patent number: 8475588Abstract: A wafer structure and epitaxial growth method for growing the same. The method may include forming a mask layer having nano-sized areas on a wafer, forming a porous layer having nano-sized pores on a surface of the wafer by etching the mask layer and a surface of the wafer, and forming an epitaxial material layer on the porous layer using an epitaxial growth process.Type: GrantFiled: March 13, 2009Date of Patent: July 2, 2013Assignee: Samsung Corning Precision Materials Co., Ltd.Inventor: Sung-Soo Park
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Patent number: 8470089Abstract: The invention relates to a process for manufacturing a single crystal comprising a rare-earth halide, having improved machining or cleavage behavior, comprising heat treatment in a furnace, the atmosphere of which is brought, for at least 1 hour, to between 0.70 times Tm and 0.995 times Tm of a single crystal comprising a rare-earth halide, Tm representing the melting point of said single crystal, the temperature gradient at any point in the atmosphere of the furnace being less than 15 K/cm for said heat treatment. After carrying out the treatment according to the invention, the single crystals may be machined or cleaved without uncontrolled fracture. The single crystals may be used in a medical imaging device, especially a positron emission tomography system or a gamma camera or a CT scanner, for crude oil exploration, for detection and identification of fissile or radioactive materials, for nuclear and high-energy physics, for astrophysics or for industrial control.Type: GrantFiled: May 15, 2008Date of Patent: June 25, 2013Assignee: Saint-Gobain Cristaux et DetecteursInventors: Dominique Richaud, Alain Iltis, Vladimir Ouspenski
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Patent number: 8460461Abstract: The present invention provides an oriented substrate for forming an epitaxial thin film thereon, which has a more excellent orientation than that of a conventional one and a high strength, and a method for manufacturing the same. The present invention provides a clad textured metal substrate for forming the epitaxial thin film thereon, which includes a metallic layer and a silver layer bonded to at least one face of the metallic layer, wherein the silver layer has a {100}<001> cube texture in which a deviating angle ?? of crystal axes satisfies ???9 degree. The textured metal substrate can be manufactured by subjecting the silver sheet containing 30 to 200 ppm oxygen by concentration to the orienting treatment of hot-working and heat-treating, and bonding the metal sheet with the oriented silver sheet by using a surface activated bonding process.Type: GrantFiled: August 15, 2012Date of Patent: June 11, 2013Assignees: Chubu Electric Power Co., Ltd., Tanaka Kikinzoku Kogyo. K.K.Inventors: Naoji Kashima, Shigeo Nagaya, Kunihiro Shima, Hirofumi Hoshino
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Patent number: 8449671Abstract: A method of fabricating an SiC single crystal includes (a) physical vapor transport (PVT) growing a SiC single crystal on a seed crystal in the presence of a temperature gradient, wherein an early-to-grow portion of the SiC single crystal is at a lower temperature than a later-to-grow portion of the SiC single crystal. Once grown, the SiC single crystal is annealed in the presence of a reverse temperature gradient, wherein the later-to-grow portion of the SiC single crystal is at a lower temperature than the early-to-grow portion of the SiC single crystal.Type: GrantFiled: June 26, 2008Date of Patent: May 28, 2013Assignee: II-VI IncorporatedInventors: Ping Wu, Ilya Zwieback, Avinesh K. Gupta, Edward Semenas
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Publication number: 20130126793Abstract: [Problems] To provide a vapor-grown carbon fiber aggregate, wherein the carbon fiber has a structure of two or more tubular graphene layers and of which the central portion in cross section of the fiber is hollow, has a little unevenness in the structure and exhibits excellent electric conductivity. [Means for Solution] A vapor-grown carbon fiber aggregate, wherein the carbon fiber has a structure of two or more tubular graphene layers and of which the central portion in cross section of the fiber is hollow, the average outer fiber diameter of the carbon fibers is from 10 to 300 nm, and not less than 70% of the whole number of the carbon fibers have hollow diameters of from 2 to 20 nm and hollow diameter/outer fiber diameter ratios of from 1.4 to 20%.Type: ApplicationFiled: July 29, 2011Publication date: May 23, 2013Applicant: HODOGAYA CHEMICAL CO., LTD.Inventors: Yoshinori Hitoe, Jun Suzuki, Hiroshi Sato, Shoji Kawashima
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Patent number: 8394194Abstract: A method of forming a layer of amorphous silicon oxide positioned between a layer of rare earth oxide and a silicon substrate. The method includes providing a crystalline silicon substrate and depositing a layer of rare earth metal on the silicon substrate in an oxygen deficient ambient at a temperature above approximately 500° C. The rare earth metal forms a layer of rare earth silicide on the substrate. A first layer of rare earth oxide is deposited on the layer of rare earth silicide with a structure and lattice constant substantially similar to the substrate. The structure is annealed in an oxygen ambience to transform the layer of rare earth silicide to a layer of amorphous silicon and an intermediate layer of rare earth oxide between the substrate and the first layer of rare earth oxide.Type: GrantFiled: June 13, 2012Date of Patent: March 12, 2013Inventors: Rytis Dargis, Andrew Clark, Robin Smith, Michael Lebby
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Patent number: 8382894Abstract: Silicon wafers wherein slip dislocations and warpages during device production are suppressed, contain BMDs with an octahedral shape, and of BMDs at a depth greater than 50 ?m from the surface of the wafer, the density of BMDs with diagonal size of 10 nm to 50 nm is ?1×1012/cm3, and the density of BSFs is ?1×108/cm3. The present silicon wafers preferably have an interstitial oxygen concentration of 4×1017 atoms/cm3 to 6×1017 atoms/cm3, and a density of BMDs with diagonal size of ?200 nm of not more than 1×107/cm3.Type: GrantFiled: October 26, 2009Date of Patent: February 26, 2013Assignee: Siltronic AGInventors: Katsuhiko Nakai, Masayuki Fukuda
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Patent number: 8328936Abstract: A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.Type: GrantFiled: October 18, 2011Date of Patent: December 11, 2012Assignee: Nippon Telegraph and Telephone CorporationInventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
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Patent number: 8323402Abstract: Methods of growing and manufacturing aluminum nitride crystal, and aluminum nitride crystal produced by the methods. Preventing sublimation of the starting substrate allows aluminum nitride crystal of excellent crystallinity to be grown at improved growth rates. The aluminum nitride crystal growth method includes the following steps. Initially, a laminar baseplate is prepared, furnished with a starting substrate having a major surface and a back side, a first layer formed on the back side, and a second layer formed on the first layer. Aluminum nitride crystal is then grown onto the major surface of the starting substrate by vapor deposition. The first layer is made of a substance that at the temperatures at which the aluminum nitride crystal is grown is less liable to sublimate than the starting substrate. The second layer is made of a substance whose thermal conductivity is higher than that of the first layer.Type: GrantFiled: December 19, 2008Date of Patent: December 4, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keisuke Tanizaki, Naho Mizuhara, Michimasa Miyanaga, Hideaki Nakahata, Yoshiyuki Yamamoto
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Patent number: 8287643Abstract: The present invention provides an oriented substrate for forming an epitaxial thin film thereon, which has a more excellent orientation than that of a conventional one and a high strength, and a method for manufacturing the same. The present invention provides a clad textured metal substrate for forming the epitaxial thin film thereon, which includes a metallic layer and a silver layer bonded to at least one face of the metallic layer, wherein the silver layer has a {100}<001> cube texture in which a deviating angle ?? of crystal axes satisfies ???9 degree. The textured metal substrate can be manufactured by subjecting the silver sheet containing 30 to 200 ppm oxygen by concentration to the orienting treatment of hot-working and heat-treating, and bonding the metal sheet with the oriented silver sheet by using a surface activated bonding process.Type: GrantFiled: April 11, 2008Date of Patent: October 16, 2012Assignees: Chubu Electric Power Co., Inc., Tanaka Kikinzoku Kogyo K.K.Inventors: Naoji Kashima, Shigeo Nagaya, Kunihiro Shima, Hirofumi Hoshino
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Patent number: 8287642Abstract: Devices and methods for providing stimulated Raman lasing are provided. In some embodiments, devices include a photonic crystal that includes a layer of silicon having a lattice of holes and a linear defect that forms a waveguide configured to receive pump light and output Stokes light through Raman scattering, wherein the thickness of the layer of silicon, the spacing of the lattice of holes, and the size of the holes are dimensioned to provide Raman lasing. In some embodiments, methods include forming a layer of silicon, and etching the layer of silicon to form a lattice of holes with a linear defect that forms a waveguide configured to receive pump light and output Stokes light through Raman scattering, wherein the thickness of the layer of silicon, the spacing of the lattice of holes, and the size of the holes are dimensioned to provide Raman lasing.Type: GrantFiled: November 17, 2010Date of Patent: October 16, 2012Assignee: The Trustees of Columbia University in the City of New YorkInventors: Chee Wei Wong, James F. McMillan, Xiaodong Yang, Richard Osgood, Jr., Jerry Dadap, Nicolae Panoiu
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Patent number: 8263483Abstract: A method including producing a monocrystalline layer is disclosed. A first lattice constant on a monocrystalline substrate has a second lattice constant at least in a near-surface region. The second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion.Type: GrantFiled: July 7, 2009Date of Patent: September 11, 2012Assignee: Infineon Technologies Austria AGInventors: Franz Hirler, Hans-Joachim Schulze
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Patent number: 8258603Abstract: A solid-state far ultraviolet light emitting element is formed by a hexagonal boron nitride single crystal, excited by electron beam irradiation to emit far ultraviolet light having a maximum light emission peak in a far ultraviolet region at a wavelength of 235 nm or shorter.Type: GrantFiled: October 16, 2009Date of Patent: September 4, 2012Assignee: National Institute for Materials ScienceInventors: Kenji Watanabe, Takashi Taniguchi, Satoshi Koizumi, Hisao Kanda, Masayuki Katagiri, Takatoshi Yamada, Nesladek Milos
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Patent number: 8227327Abstract: There is provided a method for epitaxial growth, wherein a quantum dot is formed on an epitaxial layer using a quantum-dot forming material with an excellent lattice matching property, and the formed quantum dot is positioned on a defect in the epitaxial layer, thereby minimizing transfer of the defect into an epitaxial layer formed through a subsequent process. The method includes preparing a first epitaxial layer having a defect formed therein; coating an anti-surfactant on the first epitaxial layer; supplying a quantum-dot forming material lattice-matched with respect to the first epitaxial layer, thereby forming a quantum dot obtained by allowing the anti-surfactant to react with the quantum-dot forming material on the first epitaxial layer; allowing the quantum dot to be moved onto a step of the first epitaxial layer due to a difference of surface energies between the quantum dot and the first epitaxial layer; and growing a second epitaxial layer on the first epitaxial layer.Type: GrantFiled: February 18, 2009Date of Patent: July 24, 2012Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventor: Jae-eung Oh
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Publication number: 20120181501Abstract: Graphene layers and associated methods are disclosed. In one aspect, for example, a method of making graphene on a diamond substrate is provided. Such a method can include applying a layer of a metal to a crystallographic face of the diamond substrate, and heating the diamond substrate under vacuum to convert a portion of the diamond substrate at the crystallographic face into graphene. In another aspect, the layer of metal is applied only on diamond substrate faces having a same crystallographic orientation. In yet another aspect, the layer of metal is applied to only a single crystallographic face of the diamond substrate. Additionally, in one aspect, converting the portion of the diamond substrate at the crystallographic face into graphene includes converting the portion of the diamond substrate by a martensitic transformation.Type: ApplicationFiled: January 4, 2012Publication date: July 19, 2012Inventor: Chien-Min Sung
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Patent number: 8221544Abstract: A polycrystalline film is prepared by (a) providing a substrate having a thin film disposed thereon, said film capable of laser-induced melting, (b) generating a sequence of laser pulses having a fluence that is sufficient to melt the film throughout its thickness in an irradiated region, each pulse forming a line beam having a predetermined length and width, said width sufficient to prevent nucleation of solids in a portion of the thin film that is irradiated by the laser pulse, (c) irradiating a first region of the film with a first laser pulse to form a first molten zone, said first molten zone demonstrating a variation in width along its length to thereby define a maximum width (Wmax) and a minimum width (Wmin), wherein the first molten zone crystallizes upon cooling to form one or more laterally grown crystals, (d) laterally moving the film in the direction of lateral growth a distance that is greater than about one-half Wmax and less than Wmin; and (e) irradiating a second region of the film with a secoType: GrantFiled: December 2, 2005Date of Patent: July 17, 2012Assignee: The Trustees of Columbia University in the City of New YorkInventors: James S. Im, Paul C. Van Der Wilt
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Patent number: 8216361Abstract: Monocrystalline semiconductor wafers have defect-reduced regions, the defect-reduced regions having a density of GOI-relevant defects within the range of 0/cm2 to 0.1/cm2 and occupy overall an areal proportion of 10% to 100% of the planar area of the semiconductor wafer, wherein the remaining regions of the semiconductor wafer have a significantly higher defect density than the defect-reduced regions. The wafers may be produced by a method for annealing GOI relevant defects in the wafer, by irradiating defined regions of a side of the semiconductor wafer by laser wherein each location is irradiated with a power density of 1 GW/m2 to 10 GW/m2 for at least 25 ms, wherein the laser emits radiation of a wavelength above the absorption edge of the wafer semiconductor material and wherein the temperature of the wafer rises by less than 20 K as a result of irradiation.Type: GrantFiled: September 7, 2011Date of Patent: July 10, 2012Assignee: Siltronic AGInventors: Dieter Knerer, Andreas Huber, Ulrich Lambert, Friedrich Passek
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Publication number: 20120160152Abstract: The transfer of the structure of a crystal (3) having an amorphous or crystal structure to a thin layer (1) with a different structure can be achieved by the combination of a pressing (6) and a heating (7) to apply the layer onto the crystal and anneal it to crystallize it. Characteristically, wedges (5) are placed at the edges to flex the layer and give rise to cracking of the assembly and releasing the layer when the pressure ceases, which eliminates the complicated methods for withdrawing the crystal (3) or even destroying it, enables the use of the crystal (3) in several layers to be crystallized, allows a good manufacturing rate and reduces costs.Type: ApplicationFiled: September 14, 2010Publication date: June 28, 2012Applicant: Commissariat A L'Energie Atomique Et Aux Energies AlternativesInventor: Cyril Cayron