By Pulling {c30b 29/06} Patents (Class 117/932)
  • Patent number: 7097718
    Abstract: Epitaxial wafers comprising a single crystal silicon substrate comprising agglomerated vacancy defects and having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated intrinsic point defects on the substrate surface upon which the epitaxial layer is deposited.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: August 29, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Lu Fei, Joseph C. Holzer, Harold W. Korb, Robert J. Falster
  • Patent number: 7074271
    Abstract: A surface of a reference sample is contaminated with a transition metal, and a heat treatment is performed to diffuse the transition metal in the sample. A concentration of recombination centers formed by the transition metal is measured in the entire heat-treated reference sample, and a region [V], a region [Pv], a region [Pi], and a region [I] in the reference sample are defined based on the values measured. Meanwhile, recombination lifetimes associated with the transition metal are measured in the entire heat-treated reference sample. Based on both of the measurement results, a correlation line of the concentration of recombination centers and the recombination lifetimes is produced. A surface of the measurement sample is contaminated with the transition metal, and a heat treatment is performed to diffuse the transition metal in the sample.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: July 11, 2006
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Jun Furukawa, Kazunari Kurita, Kazuhiro Harada
  • Patent number: 7014704
    Abstract: A method for growing a silicon single crystal used for semiconductor integrated circuit devices, wherein the single crystal is grown by the CZ method at a nitrogen concentration of 1×1013 atoms/cm3–1×1015 atoms/cm3 with a cooling rate of not less than 2.5° C./min at a crystal temperature of 1150° C.–1000° C., in which case, the pulling rate is adjusted such that the outside diameter of a circular region including oxidation-induced stacking faults generated at the center of a wafer which is subjected to the oxidation heat treatment at high temperature is not more than ? of the wafer diameter, wherein the wafer is prepared by slicing the grown single crystal. In the growth method, the concentration of oxygen in the silicon single crystal is preferably not more than 9×1017 atoms/cm3 (ASTM '79). With this method, the silicon single crystal, in which the generation of Grown-in defects can be effectively suppressed, can be produced in a simple process without any increase in the production cost.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: March 21, 2006
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Toshiaki Ono, Tadami Tanaka, Shigeru Umeno, Eiichi Asayama, Hideshi Nishikawa
  • Patent number: 6986925
    Abstract: A single crystal silicon wafer comprising a front surface, a back surface, a lateral surface joining the front and back surfaces, a central axis perpendicular to the front and back surfaces, and a segment which is axially symmetric about the central axis extending substantially from the front surface to the back surface in which crystal lattice vacancies are the predominant intrinsic point defect, the segment having a radial width of at least about 25% of the radius and containing agglomerated vacancy defects and a residual concentration of crystal lattice vacancies wherein (i) the agglomerated vacancy defects have a radius of less than about 70 nm and (ii) the residual concentration of crystal lattice vacancy intrinsic point defects is less than the threshold concentration at which uncontrolled oxygen precipitation occurs upon subjecting the wafer to an oxygen precipitation heat treatment.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: January 17, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, Paolo Mutti, Francesco Bonoli
  • Patent number: 6913646
    Abstract: There can be provided a silicon single crystal wafer grown according to Czochralski method wherein the whole plane of the wafer is occupied by N region on the outside of OSF generated in a shape of a ring by thermal oxidation treatment and there exists no defect region detected by Cu deposition. Thereby, there can be produced a silicon single crystal wafer according to CZ method, which does not belong to any of V region rich in vacancies, OSF region and I region rich in interstitial silicons, and can surely improve electric characteristics such as oxide dielectric breakdown voltage characteristics or the like under stable manufacture conditions.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: July 5, 2005
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masahiro Sakurada, Takeshi Kobayashi, Tatsuo Mori, Izumi Fusegawa, Tomohiko Ohta
  • Patent number: 6908509
    Abstract: Additional charge of a solid raw material 13 in the shapes of granules/lumps, low in raw material cost, and with no risk of cracking, is performed into a molten raw material 14 in a crucible in a static manner without solidifying a surface of the molten raw material 14 in the crucible 3. A bottom of a cylindrical raw material vessel 10 made of a material non-meltable when being in contact with the molten raw material 14 in the crucible 3 is closed with a bottom cover 11 made of a material meltable and removable when being in contact with the molten raw material 14 in the crucible 3. The raw material vessel 10 in a state of being filled with the solid raw material 13 in the shapes of granules/lumps is hung down above the crucible 3 to immerse the lower portion thereof into the molten raw material 14 in the crucible 3.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: June 21, 2005
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Katsunori Nakashima, Makoto Ito
  • Patent number: 6905771
    Abstract: A silicon wafer is doped with boron and germanium in a range that satisfies a relational expression defined by: ?0.8×10?3?4.64×10?24×[Ge]?2.69×10?23×[B]?1.5×10?3. This can reduce the miss-fit dislocation which might be induced when an epitaxial layer is grown over the silicon wafer that has been added with boron in high concentration. It is to be noted that in the above relational expression, the [B] denotes a boron concentration, while the [Ge] denotes a germanium concentration and a concentration unit is indicated by atoms/cm3.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: June 14, 2005
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Toshiaki Ono, Tadami Tanaka, Masataka Hourai
  • Patent number: 6896727
    Abstract: An improved method of determining the concentration of nitrogen within a wafer is provided. At least a portion of the nitrogen within the wafer is initially gettered to a gettering site. In order prevent the in-diffusion of nitrogen, a barrier layer is generally deposited upon the wafer prior to gettering the nitrogen within the wafer. The nitrogen is then measured at the gettering site. The concentration of nitrogen within the wafer is then determined based upon the measurement of nitrogen at the gettering site and the diffusion coefficient for nitrogen. In this regard, the diffusion coefficient of nitrogen permits the measurement of nitrogen at the gettering site to be translated into a measurement of the concentration of nitrogen throughout the entire wafer.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: May 24, 2005
    Assignee: SEH America, Inc.
    Inventor: Sergei V. Koveshnikov
  • Patent number: 6866713
    Abstract: The present invention provides for a process for preparing a single crystal silicon ingot by the Czochralski method. The process comprises selecting a seed crystal for Czochralski growth wherein the seed crystal comprises vacancy dominated single crystal silicon.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: March 15, 2005
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Hariprasad Sreedharamurthy, Mohsen Banan
  • Patent number: 6858307
    Abstract: A process for the preparation of a silicon single ingot in accordance with the Czochralski method. The process for growing the single crystal silicon ingot comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, during the growth of a constant diameter portion of the crystal over a temperature range from solidification to a temperature of no less than about 1325° C. to initially produce in the constant diameter portion of the ingot a series of predominant intrinsic point defects including vacancy dominated regions and silicon self interstitial dominated regions, alternating along the axis, and cooling the regions from the temperature of solidification at a rate which allows silicon self-interstitial atoms to diffuse radially to the lateral surface and to diffuse axially to vacancy dominated regions to reduce the concentration intrinsic point defects in each region.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: February 22, 2005
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Vladimir V. Vornokov, Robert J. Falster, Mohsen Banan
  • Patent number: 6849119
    Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The wafer is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a wafer having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the wafer.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: February 1, 2005
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Marco Cornara, Daniela Gambaro, Massimiliano Olmo
  • Patent number: 6846539
    Abstract: The present invention relates to a process for preparing a single crystal silicon ingot, as well as to the ingot or wafer resulting therefrom. The process comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, and (iii) a cooling rate of the crystal from solidification to about 750° C., in order to cause the formation of a segment having a first axially symmetric region extending radially inward from the lateral surface of the ingot wherein silicon self-interstitials are the predominant intrinsic point defect, and a second axially symmetric region extending radially inward from the first and toward the central axis of the ingot.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: January 25, 2005
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Chang Bum Kim, Steven L. Kimbel, Jeffrey L. Libbert, Mohsen Banan
  • Patent number: 6843847
    Abstract: A silicon single crystal wafer grown by the CZ method, which is doped with nitrogen and has an N-region for the entire plane and an interstitial oxygen concentration of 8 ppma or less, or which is doped with nitrogen and has an interstitial oxygen concentration of 8 ppma or less, and in which at least void type defects and dislocation clusters are eliminated from the entire plane, and a method for producing the same. Thus, there are provided a defect-free silicon single crystal wafer having an N-region for the entire plane, in which void type defects and dislocation clusters are eliminated, produced by the CZ method under readily controllable stable production conditions with a wide controllable range, and a method producing the same.
    Type: Grant
    Filed: November 7, 2000
    Date of Patent: January 18, 2005
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Makoto Iida, Masanori Kimura
  • Patent number: 6808781
    Abstract: A silicon wafer having a controlled oxygen precipitation behavior such that a denuded zone extending inward from the front surface and oxygen precipitates in the wafer bulk sufficient for intrinsic gettering purposes are ultimately formed. Specifically, prior to formation of the oxygen precipitates, the wafer bulk comprises dopant stabilized oxygen precipitate nucleation centers. The dopant is selected from a group consisting of nitrogen and carbon and the concentration of the dopant is sufficient to allow the oxygen precipitate nucleation centers to withstand thermal processing such as an epitaxial deposition process while maintaining the ability to dissolve any grown-in nucleation centers.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: October 26, 2004
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Jeffrey L. Libbert, Richard J. Phillips, Milind Kulkarni, Mohsen Banan, Stephen J. Brunkhorst
  • Patent number: 6800132
    Abstract: A method for producing a silicon ingot through pulling up a silicon single crystal according to the Czochralski method, wherein the silicon single crystal is pulled up while being doped with nitrogen in such a condition as to form a part having a nitrogen content of 5×1013 atoms/cm3 to 1×1015 atoms/cm3. A silicon wafer having a nitrogen content of 5×1013 atoms/cm3 to 1×1015 atoms/cm3 which is suitable for being treated with heat in a non-oxidizing atmosphere is manufactured of an ingot produced by using the method. The method can be used for producing a silicon wafer being doped with nitrogen and having satisfactory characteristics for use in a semiconductor device.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: October 5, 2004
    Assignee: Komatsu Denshi Sinzoku Kabushiki
    Inventors: Satoshi Komiya, Shiro Yoshino, Masayoshi Danbata, Kouichirou Hayashida
  • Patent number: 6780238
    Abstract: A silicon wafer is provided having controlled distribution of defects, in which denuded zones having a sufficient depth inward from the surface of the wafer are combined with a high gettering effect in a bulk region of the wafer. In the silicon wafer, oxygen precipitates, which act as intrinsic gettering sites, show vertical distribution. The oxygen precipitate concentration profile from the top to the bottom surfaces of the wafer includes first and second peaks at first and second predetermined depths from the top and bottom surfaces of the wafer, denuded zones between the top and bottom surfaces of the wafer and each of the first and second peaks, and a concave region between the first and second peaks, which corresponds to a bulk region of the wafer. For such an oxygen precipitate concentration profile, the wafer is exposed to a rapid thermal annealing process in a gas mixture atmosphere comprising ammonia (NH3) and argon (Ar) at temperatures below about 1200° C.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: August 24, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jea-gun Park
  • Patent number: 6740158
    Abstract: An inexpensive method of coating silicon shot with boron atoms comprises (1) immersing silicon shot in a boron dopant spin-on solution comprising a borosilicate, a polymer precursor, and a volatile solvent, and (2) removing the solvent so as to leave a polymeric coating containing borosilicate on the shot. A precise amount of this coated shot may then be mixed with a measured quantity of silicon pellets and the resulting mixture may then be melted to provide a boron-doped silicon melt for use in growing p-type silicon bodies that can be converted to substrates for photovoltaic solar cells.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: May 25, 2004
    Assignee: RWE Schott Solar Inc.
    Inventor: Bernhard P. Piwczyk
  • Patent number: 6663710
    Abstract: An apparatus and a method that permits a seed crystal to be directed to a precise location of a melt for growing a ribbon-shaped crystal, but after the crystal has commenced growing, the ribbon-shaped crystal is continuously pulled up so as to produce a longitudinally extending crystal using a continuous pulling device. The method for producing a ribbon-shaped crystal includes growing a ribbon-shaped crystal on a seed crystal using a linear pulling device for pulling the seed crystal and a crystal growing at the end of the seed crystal in a vertical direction, and continuing to pull the ribbon-shaped crystal by using a continuous pulling device having a continuous pulling mechanism.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: December 16, 2003
    Assignee: Ebara Corporation
    Inventors: Kentaro Fujita, Kenji Terao, Hideyuki Isozaki, Iwao Satoh
  • Patent number: 6652646
    Abstract: A process for growing a single crystal silicon ingot having an axially symmetric region substantially free of agglomerated intrinsic point defects. The ingot is grown generally in accordance with the Czochralski method; however, the manner by which the ingot is cooled from the temperature of solidification to a temperature which is in excess of about 900° C. is controlled to allow for the diffusion of intrinsic point defects, such that agglomerated defects do not form in this axially symmetric region. Accordingly, the ratio v/G0 is allowed to vary axially within this region, due to changes in v or G0, between a minimum and maximum value by at least 5%.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: November 25, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Vladimir Voronkov, Paolo Mutti
  • Patent number: 6652645
    Abstract: A process for controlling the amount of insoluble gas trapped by a silicon melt is disclosed. After a crucible is charged with polycrystalline silicon, a gas comprising at least about 10% of a gas having a high solubility in silicon is used as the purging gas for a period of time during melting. After the polycrystalline silicon charge has completely melted, the purge gas may be switched to a conventional argon purge. Utilizing a purge gas highly soluble in silicon for a period of time during the melting process reduces the amount of insoluble gases trapped in the charge and, hence, the amount of insoluble gases grown into the crystal that form defects on sliced wafers.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: November 25, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: John Davis Holder
  • Patent number: 6638357
    Abstract: A method for revealing agglomerated intrinsic point defect. The method comprising coating a sample with a metal capable of decorating agglomerated intrinsic point defects, heat-treating the coated sample to decorate any agglomerated intrinsic point defects, cooling the sample, etching the surface of the cooled sample without delineating the decorated agglomerated intrinsic point defects and etching the etched surface with a delineating etchant to reveal the decorated intrinsic point defects.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: October 28, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Robert J. Falster
  • Patent number: 6605150
    Abstract: The present invention relates to a single crystal silicon, in wafer and ingot form, which contains an axially symmetric region which is free of agglomerated intrinsic point defects. The region extends from a circumferential edge of the wafer or constant diameter region of an ingot, axially inwardly toward a central axis such that the entire wafer, a constant diameter portion of the ingot, or an annular-shaped portion of wafer or ingot is free of agglomerated intrinsic point defects. The present invention further relates to these axially symmetric regions wherein silicon self-interstitials are the predominant intrinsic point detect.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: August 12, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Joseph C. Holzer
  • Patent number: 6599603
    Abstract: The present invention provides a CZ silicon wafer, wherein the wafer includes rod-like void defects and/or plate-like void defects inside thereof, and a CZ silicon wafer, wherein the silicon wafer includes void defects inside the wafer, a maximum value of a ratio between long side length L1 and short side length L2 (L1/L2) in an optional rectangle circumscribed the void defect image projected on an optional {110} plane is 2.5 or more, and the silicon wafer including rod-like void defects and/or plate-like void defects inside the wafer, wherein a void defect density of the silicon wafer at a depth of from the wafer surface to at least 0.5 &mgr;m after the heat treatment is ½ or less than that of inside the wafer. According to this, the silicon wafer, which is suitable for expanding reducing effect of void defects by heat treatment up to a deeper region, can be obtained.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: July 29, 2003
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masahiro Kato, Masaro Tamatsuka, Osamu Imai, Akihiro Kimura, Tomosuke Yoshida
  • Patent number: 6586068
    Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies in the wafer. During the heat-treatment, the front and back surfaces of the wafer are each exposed to either a nitriding or non-nitriding gas. The wafer is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a wafer having a vacancy concentration profile determined in part by the gas that each surface is exposed to and in part by the cooling rate.
    Type: Grant
    Filed: November 2, 2000
    Date of Patent: July 1, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert Falster, Marco Cornara, Daniela Gambaro, Massimiliano Olmo
  • Patent number: 6569535
    Abstract: A silicon wafer characterized in that the laser scattering tomography defect occurrence region accounts for at least 80% of the wafer surface area and that the laser scattering tomography defects have a mean size of not more than 0.1 &mgr;m, with the density of those defects which exceed 0.1 &mgr;m in size being not more than 1×105 cm−3, and wafers derived from this wafer as the raw material by heat treatment for oxide precipitate formation, by heat treatment for denuded layer formation or by epitaxial layer formation on the surface are useful as semiconductor materials.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: May 27, 2003
    Assignee: Sumitomo Metal Industries, Ltd.
    Inventors: Hiroki Murakami, Kazuyuki Egashira
  • Patent number: 6565649
    Abstract: The present invention is directed to an epitaxial wafer comprising a single crystal silicon substrate having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated silicon self-interstitial defects on the substrate surface upon which the epitaxial layer is deposited.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: May 20, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule′Stagno, Lu Fei, Joseph C. Holzer, Harold W. Korb, Robert J. Falster
  • Patent number: 6555194
    Abstract: The present invention is directed to a process for producing a silicon wafer which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, may form an ideal, non-uniform depth distribution of oxygen precipitates and may additionally contain an axially symmetric region which is substantially free of agglomerated intrinsic point defects. The process including growing a single crystal silicon ingot from molten silicon, and as part of the growth process, controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, during the growth of a constant diameter portion of the crystal over a temperature range from solidification to a temperature of no less than about 1325° C., and (iii) a cooling rate of the crystal from a solidification temperature to about 1,050° C., in order to cause the formation of an axially symmetrical segment which is substantially free of agglomerated intrinsic point defects.
    Type: Grant
    Filed: November 2, 2000
    Date of Patent: April 29, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert A. Falster, Joseph C. Holzer, Marco Cornara, Daniela Gambaro, Massimiliano Olmo, Steve A. Markgraf, Paolo Mutti, Seamus A. McQuaid, Bayard K. Johnson
  • Patent number: 6544332
    Abstract: A method for producing a silicon single crystal in accordance with CZ method, characterized in that before producing the crystal having a predetermined kind and concentration of impurity, another silicon single crystal having the same kind and concentration of impurity as the crystal to be produced is grown to thereby determine an agglomeration temperature zone of grown-in defects thereof, and then based on the temperature, growth condition of the crystal to be produced or temperature distribution within a furnace of a pulling apparatus is set such that a cooling rate of the crystal for passing through the agglomeration temperature zone is a desired rate to thereby produce the silicon single crystal. A silicon single crystal produced in accordance with the above method, characterized in that a density of LSTD before subjecting to heat treatment is 500 number/cm2 or more and the average defect size is 70 nm or less.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: April 8, 2003
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Makoto Iida, Masanori Kimura, Hiroshi Takeno, Yoshinori Hayamizu
  • Patent number: 6521316
    Abstract: The present invention relates to a single crystalline silicon ingot, a single crystalline wafer, and a producing method thereof in accordance with the Czochralski method which enables reduction of a large defect area while increasing a micro-vacancy defect area in an agglomerated vacancy point area, which is the area between a central axis and an oxidation-induced stacking fault ring, by providing uniform conditions of crystal ingot growth and cooling and by adjusting a pulling rate for growing an ingot to grow, thus the oxidation-induced stacking fault ring exists only at an edge of the ingot radius.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: February 18, 2003
    Assignee: Siltron Inc.
    Inventors: Hong-Woo Lee, Joon-Young Choi, Hyon-Jong Cho, Hak-Do Yoo
  • Patent number: 6503594
    Abstract: A silicon wafer is provided having controlled distribution of defects, in which denuded zones having a sufficient depth inward from the surface of the wafer are combined with a high gettering effect in a bulk region of the wafer. In the silicon wafer, oxygen precipitates, which act as intrinsic gettering sites, show vertical distribution. The oxygen precipitate concentration profile from the top to the bottom surfaces of the wafer includes first and second peaks at first and second predetermined depths from the top and bottom surfaces of the wafer, denuded zones between the top and bottom surfaces of the wafer and each of the first and second peaks, and a concave region between the first and second peaks, which corresponds to a bulk region of the wafer. For such an oxygen precipitate concentration profile, the wafer is exposed to a rapid thermal annealing process in a gas mixture atmosphere comprising ammonia (NH3) and argon (Ar) at temperatures below about 1200° C.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: January 7, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jea-gun Park
  • Patent number: 6500255
    Abstract: A process for growing a single crystal silicon ingot having an axially symmetric region substantially free of agglomerated intrinsic point defects. The ingot is grown generally in accordance with the Czochralski method; however, the manner by which the ingot is cooled from the temperature of solidification to a temperature which is in excess of about 900° C. is controlled to allow for the diffusion of intrinsic point defects, such that agglomerated defects do not form in this axially symmetric region. Accordingly, the ratio v/G0 is allowed to vary axially within this region, due to changes in v or G0, between a minimum and maximum value by at least 5%.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: December 31, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Vladimir Voronkov, Paolo Mutti
  • Patent number: 6485807
    Abstract: A silicon wafer is provided having controlled distribution of defects, in which denuded zones having a sufficient depth inward from the surface of the wafer are combined with a high gettering effect in a bulk region of the wafer. In the silicon wafer, oxygen precipitates, which act as intrinsic gettering sites, show vertical distribution. The oxygen precipitate concentration profile from the top to the bottom surfaces of the wafer includes first and second peaks at first and second predetermined depths from the top and bottom surfaces of the wafer, denuded zones between the top and bottom surfaces of the wafer and each of the first and second peaks, and a concave region between the first and second peaks, which corresponds to a bulk region of the wafer. For such an oxygen precipitate concentration profile, the wafer is exposed to a rapid thermal annealing process in a gas mixture atmosphere containing nitrogen (N2) and argon (Ar) or N2 and hydrogen (H2), in a donor killing step during a wafering process.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: November 26, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jea-gun Park
  • Patent number: 6458202
    Abstract: A Czochralski method of producing a single crystal silicon ingot having a uniform thermal history. In the process, the power supplied to the side heater is maintained substantially constant throughout the growth of the main body and end-cone of the ingot, while power supplied to a bottom heater is gradually increased during the growth of the second half of the main body and the end-cone. The present process enables an ingot to be obtained which yields wafers having fewer light point defects in excess of about 0.2 microns, while having improved gate oxide integrity.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: October 1, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Makoto Kojima, Yasuhiro Ishii
  • Patent number: 6451107
    Abstract: A first step models a hot zone in a pulling apparatus of a single crystal as a mesh structure, and a second step inputs physical property values of each member corresponding to meshes combined for each member of the hot zone into a computer. A third step obtains the surface temperature distribution of each member on the basis of the calorific power of a heater and the emissivity of each member, and a fourth step obtains the internal temperature distribution of each member on the basis of the surface temperature distribution and the thermal conductivity of each member, and then further obtains the internal temperature distribution of a molten liquid being in consideration of convection. A fifth step obtains the shape of the solid-liquid interface between the single crystal and the molten liquid in accordance with an isothermal line including a tri-junction of the single crystal. A sixth step repeats said third to fifth steps until the tri-junction becomes the melting point of the single crystal.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: September 17, 2002
    Assignee: Mitsubishi Materials Silicon Corporation
    Inventors: Kounosuke Kitamura, Naoki Ono
  • Patent number: 6416836
    Abstract: A single crystal silicon wafer having a central axis, a front side and a back side which are generally perpendicular to the central axis, a central plane between the front and back sides, a circumferential edge, and a radius extending from the central axis to the circumferential edge. The wafer comprises first and second axially symmetric regions. The first axially symmetric region extends radially inwardly from the circumferential edge, contains silicon self-interstitials as the predominant intrinsic point defect, and is substantially free of agglomerated interstitial defects. The second axially symmetric region has vacancies as the predominant intrinsic point defect, comprises a surface layer extending from the front side toward the central plane and a bulk layer extending from the surface layer to the central plane, wherein the number density of agglomerated vacancy defects present in the surface layer is less than the concentration in the bulk layer.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: July 9, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Martin Jeffrey Binns, Alan Wang
  • Patent number: 6409827
    Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region which is free of agglomerated intrinsic point defects, and a process for the preparation thereof. The process including controlling growth conditions, such as growth velocity, v, instantaneous axial temperature gradient, G0, and the cooling rate, within a range of temperatures at which silicon self-interstitials are mobile, in order to prevent the formation of these agglomerated defects. The control of G0 is accomplished by controlling heat transfer at the melt/solid interface.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: June 25, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Joseph C. Holzer
  • Patent number: 6409826
    Abstract: The present invention relates a process for the preparation of single crystal silicon, which contains an axially symmetric region which is free of agglomerated intrinsic point defects. The process for growing the single crystal silicon including controlling the ratio v/G0, where v is the growth velocity and G0 is the average axial temperature gradient during the growth of a constant diameter portion of the crystal over a temperature range from solidification to a temperature of no less than about 1325° C., and a cooling rate of the crystal from a solidification temperature to about 1,050° C., in order to cause the formation of an axially symmetrical segment which is substantially free of agglomerated intrinsic point defects. The control of V/G0 accomplished by controlling heat transfer at the melt/solid interface.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: June 25, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert A. Falster, Joseph C. Holzer, Steve A. Markgraf, Paolo Mutti, Seamus A. McQuaid, Bayard K. Johnson
  • Patent number: 6379642
    Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region in which vacancies are the predominant intrinsic point defect and which is substantially free of agglomerated vacancy intrinsic point defects, wherein the first axially symmetric region has a width which is at least about 50% of the length of the radius of the ingot, and a process for the preparation thereof.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: April 30, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert A. Falster, Joseph C. Holzer, Steve A. Markgraf, Paolo Mutti, Seamus A. McQuaid, Bayard K. Johnson
  • Patent number: 6372040
    Abstract: In an arrangement to grip lower part of a portion with larger diameter of single crystal formed by CZ method, the present invention provides an apparatus and a method for growing and pulling up the single crystal without causing deformation or rupture and under dislocation-free and stable condition even when the portion with larger diameter is at high temperature and when the single crystal rod has heavy weight of about 400 kg and large diameter. Under the condition that a material having Shore hardness of not less than 70, Vickers hardness of not more than 100, and tensile strength of not less than 400 MPa is used as a contact member which is used on a portion of gripping members in contact with lower part of the portion with larger diameter, and when minimum diameter of a constricted portion under the portion with larger diameter is set to 12 mm or more, temperature (° C.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: April 16, 2002
    Assignee: Super Silicon Crystal Research Institute Corp.
    Inventor: Hirotoshi Yamagishi
  • Patent number: 6350312
    Abstract: A process for preparing strontium doped molten silicon for use in a single silicon crystal growing process is disclosed. Polysilicon is doped strontium and melted in a silica crucible. During melting and throughout the crystal growing process the strontium acts as a devitrification promoter and creates a layer of devitrified silica on the inside crucible surface in contact with the melt resulting in a lower level of contaminants in the melt and grown crystal.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: February 26, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Richard Joseph Phillips, Steven Jack Keltner, John Davis Holder
  • Patent number: 6344083
    Abstract: A process for controlling the amount of insoluble gas trapped by a silicon melt is disclosed. After a crucible is charged with polycrystalline silicon, a gas comprising at least about 10% of a gas having a high solubility in silicon is used as the purging gas for a period of time during melting. After the polycrystalline silicon charge has completely melted, the purge gas may be switched to a conventional argon purge. Utilizing a purge gas highly soluble in silicon for a period of time during the melting process reduces the amount of insoluble gases trapped in the charge and, hence, the amount of insoluble gases grown into the crystal that form defects on sliced wafers.
    Type: Grant
    Filed: February 14, 2000
    Date of Patent: February 5, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: John Davis Holder
  • Patent number: 6315827
    Abstract: There is described an apparatus for producing a single crystal ingot capable of stably manufacturing a single crystal ingot by means of the Czochralski method, without being affected by influence of variation in extension of wires or an offset in points clamped by a clamping member. The clamping member is engaged with an engagement step formed in a single crystal which is being pulled by the CZ method, and the single crystal is pulled. The single crystal ingot manufacturing apparatus is provided with a flexible mechanism for absorbing variation in extension of the wires, in intermediate portions of the wires. Variation in extension of the wires is eliminated by means of the flexible mechanism, thereby retaining the single crystal in an upright position. Further, a sacrifice member which deforms so as to conform to the circumference of the engagement step is interposed between the clamping member and the engagement step, thereby preventing occurrence of cracking or deformation in the single crystal.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: November 13, 2001
    Assignee: Komatsu Electronics Metals Co., Ltd.
    Inventors: Shoei Kurosaka, Junsuke Tomioka, Masakazu Kobayashi, Kazuhiro Mimura, Kenji Okamura, Hiroshi Monden, Naritoshi Ohtsukasa, Hiroshi Yoshinada
  • Patent number: 6315828
    Abstract: A continuous oxidation process and apparatus for using the same are disclosed. During growth of a semiconductor crystal an oxygen-containing gas is continuously injected into the crystal pulling apparatus in an exhaust tunnel downstream from the hot zone to continuously oxidize hypostoichiometric silicon dioxide, silicon vapor, and silicon monoxide produced in the hot zone during the crystal growth so as to minimize or eliminate the possibility of rapid over-pressurization of the apparatus upon exposure to the atmosphere.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: November 13, 2001
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: John D. Holder, Bayard K. Johnson
  • Patent number: 6312516
    Abstract: A process for growing a single crystal silicon ingot having an axially symmetric region substantially free of agglomerated intrinsic point defects. The ingot is grown generally in accordance with the Czochralski method; however, the manner by which the ingot is cooled from the temperature of solidification to a temperature which is in excess of about 900° C. is controlled to allow for the diffusion of intrinsic point defects, such that agglomerated defects do not form in this axially symmetric region. Accordingly, the ratio v/G0 is allowed to vary axially within this region, due to changes in v or G0, between a minimum and maximum value by at least 5%.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: November 6, 2001
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Vladimir Voronkov, Paolo Mutti
  • Patent number: 6312517
    Abstract: A method of lowering the resistivity of resultant silicon crystal from a Czochralski crystal growing process by adding arsenic dopant to the melt in multiple stages.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: November 6, 2001
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Mohsen Banan, Milind Kulkarni, Charles Whitmer, II
  • Patent number: 6287380
    Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region which is free of agglomerated intrinsic point defects, and a process for the preparation thereof. The process comprises controlling growth conditions, such as growth velocity, v, instantaneous axial temperature gradient, G0, and the cooling rate, within a range of temperatures at which silicon self-interstitials are mobile, in order to prevent the formation of these agglomerated defects. In ingot form, the axially symmetric region has a width, as measured from the circumferential edge of the ingot radially toward the central axis, which is at least about 30% the length of the radius of the ingot. The axially symmetric region additionally has a length, as measured along the central axis, which is at least about 20% the length of the constant diameter portion of the ingot.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: September 11, 2001
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Joseph C. Holzer
  • Patent number: 6284039
    Abstract: The present invention is directed to a set of epitaxial silicon wafers assembled in a wafer cassette, boat or other wafer carrier. Each wafer comprises a single crystal silicon substrate having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated silicon self-interstitial defects on the substrate surface upon which the epitaxial layer is deposited.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: September 4, 2001
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Lu Fei, Joseph C. Holzer, Harold W. Korb, Robert J. Falster
  • Publication number: 20010008114
    Abstract: A process for growing single crystal silicon ingots which are substantially free of agglomerated intrinsic point defects. An ingot is grown generally in accordance with the Czochralski method. No portion of the ingot cools to a temperature which is less than a temperature TA at which agglomeration of intrinsic point defects in the ingot occurs during the time the ingot is being grown. The achievement of defect free ingots is thus substantially decoupled from process parameters, such as pull rate, and system parameters, such as axial temperature gradient in the ingot.
    Type: Application
    Filed: June 25, 1999
    Publication date: July 19, 2001
    Inventors: ROBERT J. FALSTER, HAROLD W. KORB
  • Publication number: 20010003268
    Abstract: A process for growing a single crystal silicon ingot having an axially symmetric region substantially free of agglomerated intrinsic point defects. The ingot is grown generally in accordance with the Czochralski method; however, the manner by which the ingot is cooled from the temperature of solidification to a temperature which is in excess of about 900° C. is controlled to allow for the diffusion of intrinsic point defects, such that agglomerated defects do not form in this axially symmetric region. Accordingly, the ratio v/G0 is allowed to vary axially within this region, due to changes in v or G0, between a minimum and maximum value by at least 5%.
    Type: Application
    Filed: June 25, 1999
    Publication date: June 14, 2001
    Inventors: ROBERT J. FALSTER, VLADIMIR VORONKOV
  • Patent number: 6228167
    Abstract: In the apparatus according to the present invention, self-weight of a single crystal is moved in soft manner when the single crystal being pulled up is gripped by grippers, and driving of pulling operation after self-weight movement is performed by a single driving source, and it is aimed to prevent contamination and dislocation of the single crystal by arranging all driving units outside a vacuum chamber for storing the single crystal. There is provided a support member 70 for supporting a portion with larger diameter 5 under a seed crystal 3, and the support member 70 is provided with a through-hole, which is communicated with outer peripheral portion via a slit 74, and it can be rotated in horizontal direction between a non-holding position and a holding position by the motor 40.
    Type: Grant
    Filed: May 9, 1999
    Date of Patent: May 8, 2001
    Assignee: Super Silicon Crystal Research Institute Corp.
    Inventors: Makoto Kuramoto, Tetsuhiro Iida