Masks, Special Patents (Class 148/DIG106)
  • Patent number: 5932489
    Abstract: A method for manufacturing phase-shifting masks utilizing a photolithographic process and sidewall spacers to fabricate a phase-shifting layer. The method provides precise control over the shape and size of the resulting phase-shifting layer, and thus, simplifies photomask production.
    Type: Grant
    Filed: April 22, 1997
    Date of Patent: August 3, 1999
    Assignee: United Microelectronics Corp.
    Inventor: Chien Chao Huang
  • Patent number: 5811342
    Abstract: A method for forming a semiconductor device with a graded lightly-doped drain (LDD) structure is disclosed. The method includes providing a semiconductor substrate (10) having a gate region (14 and 16) thereon, followed by forming a pad layer (18) on the substrate and the gate region. Next, ions are implanted into the substrate, and a spacer (22) is formed on sidewalls of the gate region, wherein the first spacer has a concave surface inwards on a surface of the first spacer. Finally, ions are further implanted into the substrate using the gate region and the spacer as a mask, thereby forming a graded doping profile (20) in the substrate.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: September 22, 1998
    Assignee: Texas Instruments - Acer Incorporated
    Inventor: Shye-Lin Wu
  • Patent number: 5792270
    Abstract: A method and apparatus for producing a pattern of nucleation sites is disclosed. The method enables the growth of single crystal layers of a desired orientation on a suitable amorphous and/or non-single crystal surface. The method can be used to produce single crystal Si layers of a desired orientation on an amorphous layer, e.g. of SiO.sub.2 or Si.sub.3 N.sub.4. The method can provide for growth of (100) crystal orientation on SiO.sub.2. Semiconductor films may be accordingly grown on amorphous glass substrates for producing solar cells of high efficiency. A pattern of nucleation sites is created in amorphous layers, e.g. SiO.sub.2 on an IC wafer, by high-dose implantation through a single crystal mask having appropriate channeling directions at the desired lattice constants. Such implantation may be performed in a conventional ion implanter. Subsequent to creation of spaced-apart nucleation sites, epitaxial Si may be grown on such an SiO.sub.2 surface by CVD of Si.
    Type: Grant
    Filed: October 21, 1993
    Date of Patent: August 11, 1998
    Inventor: Arjun Saxena
  • Patent number: 5683936
    Abstract: A process to fabricate a specified height and cross-section of Microwave Monolithic Integrated Circuit gold posts comprising a patterned conductive substrate overlayed by an adhesive layer, a matrix layer, and a photoresist layer. Using photolithographic techniques, gold post locations are defined in the photoresist layer. m Gold post locations and cross-sections are defined in the matrix layer. The adhesive layer at the gold post locations is removed. The gold post locations are plated to form gold posts. The matrix is etched and the adhesive is dissolved.
    Type: Grant
    Filed: January 27, 1995
    Date of Patent: November 4, 1997
    Assignee: The Whitaker Corporation
    Inventors: Krishna Pande, Olaleye A. Aina, Orlando E. Asuncion, Fred R. Phelleps, Jay Mathews, Richard Dean
  • Patent number: 5679608
    Abstract: The interconnects in a semiconductor device contacting metal lines includes a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof. A tri-layer resist structure is used, together with a lift-off process, to form the interconnects. The low dielectric constant material provides a diffusion barrier to the diffusion of the low resistance metal. The tri-layer resist includes a first layer of a dissolvable polymer, a second layer of a hard mask material, and a third layer of a resist material. The resulting structure provides an integrated circuit with increased speed and ease of fabrication.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: October 21, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robin W. Cheung, Mark S. Chang
  • Patent number: 5668018
    Abstract: A device and method are described for defining a region on a wall of a semiconductor structure, such as a sidewall of a trench formed in a semiconductor substrate. The method includes the steps of forming a vertical structure above the semiconductor structure and spaced parallel to the wall; providing within the vertical structure an area of one of transparence, reflection or refraction; and projecting light at a given angle to the wall, wherein only a portion of the light passes the vertical structure via the area provided therein to impinge upon the wall of the semiconductor structure, and thereby define the region on the wall. As an alternative, the area can comprise an aperture in the vertical structure such that the vertical structure can be employed as a mask to direct selective ion implantation of the wall.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 16, 1997
    Assignee: International Business Machines Corporation
    Inventors: John Edward Cronin, Joseph Edward Gortych
  • Patent number: 5668042
    Abstract: A method for aligning micro patterns of a semiconductor device, capable of reducing the number of dies having poor quality in the formation of patterns, thereby achieving an improvement in operation reliability of the semiconductor device. The method of the present invention utilizes the fact that even in the case of a semiconductor wafer having alignment marks damaged due to an error occurring in the formation or etching of thin films, outer mark portions of its overlay measuring marks can be observed. For several dies sampled as observation dies from the semiconductor wafer, light exposure is carried out to form photoresist film patterns under the condition that the semiconductor wafer is misaligned from the light exposure mask. Thereafter, alignment marks and inner mark portions of overlay measuring marks are formed. A misalignment angle .theta. between the semiconductor wafer and light exposure mask is also calculated.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: September 16, 1997
    Assignee: Hyundai Electronics Industries Co., Ltr.
    Inventor: Sang Man Bae
  • Patent number: 5604139
    Abstract: In forming a thin film transistor (TFT) having an offset structure or a lightly doped drain (LDD) structure, a blocking material having a lower etching rate than that of a material constructing a gate electrode is formed. By using the blocking material as a mask, a gate electrode material is side-etched selectively to form gate electrodes. The blocking material is processed selectively and remains in a drain region side. Also, an offset region or an LDD region is formed under the blocking material by performing an impurity ion implantation. On the other hand, after the gate electrodes are formed, a resist is added and then light exposure is performed from a source region side using a light blocking material as a mask, so that the resist remains in a drain region side of the gate electrode. Also, by implanting an impurity ion, an offset region or an LDD region is formed in the drain region side.
    Type: Grant
    Filed: February 9, 1995
    Date of Patent: February 18, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsufumi Codama, Ichiro Takayama, Michio Arai
  • Patent number: 5583069
    Abstract: The present invention provides a method for making a fine annular charge storage electrode in a semiconductor device, which is capable of easily forming the charge storage electrode having a double cylinder-shaped structure and a fine annular pattern which is smaller than the wavelength from the light source, using a phase-shift mask. Accordingly, the present invention has an effect in that the reliability of a memory device having the charge storage electrode is improved, by removing the bad contact in the double cylinder-shaped structure, and that the surface of the charge storage electrode can be easily increased from 20% to 80%.
    Type: Grant
    Filed: July 7, 1995
    Date of Patent: December 10, 1996
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Chang N. Ahn, Ik B. Hur, Hung E. Kim, Seung C. Moon, Il H. Lee
  • Patent number: 5573963
    Abstract: The present invention provides a method of manufacturing twin wells in a silicon substrate which uses only one photo step and provides a smooth surface topology. The first embodiment begins by forming spaced field oxide regions in the substrate. The spaced field oxide regions define a first region and a second region. A masking layer composed of borophosphosilicate glass (BPSG) and a barrier layer are formed over the field oxide regions. The barrier layer and the masking layer over the first region are removed by a photo etch process. Then, N-type impurities are implanted into the first region forming a n-well using the barrier layer and masking layers as a mask. Then, p-type impurities are implanted into the substrate to form a p-type layer beneath the N-well and a P-well in the second region. The barrier layer and the masking layer are then removed. The substrate is then annealed to drive in the ion implanted impurities thereby forming a n-well and a p-well.
    Type: Grant
    Filed: May 3, 1995
    Date of Patent: November 12, 1996
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Jan M. Sung
  • Patent number: 5565031
    Abstract: Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: October 15, 1996
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kevin K. Chan, Jack O. Chu, James M. E. Harper
  • Patent number: 5550074
    Abstract: Disclosed is a semiconductor fabrication process for fabricating MOS transistors in which ions are implanted only beneath the channel and are not overlapped with the source/drain regions so as to significantly reduce the junction capacitance of the source/drain regions for performance enhancement. The process comprises a first step of preparing a silicon substrate on which a field oxide region is formed to define an active region. In the second step, a phase-shift mask is used to define a substantially rectangular removal portion on a photoresist layer. One side of the rectangular removal portion is substantially aligned with the channel of the MOS transistor to be fabricated and the other three sides are placed within the field oxide region.
    Type: Grant
    Filed: January 19, 1996
    Date of Patent: August 27, 1996
    Assignee: United Microelectronics Corp.
    Inventor: Jengping Lin
  • Patent number: 5543342
    Abstract: In implantation of ions into a wafer, in the manufacture of a semiconductor device, a desired ion beam absorber pattern having locally different thicknesses is previously formed on a major surface of the wafer. The ion beam absorber pattern absorbs an ion beam to be implanted and is formed of a thin film material with its absorbency varying depending on its thickness. Ions are implanted once on the major surface of the wafer through this ion beam absorber pattern to form desired different impurity profiles in depth of desired regions on the major surface of the wafer.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: August 6, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takao Mukai, Nobuyuki Yoshioka
  • Patent number: 5525534
    Abstract: A method of producing a semiconductor device includes the steps of (a) preparing a substrate having a semiconductor element formed in a predetermined region of a surface of the substrate, (b) forming a first layer on the substrate, where the first layer is made of silicon oxide including at least one of boron and phosphor, (c) forming a second layer on a surface of the first layer, where the second layer is made of a material selected from a group consisting of silicon nitride and silicon oxide nitride, (d) coating a resist layer on the entire surface of the substrate, (e) exposing and developing a predetermined region of the resist layer using a reticle having a first opening so as to form a second opening in the resist layer, where the first opening has a polygonal shape having n corners respectively having obtuse angles and n is a natural number satisfying n.gtoreq.5, and (f) etching the second and first layers via the second opening.
    Type: Grant
    Filed: January 5, 1995
    Date of Patent: June 11, 1996
    Assignee: Fujitsu Limited
    Inventors: Shinichiro Ikemasu, Taiji Ema, Masaya Katayama
  • Patent number: 5512514
    Abstract: An integral via structure and contact manufacturing process (10) with a first conductive layer patterning process section (12) that includes depositing a first conductive layer (34), creating a first via etch mask (44) on the first conductive layer (34), partially etching the exposed portions of the first conductive layer (34) to create first via structures (52) and a remaining first conductive layer (34), stripping the first via etch mask (44), masking the remaining first conductive layer (34) with a first layer etch mask (56) that covers the via structures (52), etching the exposed portions of the remaining first conductive layer (34) to form a first conductive pattern (60) having integral via structures (52). A first dielectric (72) is deposited and planarized to expose top portions of the first via structure (52) and a second conductive layer (90) is deposited, making contact with the first via structures (52).
    Type: Grant
    Filed: November 8, 1994
    Date of Patent: April 30, 1996
    Assignee: Spider Systems, Inc.
    Inventor: Chong E. Lee
  • Patent number: 5510294
    Abstract: A method is provided for forming a via for multilevel metallization of an integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed over the integrated circuit. A first dielectric layer is then, formed over the first conductive layer. A second dielectric layer over the first dielectric layer and a second conductive layer is formed over the second dielectric layer. A photoresist layer is formed and patterned over the second conductive layer to expose a portion of the second conductive layer. The second conductive layer is etched to form an opening exposing a portion of the second dielectric layer. The second dielectric layer is then etched in the opening to form partially sloped sidewalls sloping outward at an upper surface of the dielectric layer. The photoresist layer is removed. The remaining second dielectric layer and the first electric layer is then anisotropically etched in the opening exposing the portion of the first conductive layer in the opening.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: April 23, 1996
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Girish A. Dixit, Fusen E. Chen, Alexander Kalnitsky
  • Patent number: 5466639
    Abstract: A method of forming contact to a semiconductor memory device feature comprises the steps of forming a first oxide layer over a feature such as a semiconductor substrate or a conductive line or plate, then forming a hard mask over the first oxide layer. A first patterned resist layer is formed on the hard mask, then the hard mask is patterned using the first resist layer as a pattern. The first resist layer is removed and a second oxide layer is formed over the hard mask. A second patterned resist layer is formed over the second oxide layer and the second oxide layer is etched using the second resist layer as a pattern while, during a single etch step, the first oxide layer is etched using the hard mask as a pattern, the hard mask functioning as an etch stop.
    Type: Grant
    Filed: October 6, 1994
    Date of Patent: November 14, 1995
    Assignee: Micron Semiconductor, Inc.
    Inventor: Philip J. Ireland
  • Patent number: 5466640
    Abstract: The object of the present invention is to prevent the electrical short between the adjacent metal wires by forming metal wires alternately between insulation films and to improve the process margin in the lithography process and the etching process.The present invention alternately forms a plurality of metal wires between the insulation films by manufacturing the photomask for metal wires in two separate pieces to correspond to the photomask for general metal wires for forming a plurality of metal wires which are densely constituted, and by utilizing the two photomasks.
    Type: Grant
    Filed: February 15, 1995
    Date of Patent: November 14, 1995
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Yang K. Choi
  • Patent number: 5466632
    Abstract: A method of forming field oxides with curvilinear boundaries between active regions on a substrate in an integrated circuit (IC) so that the stresses induced in the active regions due to the formation of field oxide can be reduced. Problems like junction leakage are reduced due to the rounded boundaries of the field oxides.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: November 14, 1995
    Assignee: United Microelectronics Corp.
    Inventors: Water Lur, Jiun Y. Wu
  • Patent number: 5462888
    Abstract: A process for fabricating transistors on a substrate is disclosed. In accordance with the process, stacks of material are formed on the surface of the substrate. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. A first layer of polycrystalline material is deposited over the substrate and selectively removed such that only those portions of the polycrystalline layer that surround the stacks of material remain. A layer of silicon nitride or silicon dioxide is then formed over the substrate surface. A first resist is then spun on the substrate surface. This resist aggregates near the stacks of material. An isolation mask is generated that leaves exposed only those areas of the substrate that correspond to the area of overlap between the first polycrystalline area and the stacks of material, which also contain a layer of polycrystalline material.
    Type: Grant
    Filed: June 6, 1994
    Date of Patent: October 31, 1995
    Assignee: AT&T IPM Corp.
    Inventors: Tzu-Yin Chiu, Frank M. Erceg, Francis A. Krafty, Te-Yin M. Liu, William A. Possanza, Janmye Sung
  • Patent number: 5432117
    Abstract: An insulating film and a silicon nitride film are formed on a semiconductor substrate. A resist film is patterned on the silicon nitride film. Thereafter, using the patterned resist film as a mask, the silicon nitride film is removed in such a manner that the film thickness is the maximum at its center portion and becomes gradually small downwardly in the neighborhood of the ends of the resist film pattern. The silicon nitride film which is thick at its center portion is adopted as a mask for selective oxidation.
    Type: Grant
    Filed: May 23, 1994
    Date of Patent: July 11, 1995
    Assignee: Rohm Co., Ltd.
    Inventor: Kouji Yamamoto
  • Patent number: 5413956
    Abstract: A method for producing a semiconductor laser device includes the steps of: forming window layers on either one of a top surface of an internal structure or a reverse surface of a substrate and on light-emitting end facets of the internal structure; forming a reflection film on the light-emitting end facets; removing the window layer formed on either one of the top surface or the reverse surface by using an etchant which hardly etches the reflection film; and forming electrodes on the surface from which the window layer is removed by etching and on the other surface. Another method for producing a semiconductor laser device includes the steps of: forming window layers on light-emitting end facets of the bars; inserting the bars into an apparatus having openings for forming electrodes and a supporting portion for preventing a positional shift between the bars and the openings, and forming the electrodes on the top surfaces and the reverse surfaces of the bars; and cutting the bars into the chips.
    Type: Grant
    Filed: December 22, 1992
    Date of Patent: May 9, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masanori Watanabe, Ken Ohbayashi, Kazuaki Sasaki, Osamu Yamamoto, Mitsuhiro Matsumoto
  • Patent number: 5395799
    Abstract: A workpiece is formed comprising a silicon substrate covered by four successive layers of silicon dioxide, undoped polysilicon, undoped WSi.sub.2 and a top layer of silicon dioxide on silicon nitride. The four layers are patterned to provide gate electrode structures each comprising the four layers. The workpiece is covered with a masking layer and the top layer of each structure is exposed through the masking layer. The top layers are then removed and ions of one conductivity type are implanted into the WSi.sub.2 layers of one group of gate electrode structures while another group of structures is masked, and ions of the other conductivity type are implanted into the WSi.sub.2 layers of the second group while the first group is masked. Thereafter, doped regions are formed in the substrate adjacent to the gate electrode structures.
    Type: Grant
    Filed: October 4, 1993
    Date of Patent: March 7, 1995
    Assignee: AT&T Corp.
    Inventor: Chen-Hua D. Yu
  • Patent number: 5356824
    Abstract: A process for the production of thin film transistor with a double gate and an optical mask consisting of depositing a conductive source and drain layer on an insulating substrate (31), producing photosensitive resin patterns fixing the location of the source and drain (34), etching the conductive layer, depositing on the structure obtained an opaque metal layer for forming the lower gate (42), carrying out thermal contraction of the resin patterns, depositing in isotropic manner a preferably a-C:H layer (39), dissolving the resin patterns, depositing a semiconductor layer (44), an insulating layer (45) and then a conductive layer (46) for producing the upper gate of the transistor and photoetching the stack formed by the conductive layer, the semiconducting layer and the insulating layer in order to fix the transistor dimensions and passivate the structure obtained with an electrical insulant (48).
    Type: Grant
    Filed: February 25, 1993
    Date of Patent: October 18, 1994
    Assignee: France Telecom Establissement Autonome de Droit Public
    Inventors: Yannick Chouan, Madeleine Bonnel
  • Patent number: 5342804
    Abstract: A semiconductor device structure (10) includes similar devices (30), (32), and (34) having different operating characteristics. Each similar device is formed on a semiconductor substrate layer (14) through openings (16), (18), and (20) in a mask layer (12). Each opening (16), (18), and (20) has a different feature size and spacing that allows for various thickness levels of layers within the similar devices (30), (32), and (34) due to desorption from the mask layer (12). The growth rate within each opening (16), (18), and (20) is inversely proportional to the feature size of the respective opening.
    Type: Grant
    Filed: May 19, 1993
    Date of Patent: August 30, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Edward A. Beam, III
  • Patent number: 5332681
    Abstract: The present invention provides a method for depositing a pattern of deposd material on or within a substrate, comprising the steps of: interposing a glass mask between a source and a substrate, the mask having channels therethrough which are arranged in a pattern and which have an average diameter of less than 1 micron; and depositing a material selected from the group of sources consisting of ions, electrons, photons, metals and semiconductor materials through the glass mask into or onto the substrate. The present invention also provides semiconductor devices made by this method.
    Type: Grant
    Filed: June 12, 1992
    Date of Patent: July 26, 1994
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Ronald J. Tonucci, Brian L. Justus
  • Patent number: 5328864
    Abstract: The present invention relates to a method of manufacturing a semiconductor device. In a semiconductor substrate formed with a first semiconductor region of P-type and a second semiconductor region of N-type and an insulating film formed between and extending into the first and the second semiconductor regions, gate electrodes of a laminate of a polysilicon layer and a silicide layer are formed on the insulating film covering the first and the second semiconductor regions. A gate electrode situated on the first semiconductor region has an end portion facing and spaced from an end portion of a gate electrode situated on the second semiconductor region. A masking layer is formed on the second semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The first semiconductor region is doped with an impurity of N-type, thereby forming a third semiconductor region in the first semiconductor region.
    Type: Grant
    Filed: May 13, 1991
    Date of Patent: July 12, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Keiichi Yoshizumi, Satoshi Kudo
  • Patent number: 5314837
    Abstract: The process of making a registration mark on an integrated-circuit substrate wherein photoimaging first is used to define an optically-recognizable mark on a predetermined position of the substrate, and the substrate then is covered with silicon dioxide. Photoresist then is applied over the substrate and selectively removed except over the mark. Etchant then is applied to remove all silicon dioxide except over the photoresist-covered mark. An epitaxial layer thereafter is grown over the substrate. The silicon dioxide over the mark prevents epitaxial growth in that region, so that the mark remains clear and optically visible for the rest of the IC processing.
    Type: Grant
    Filed: June 8, 1992
    Date of Patent: May 24, 1994
    Assignee: Analog Devices, Incorporated
    Inventors: Herbert J. Barber, Pamela A. Mayernik
  • Patent number: 5300446
    Abstract: On an insulating film (12) covering the surface of a semiconductor substrate (10), a gate electrode layer (14), a gate insulating film (16), and a semiconductor layer (18) such as silicon are sequentially deposited to form an under-gated MOS transistor. A flat coating film such as resist is formed covering the semiconductor layer (18). The coating film is then etched back to expose the surface of the semiconductor layer (18) at the area above the gate electrode layer (14). The left coating film is used as the mask for the selective growth of a mask material layer (24) such as tungsten on the exposed surface of the semiconductor layer (18) with a side-projection. After removing the left coating film, impurity ions such as BF2 are selectively injected in the semiconductor layer (18) using the mask material layer (24) as the mask to form a source region (18S) and a drain region (18D).
    Type: Grant
    Filed: May 5, 1993
    Date of Patent: April 5, 1994
    Assignee: Yamaha Corporation
    Inventor: Toshio Fujioka
  • Patent number: 5300454
    Abstract: A method for forming a first doped region (24) and a second doped region (26) within a substrate (12). A masking layer (14) overlies the substrate (12). A first region (20) of the masking layer (14) is etched to form a first plurality of openings. A second region (22) of the masking layer (14) is etched to form a single opening or a second plurality of openings different in geometry from the first plurality of openings. A single ion implant step or an equivalent doping step is used to dope exposed portions of the substrate (12). The geometric differences in the masking layer (14) between region (20) and region (22) results in the formation of the first and second doped regions (24 and 26) wherein the first and second doped regions (24 and 26) vary in doping uniformity, doping concentration, and doping junction depth.
    Type: Grant
    Filed: November 24, 1992
    Date of Patent: April 5, 1994
    Assignee: Motorola, Inc.
    Inventors: Robert C. Taft, Ravi Subrahmanyan
  • Patent number: 5298445
    Abstract: In a method for fabricating a FET of the present invention, first and second side walls are formed on a side surface of a gate electrode, and two n-GaAs layers are formed on an active layer by selective growth using the side walls as a mask. After that, the side walls are removed, whereby double recesses are formed around the gate electrode.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: March 29, 1994
    Assignee: NEC Corporation
    Inventor: Kazunori Asano
  • Patent number: 5294565
    Abstract: An epitaxial growth method of a single crystal of III-V compound semiconductor on the surface of a semiconductor substrate by supplying a molecular beam of a group III source material and a molecular beam of a group V source material onto the surface of the substrate in a chamber held in vacuum. With this method, the molecular beams comprises a molecular beam of a first group III source material composed of an organic metal compound of a group III element not having a halogen, a molecular beam of a second group III source material having a halogen chemically bonded to atoms of the group III element, and a molecular beam of a group V source material making a compound semiconductor with the group III element of the first group III material. By setting a substrate temperature at, for example, about 500.degree. C. a single crystal of III-V compound semiconductor can be satisfactorily selectively grown.
    Type: Grant
    Filed: July 22, 1992
    Date of Patent: March 15, 1994
    Assignee: NEC Corporation
    Inventor: Yasushi Shiraishi
  • Patent number: 5292676
    Abstract: A buried contact is formed in a substrate implantation of phosphorous or arsenic through a window cut into the insulating silicon oxide layer and a superimposed thin silicon layer. The photoresist used to etch the window is cut back a limited amount prior to implantation. The peripheral margin of the buried contact implanted through the exposed part of the thin layer of silicon lowers the threshold voltage of any parasitic MOS device which may be created between the buried contact and the remote N+source or drain structure.
    Type: Grant
    Filed: July 29, 1992
    Date of Patent: March 8, 1994
    Assignee: Micron Semiconductor, Inc.
    Inventor: Monte Manning
  • Patent number: 5292402
    Abstract: Materials of the lead perovskite family PbZr.sub.x Ti.sub.1-x O.sub.3 have been discovered to be excellent masking materials in the etching of silicon and silicon-containing materials with chlorine and fluorine -based plasmas. Generally, materials of the lead perovskite family are suitable masking materials for any material that is etched in chlorine and fluorine -based plasmas.
    Type: Grant
    Filed: July 9, 1992
    Date of Patent: March 8, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Norman E. Abt, Sheldon Aronowitz
  • Patent number: 5290713
    Abstract: A photoresist mask composed of a plurality of isolated plane patterns having no opening is formed on a main surface of a semiconductor substrate. The breakdown of the gate oxide film due to charge build up can be prevented because no photoresist mask opening patterning is involved.
    Type: Grant
    Filed: May 13, 1992
    Date of Patent: March 1, 1994
    Assignee: NEC Corporation
    Inventor: Shigeharu Matsumoto
  • Patent number: 5288659
    Abstract: An improved process for fabricating photonic circuits is disclosed. The inventive process starts with a growth of a base wafer comprising a stack of epitaxial layers of various materials. At least a portion of each of the material layers will ultimately be a functioning part of any of a number of devices which will form the PIC or will serve a role in at least one of the fabrication processing steps. Specific inventive processing steps are addressed to (1) interconnecting passive waveguides, active devices, and grating filtering regions without the substantial optical discontinuities which appear in the prior art, and (2) etching continuous waveguide mesas to different depths in different regions of the PIC so as to optimize the performance of each PIC device.
    Type: Grant
    Filed: September 14, 1992
    Date of Patent: February 22, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Thomas L. Koch, Uziel Koren
  • Patent number: 5282922
    Abstract: Hybrid circuit structures and methods of fabrication particularly suitable for the fabrication of high density multi-layer interconnects utilizing silicon substrates are disclosed. In accordance with the method, a layer of alumina is put down over the silicon substrate, typically having an oxide layer thereover, which layer of alumina acts as a blocking barrier to any subsequent plasma etching process for etching polymer layers thereover during the subsequent high density multilayer interconnect fabrication steps. Various representative high density multi-layer interconnect structures on silicon substrates and methods of forming the same are disclosed, including the inclusion of an adhesion enhancement layer over the layer of alumina to enhance the adhesion of a polymer which would not otherwise adhere well directly to the layer of alumina.
    Type: Grant
    Filed: March 11, 1992
    Date of Patent: February 1, 1994
    Assignee: Polycon Corporation
    Inventor: John J. Reche
  • Patent number: 5266156
    Abstract: Methods of forming local interconnects and high resistor polysilicon loads are disclosed. The local interconnects are formed by depositing a layer of polysilicon over CoSi.sub.2 in partially fabricated semiconductor wafers. The polysilicon is then coated with cobalt and annealed to form a second layer of of CoSi.sub.2. The method can be expanded to form a high resistor polysilicon load by depositing and patterning an oxide layer to form contact windows before application of the polysilicon layer. Another oxide layer is deposited over the polysilicon and patterned before application of the cobalt layer to define the areas which create the resistor load.
    Type: Grant
    Filed: June 25, 1992
    Date of Patent: November 30, 1993
    Assignee: Digital Equipment Corporation
    Inventor: Andre I. Nasr
  • Patent number: 5219775
    Abstract: A manufacturing method of a semiconductor memory device includes the steps of selectively forming a field oxide film and a gate oxide film on a semiconductor substrate, depositing a first conductive layer on an entire surface of the resultant structure, selectively etching the first conductive layer located in a region other than an element region, depositing a second conductive layer on an entire surface of the resultant structure, and etching the first conductive layer and the second conductive layer using the same mask to form a plurality of floating gates by the first conductive layer and to form a plurality of control gates by the second conductive layer, wherein the step of selectively etching the first conductive layer includes the first etching step of forming cell slits for separating the plurality of floating gates from each other and the second etching step of forming removed regions each of which includes only one end of each of the plurality of control gates.
    Type: Grant
    Filed: February 18, 1992
    Date of Patent: June 15, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukihiro Saeki, Osamu Matsumoto, Masayuki Yoshida, Takahide Mizutani, Nobuyoshi Chida, Tomohisa Shigematsu, Teruo Uemura, Kenji Toyoda, Hiroyuki Takamura
  • Patent number: 5219770
    Abstract: A semiconductor device comprising a drain and source region formed in a semiconductor substrate is provided. In order to provide a semiconductor device having a high packing density of the circuit elements, the contact windows for the source region and substrate region are combined into one opening in the source region. A common contact region is formed in a portion of the contact window for the source region by doping opposite conductivity type impurities. The depth of the converted region is deep enough to extend to the substrate. By connecting the source region and the substrate region in the common contact hole, the positioning margin and the wiring for connecting them are unnecessary and thus, the packing density of the devices in the MIS IC is increased.
    Type: Grant
    Filed: July 26, 1990
    Date of Patent: June 15, 1993
    Assignee: Fujitsu Limited
    Inventors: Takehide Shirato, Toshihiko Yoshida
  • Patent number: 5212111
    Abstract: A local oxidation of silicon (LOCOS) process for semiconductor manufacture in which a barrier layer for the oxidation process and for a subsequent field implant is formed of a ceramic material. The ceramic material is one that can be easily deposited on silicon with low stress and is characterized by an ion stopping power greater than that of silicon nitride. Suitable ceramic materials include metal oxides, titanates, carbides, glasses and ferroelectrics.
    Type: Grant
    Filed: April 22, 1992
    Date of Patent: May 18, 1993
    Assignee: Micron Technology, Inc.
    Inventors: Trung T. Doan, Gurtej S. Sandhu
  • Patent number: 5196368
    Abstract: A technique for achieving a substantially planar structure incorporating embedded vapor phase epitaxial growth involves the use of a window-frame shaped mask 40 of epitaxial growth resistant material to define a well in which embedded growth is to occur, and subsequently to ease mask registration problems in the location of a mask 60 employed while selectively removing unwanted material epitaxially grown on regions surrounding the well. Complementary format structures may also be formed in which epitaxial growth is provided up the sides of a mesa to substantially the same height as material grown on top of the mesa itself.
    Type: Grant
    Filed: May 8, 1991
    Date of Patent: March 23, 1993
    Assignee: Northern Telecom Limited
    Inventors: George H. B. Thompson, Piers J. G. Dawe, David A. H. Spear
  • Patent number: 5194118
    Abstract: A method for dry etching enabling good anisotropic processing even at a wafer cooling temperature closer to room temperature than with conventional low temperature etching. Etching is carried out using an etching gas including a compound containing oxygen (O) as a component element and a compound containing hydrogen (H) as a component element, or using a H.sub.2 O containing gas, while the wafer is cooled to a temperature not higher than 0.degree. C. H.sub.2 O produced or present in an etching system is condensed in a quantity monistically determined by the relation between the amount of the moisture and the dew point and is deposited as ice on a wafer surface. This ice contributes to anisotropic processing by being deposited on a pattern sidewall on which ions are not bombarded in the perpendicular direction. In this manner, etching at a temperature at which ice can be deposited is enabled without regard to the combinations between the layer of a material to be etched and the etching gas.
    Type: Grant
    Filed: December 27, 1991
    Date of Patent: March 16, 1993
    Assignee: Sony Corporation
    Inventor: Keiji Shinohara
  • Patent number: 5190894
    Abstract: In a method of manufacturing a semiconductor device, an Al wiring layer is formed on an interlevel insulator using a positive resist. The interlevel insulator has a recess portion formed on its surface corresponding to a position between two electrodes under the interlevel insulator. The Al wiring layer extends along the recess portion in the longitudinal direction and is formed to bridge the recess portion in a direction perpendicular to the logitudinal direction. The method includes the steps of arranging an Al layer on a region of the interlevel insulator including the recess portion, arranging the resist of the Al layer, exposing the resist to a light beam using a mask member having a light-shielding portion corresponding to the wiring layer, patterning the photoresist, and etching the Al layer using the patterned resist as a mask to form the wiring layer.
    Type: Grant
    Filed: April 19, 1991
    Date of Patent: March 2, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirohito Taneda, Masataka Takebuchi
  • Patent number: 5185293
    Abstract: A method is described for forming patterns in deposited overlayers on GaAs and for aligning the formed patterns with etch features produced through dry processing. The deposited overlayers on GaAs are protected during pattern formation and subsequent processing by a durable, process integrable mask of hydrogenated amorphous carbon.
    Type: Grant
    Filed: April 10, 1992
    Date of Patent: February 9, 1993
    Assignee: Eastman Kodak Company
    Inventors: Hans G. Franke, Eric T. Prince
  • Patent number: 5183775
    Abstract: An improved process for formation of a capacitor in a trench formed in a semiconductor wafer is disclosed. The improved process comprises selectively implanting oxygen through the bottom surface of the trench into the region of the wafer adjacent the bottom surface of the trench and through the surfaces at the top corners of the trench into regions of the wafer adjacent such surfaces at the top corners of the trench using a plasma formed in a plasma-assisted etching apparatus while maintaining a high negative DC bias on the wafer being implanted. Subsequent growth of oxide on the surfaces of the trench will cause the implanted oxygen to form additional oxide in the implanted regions of the wafer adjacent the bottom surface of the trench and adjacent the surface at the top corners of the trench to compensate for the lower oxide growth rates in these areas.
    Type: Grant
    Filed: January 23, 1990
    Date of Patent: February 2, 1993
    Assignee: Applied Materials, Inc.
    Inventor: Karl B. Levy
  • Patent number: 5158910
    Abstract: Self-aligned and/or isolated contacts are formed in a semiconductor device, while simultaneously providing device planarization. In one form, an imagable material is deposited directly on a substrate material. The imagable material is patterned to form a sacrifical plug on a portion of the substrate material. A substantially planar insulating layer is then deposited overlying the substrate material. The plug formed of the imagable material is then removed, thereby exposing a portion of the substrate material and defining a contact opening. A conductive layer is deposited and patterned to complete formation of a contact.
    Type: Grant
    Filed: November 26, 1990
    Date of Patent: October 27, 1992
    Assignee: Motorola Inc.
    Inventors: Kent J. Cooper, Michael P. Woo, Wayne J. Ray
  • Patent number: 5147825
    Abstract: An improved process for fabricating photonic circuits is disclosed. The inventive process starts with a growth of a base wafer comprising a stack of epitaxial layers of various materials. At least a portion of each of the material layers will ultimately be a functioning part of any of a number of devices which will form the PIC or will serve a role in at least one of the fabrication processing steps. Specific inventive processing steps are addressed to (1) interconnecting passive waveguides, active devices, and grating filtering regions without the substantial optical discontinuities which appear in the prior art, and (2) etching continuous waveguide mesas to different depths in different regions of the PIC so as to optimize the performance of each PIC device.
    Type: Grant
    Filed: August 26, 1988
    Date of Patent: September 15, 1992
    Assignee: Bell Telephone Laboratories, Inc.
    Inventors: Thomas L. Koch, Uziel Koren
  • Patent number: 5147812
    Abstract: A method for fabricating a sub-micron geometry semiconductor device using a chromeless mask. An optical exposure system (22) directs light through a chromeless mask (21). The chromeless mask (21) uses destructive interference of light to pattern a light sensitive material (32) on a semiconductor wafer (28). Phase differences in light passing thru chromeless mask (21) creates dark regions which form a non-exposed area of light sensitive material (37). The exposed light sensitive material is removed. The non-exposed area of light sensitive material (37) which remains, protects the gate material underneath it, as all other gate material is removed from the wafer. The non-exposed area of light sensitive material (37) is removed leaving a sub-micron gate (39). A drain and source is then formed to complete the device.
    Type: Grant
    Filed: April 1, 1992
    Date of Patent: September 15, 1992
    Assignee: Motorola, Inc.
    Inventors: James G. Gilbert, Fourmun Lee, Thomas Zirkle
  • Patent number: 5120669
    Abstract: An ion-implanted JFET has a channel barrier region at the top gate surface self-aligned to the source and drain, thereby maintaining sufficient separation between the channel barrier and the source and drain for attaining a high source/drain breakdown voltage. After a top gate and an underlying channel layer are ion-implanted through a thin oxide layer, a first photoresist layer is formed and patterned to expose surface portions of the thin oxide layer where source, drain and channel barrier regions are to be formed. Through these apertures in the first photoresist mask, shallow high impurity concentration surface region are ion-implanted. A second photoresist layer is formed on the first photoresist layer, and patterned to completely expose the first and second apertures in the first photoresist layer and to remove material of the second photoresistor layer down to the surface of the the oxide layer, while masking the barrier region.
    Type: Grant
    Filed: February 6, 1991
    Date of Patent: June 9, 1992
    Assignee: Harris Corporation
    Inventor: Gregory A. Schrantz