Abstract: The present invention comprises a method of selective epitaxy on a semiconductor substrate. The present invention provides a method of selectively forming high quality, thin GeSi layers in a silicon circuit, and a method for fabricating smaller semiconductor chips with a greater yield (more error free chips) at a lower cost. The method comprises forming an upper layer over a substrate, and depositing a reflectivity mask which is then removed over selected sections. Using a laser to melt the unmasked sections of the upper layer, the semiconductor material in the upper layer is heated and diffused into the substrate semiconductor material. By varying the amount of laser radiation, the epitaxial layer is formed to a controlled depth which may be very thin. When cooled, a single crystal epitaxial layer is formed over the patterned substrate. The present invention provides the ability to selectively grow layers of mixed semiconductors over patterned substrates such as a layer of Ge.sub.x Si.sub.

Abstract: A method of forming a planar ITO gate electrode structure with sub-micron spacing includes forming L-shaped nitride spacer portions.

Abstract: A method of forming conducting pillars in a semiconductor integrated circuit which are defined by insulating spacers of a previous conducting layer. The method includes the steps of forming parallel-spaced conductor lines on a silicon substrate having spaces therebetween; forming insulating spacers on the sidewalls of the conductor lines while leaving a gap between the lines; filling the gaps with a conductor film and etching the film to form conducting pillars; and photo-etching contact vias to the conducting pillars for forming a multilevel interconnect between the conductor lines and another conductor.

Abstract: A method is described for selectively masking sidewall regions of a concave surface formed in a semiconductor body, the method comprising the steps of: forming a conformal layer of masking material on a sidewall of the concave structure; emplacing in the concave structure, a selectively removable material that partially fills the concave structure, an upper surface of the material determining the edge of a region of the concave structure to be masked; removing a portion of the conformal layer above the upper surface of the selectively removable material; and removing the selectively removable material to leave a region of remaining conformal material as a mask.

Abstract: A method of partially eliminating the field oxide bird's beak over a storage cell and slightly enlarging the storage cell active area without adding any process steps is described. A photomask is used during a buried contact etch to reduce the field oxide bird's beak both vertically and horizonally. The storage cell active area is further enlarged during a first polysilicon etch step without adding process steps. At that point, the wafer is completed by existing techniques.

Abstract: After a base region and a base contact region, a diffused resistance region and a pair of contact regions formed at each end of the diffused resistance region are formed, an silicon oxide film of essentially uniform thickness is formed anew on the surface of an epitaxial layer. In the silicon oxide film, a collector contact/doping window, a base contact window, an emitter contact/doping window, a lower layer electrode contact window, and a diffused resistance element contact window are formed simultaneously, then the base contact region and the diffused resistance element contact regions are shielded by a mask and a collector contact region, an emitter contact region, and a lower layer electrode contact region are doped. The method of manufacturing a semiconductor integrated circuit of the present invention has the advantages that all insulating films have a uniform film thickness, eliminates the problems of side etching when the contact windows or dopant windows are formed or of etching the element regions.

Abstract: A method for fabricating an active matrix substrate is disclosed which includes the following steps: forming an island region of a first semiconductor film on a prescribed insulating substrate; forming a first insulating film and a second semiconductor film on said first insulating film; forming a second insulating film on said second semiconductor film and thereafter forming a prescribed pattern of the second insulating film; depositing prescribed metal on the pattern and thereafter forming a compound of the second semiconductor film and the metal; removing unreacted portion of the metal; and etching said second semiconductor film and said first insulating film using said compound as a mask.

Abstract: A semiconductor body (1) is provided by growing epitaxial layers of semiconductor material on a substrate placed within a processing chamber and forming a mesa structure (3) on an upper epitaxial layer (2). The mesa structure (3) is formed by epitaxially growing, with the semiconductor body (1) still within the processing chamber, a first layer (4) of a semiconductor material different from that of the upper layer (2) on the upper layer (2) and the opening a window (5) in the first layer (4) to expose an area (2a) of the upper layer (2). A further layer (6) of a semiconductor material different from that of the first layer (4) is then epitaxially grown on the first layer (4) and on the said area (2a) of the upper layer. The first layer (4) is then selectively etched so as to remove the first layer (4) and the part of the further layer (6) carried by the first layer ( 14) leaving the remainder (60a, 60b) of the further layer (6) in the window (5) to form the mesa structure (3).

Abstract: High voltage (200-400 volts) Zener diodes having much improved resistance to degradation under 150.degree. C. HTRB are obtained by a junction passivation comprising a thermal oxide next to the silicon, covered by a TEOS CVD glass, a CVD nitride and a further TEOS CVD glass. Multiple Zener voltages are obtained with otherwise identical, simultaneous wafer processing steps by using epi-wafers having different epi doping and thickness. Back-side for wafer thinning is avoided.

Abstract: A light emitting semiconducting structure is formed over a light reflecting surface using epitaxial growth techniques. The light reflecting surface is provided by an appropriate metal layer intermediately disposed between two dielectric layers, this multi-layer structure is disposed intermediate between an underlying substrate and the overlaying light emitting semiconducting components. The light reflecting surface provides enhanced photon reflectance for the light emitting device. The active region of the light emitting device is formed using epitaxial growth techniques.

Abstract: A method of fabricating a MOS field effect semiconductor device having an LLD structure is described in which an insulating film is formed on a gate electrode and a layer of polycrystalline silicon, oxide, high melting point metal or a silicide of a high melting point metal is formed on a wafer and etched away by anisotropic RIE, except a portion thereof on a sidewall of the gate. With the resulting structure, degradation of the transconductance of the device due to injection of hot carriers is prevented. Also, the size of the device can be minimized without unduly increasing the resistances of the drain/source region, the gate electrode, and the contacts of the device.

Abstract: A monolithic integrated circuit of either the MOS or CMOS type comprises an intermediate layer of polycrystalline silicon, a layer of a silicide of a refractory metal overlying said polycrystalline silicon layer, and regions of preset area and preset paths formed in the polycrystalline silicon layer and the silicide layer; the preset area regions and preset paths forming respectively high resistivity resistances and low resistivity interconnection lines for an intermediate connection level.

Abstract: A method of manufacture of thin film, field-effect transistors formed on a transparent substrate and with transparent, conductive source and drain electrodes, uses initially deposited gate electrodes as a mask in association with photolithographic processing using radiation transmitted through the substrate and electrodes to minimize parasitic capacitance between the gate and source and drain electrodes.

Abstract: A self-aligned gate (SAG) transistor or FET is described which transistor overcomes several disadvantages of the prior art for making SAG field-effect transistors. The disadvantages noted above result from the fact that current SAG FET's have a symmetrical structure, with n+ regions on either side of the gate electrode. This invention provides a means of masking off a region on the drain side of the gate electrode before performing an n+ implant, so that the n+ implanted region is asymmetrical on the two sides of the gate electrode. This has the desired beneficial effect of reducing the parasitic source resistance, without the deleterious effects on gate-drain breakdown voltage, gate-drain capacitance, and output resistance that invariably accompany a high doping level on the drain side of the gate. Using this technique, substantially increased performance can be obtained from a self-aligned FET.

Abstract: In a process of fabricating a MISFET of the LDD structure, a gate insulation film is formed on a semiconductor substrate or a semiconductor thin film. A gate electrode is formed on the gate insulation film, and lightly-doped regions are formed in the semiconductor substrate or the semiconductor thin film by ion implantation using the gate electrode as a mask. Next, a CVD oxide film containing an impurity is unselectively deposited, sidewalls are formed along the edges of the gate electrodes by anisotropic etching, and heavily-doped source and drain regions are formed in the semiconductor substrate or the semiconductor thin film by ion implanation using the gate electrode and the sidewalls as a mask.

Abstract: Disclosed is a device for making multi-layer crystals. It includes a holder and a plurality of masking elements adapted to be secured successively to the holder. The masking elements have cover pieces that overlie the area protected by the preceding cover pieces and have an additional cover piece. This produces a device having progressively truncated corner sections. There is thus formed a multi-layered crystal having portions adapted to be connected to electrical leads.

Abstract: A planar process for fabricating an optoelectronic integrated circuit device is described. The process includes the in situ formation of laser diode mirror facets comprising the steps of providing a semi-insulating gallium arsenide substrate having thereon layers of n-doped gallium arsenide, n-doped aluminum gallium arsenide, and undoped gallium arsenide; patterning and etching the undoped gallium arsenide layer into a mandrel having substantially vertical walls; establishing insulator sidewalls on the vertical walls; removing the mandrel, thereby exposing the inner walls of the insulator sidewalls and leaving the insulator sidewalls self-standing; removing the aluminum gallium arsenide using the insulator sidewall as a mask; and forming a laser diode within the region between the insulator sidewalls and creating the mirror facets with the inner walls of the insulator sidewalls. Mirror facets formed in accordance with this process are substantially free of contaminants.

Abstract: A method of manufacturing an insulated gate field effect transistor is described. The method comprises providing a gate layer (6) on an insulating layer (12) on one surface (4) of a semiconductor body (1) and source regions (2) of one conductivity type within a respective body region (14), a portion of each body region (14) underlying a portion of the gate layer to provide a channel area extending between the source region (2) and a drain region (3) meeting another surface (5) of the semiconductor body opposite the one surface (4).

Abstract: A method for forming substrate contacts in an integrated circuit structure uses a layer of conductive material, preferably polycrystalline silicon, applied to the surface of the semiconductor structure to make electrical contact with exposed portions of the substrate. The polycrystalline silicon layer is then coated with a nitride layer. A via mask which is opaque over the region where a contact will be formed produces a photoresist stud smaller that the original via mask. The photoresist stud is used to pattern the nitride to remain only over the contact region. Following this, the polycrystalline silicon is oxidized except at the nitride mask, forming a bird's beak beneath edges of the nitride. The resulting contact is smaller than the photolithographic limit of the via mask and thus allows for smaller space allocated for contact regions and smaller total structure.

Abstract: A method of selective epitaxial growth for compound semiconductor includes the steps of forming a layer of group IV element semiconductor, such as Ge, with a predetermined pattern on a compound semiconductor substrate and forming a compound semiconductor layer selectively on the compound semiconductor substrate by alternately supplying a gas of compound containing a group III or II element, such as trimethylgallium, triethylgallium and triisobutylaluminum, and a gas of compound containing a group V or VI element, such as AsH.sub.3, onto both surface of the layer of group IV element semiconductor and the compound semiconductor substrate. Another semiconductor layer of group IV element semiconductor or compound semiconductor may be formed on the layer of group IV element semiconductor by organometallic vapor phase epitaxy or MBE.

Abstract: When high-vacuum methods are used in the manufacture of miniaturized devices such as, e.g., semiconductor integrated-circuit devices, device layers on a substrate are preferably patterned without breaking of the vacuum. Preferred patterning involves deposition of a semiconductor mask layer, generation of the pattern in the mask layer by ion deflected-beam writing, and transfer of the pattern by dry etching. When the mask layer is an epitaxial layer, further epitaxial layer deposition after patterning may proceed without removal of remaining mask layer material.

Abstract: A triangular ring laser utilizing total internal reflection at two angled facets and a preselected amount of reflection at a third angled facet is disclosed. Partial transmission occurs through the third facet to reduce the threshold current required for achieving stimulated emission. The facets are at three corners of the triangular laser, and are formed by chemically assisted ion beam etching in which SiO.sub.2 is used as a mask, whereby smooth vertical walls are produced to form facets having reflective characteristics equivalent to those formed by cleaving.

Abstract: A method of manufacturing a DMOS is disclosed. On a polysilicon gate layer, a multiple dielectric mask including studs (71) defines a window (70) for body implantation (80) into a substrate. Unmasked regions of polysilicon and substrate are oxidized to form oxide regions (84,85,88). Subsequent to the removal of the protective studs and a portion of the oxide, remaining oxide regions (90,91,92) act as a mask for source implantation (99,100).

Abstract: A semiconductor optical element having a layer which exhibits a function of diffraction grating between a first cladding layer and a second cladding layer, wherein the layer which exhibits the function of diffraction grating consists of a superlattice layer in which crystal layers are periodically mixed to constitute a semiconductor grating layer.

Abstract: A masking layer is formed on the light-emitting mirror surface of a semiconductor laser body. The masking layer is capable of blocking or cutting off light emitted from the semiconductor laser body and of being made optically transparent by exposure to the light emitted from the semiconductor laser body dependent on the amount of energy of the emitted light. When the light is emitted from the semiconductor laser body on which the masking layer is deposited, a small light-emitting hole is defined in the masking layer, the light-emitting hole having a desired diameter commensurate with the amount of energy of the emitted light which is applied to the masking layer.

Abstract: A method for manufacturing a semiconductor device of the invention comprises the steps of(a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulating film;(b) forming a source region and a drain region by doping said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate;(c) forming a self-aligned insulating layer on the side walls of the gate electrode;(d) forming a self-aligned metal layer on a region on which an insulating film is not formed, the region including the source region and the drain region; and(e) forming electrodes which are connected to the source region, drain region and gate electrode.

Abstract: A method is disclosed for fabricating a semiconductor device and especially for contacting a semiconductor device. A silicon substrate is provided which has a device region formed at the surface thereof and which is contacted with a silicide. An insulating layer overlies the substrate and has an opening therethrough which exposes a portion of that device region. Titanium nitride is deposited in a blanket layer overlying the silicide and the insulating layer. A leveling agent such as a spin-on glass is applied to the structure to substantially fill the opening. That leveling agent is then anisotropically etched to leave the leveling agent only in the opening. The leveling agent is used as an etch mask to remove the portion of titanium nitride which is located outside the opening. After removing the remaining leveling agent, the titanium nitride in the opening is used as a nucleating surface for the selective deposition of a tungsten plug which fills the contact opening.

Abstract: An MOS structure and a method for making same, including the formation of el-shaped shielding members used to form one or more lightly doped drain regions to avoid short channel and punch-through problems is disclosed which comprises forming a shielding layer of an insulating material over a gate electrode on a substrate; forming another layer of a dissimilar material over the shielding layer; anisotropically etching the layer of dissimilar material to form spacer portions adjacent the sidewalls of the gate electrode; removing the portions of the shielding layer not masked by the spacer portions, leaving one or more el-shaped shielding members; removing the spacer portions; N+ or P+ implanting the substrate at a sufficiently low energy to prevent penetration of the dopant through the el-shaped shielding member to form a highly doped source/drain region in the substrate not shielded by the el-shaped shielding member or the gate electrode; N- or P- implanting the substrate at a sufficiently high energy to penet

Abstract: A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.

Abstract: An improved patterning process, useful for the metallization of highly efficient photovoltaic cells, the formation of X-ray lithography masks in the sub half-micron range, and in the fabrication of VLSI and MMIC devices, is disclosed. The improved patterning process includes the steps of providing a substrate with a photoactive layer, patterning the photoactive layer with an inclined profile, depositing on both the substrate and the patterned photoactive layer a layer of disjointed metal such that the thickness of the metal layer exceeds that of the patterned photoactive layer and that the metal layer deposited on the substrate is formed with walls normal to the surface of the substrate. Preferably, the deposition of the disjointed metal layer is effected by evaporative metallization in a direction normal to the surface of the substrate. The deposited metal layer on the substrate is characterized by a high aspect ratio, with a rectangular cross section.

Abstract: A method for producing a hole in a polymer film includes the steps of depositing a conductive layer onto the polymer film and irradiating a spot on the layer with a burst of focused laser energy at a level sufficient to form an opening in the film and, subsequently, plasma etching the film so as to form a hole of desired depth in the polymer film underlying the opening in the conductive layer. This method is particularly applicable to the formation of multichip intergrated circuit packages in which a plurality of chips formed in a semiconductor wafer are coated with a polymer film covering the chips and the substrates. The holes are provided for the purpose of interconnecting selected chip contact pads via a deposited conductive layer which overlies the film and fills the holes.

Abstract: A method is disclosed for fabricating a VLSI multilevel metallization integrated circuit in which a first dielectric layer (10), a thin silicon layer (16), and then a second dielectric layer (18) are deposited on the upper surface of a substrate. A trench (20) is formed in the upper, second dielectric layer leaving a thin layer of the second dielectric layer overlying the thin silicon layer. A contact hole (26) is then etched through the central part of the thin layer of the second dielectric layer, the thin silicon layer and the first dielectric layer to the surface of the substrate. Using the remaining outer portion (24a) of the thin layer of the dielectric layer as a mask over the underlying portion of the thin silicon layer, metal (28) such as tungsten is selectively deposited into the contact hole. The remaining portion of the thin layer of the second dielectric layer is then removed and the trench is selectively filled with a metal that is in electrical contact with the metal filling the contact hole.

Abstract: A method of forming complementary metal oxide semiconductor field-effect transistors (CMOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effects, to increase punch through voltage and to increase gate-aided breakdown voltage.

Abstract: With an increase of integration density in an integrated circuit, the channel length of MIS FET becomes shorter and shorter, which causes a hot carrier effect. To solve the problem, the doping profile of source/drain regions and doping amount must be precisely controlled such that a strong electric field is not generated in a transition region from channel to drain. To obtain this objective, the present invention discloses a method, in which reflowed sidewalls of doped silicate glass having a gentle slope are formed on both sides of a gate electrode, and the gate electrode and the sidewalls thus formed are used as a mask for ion implantation. The depth of ion implantation and the doping amount change gradually from the channel region to the drain region avoiding a generation of the strong electric field and thus alleviates the short channel trouble.

Abstract: A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDs) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Other materials such as CVD polysilicon may also be useful for the sidewall spacers. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implanation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation. The invention also includes the use of a differential oxide layer. A second set of disposable sidewall spacers or the use of permanent sidewall spacers form optional embodiments.

Abstract: A method for using a self-aligned electromigration barrier metal and flow oxidation mask utilizing titanium nitride as the preferred embodiment. After providing a metallic mask layer, contact openings in a semiconductor substrate are sputtered with suitable metal (in the preferred embodiment, titanium) in a suitable atmosphere (in the present embodiment, nitrogen) to deposit a thin layer of material at the exposed junction sites. This deposited material serves as a barrier to spiking with an overlying metallic interconnect layer, improves contact adherence, and serves as an oxidation mask during subsequent high temperature flow processing steps. The metallic mask layer is removed, and optionally an interlevel oxide layer is flowed to provide a better contact between a subsequent metallic interconnect level and the barrier metal/oxidation mask material. After any flow step, a metallic contact layer may be formed to the silicon junction through the barrier metal/oxidation mask material.

Abstract: A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.

Abstract: A method for manufacturing thin-film transistor comprises steps of sequentially forming in laminar state a gate film, an insulating film and a conductive film having a transparent electrode film and an amorphous silicon film added with an impurity thereto on the top surface of glass substrate or layer; irradiating ultraviolet ray from the bottom surface side of the substrate to expose negative photoresist film on said conductive film and to etch the same; and forming an amorphous semiconductive film on the structure. In this manner, source and drain electrodes are respectively self-aligned with the gate electrode and contacted therewith through a semiconductive film and a low resistive and semiconductor film.

Abstract: A method of producing a semiconductor memory device comprises the steps of forming a first mask on a substrate and forming an opening in the first mask, implanting impurity ions into the substrate from the opening in the first mask so as to form an impurity region, forming a side wall layer of oxidation-resistant material having a predetermined width on a side surface of the opening in the first mask, forming a tunnel region having a width determined by the predetermined width by using the oxidation-resistant side wall layer as a second mask and forming a gate part on the tunnel region.

Abstract: A simple process is provided for making two self-aligned recessed oxide isolation regions of different thicknesses which includes the steps of defining first and second spaced apart regions on the surface of a semiconductor substrate, forming a protective layer over the first region, forming a first insulating layer of a given thickness within the second region while the first region is protected by the protective layer, removing the protective layer from the first region and forming a second insulating layer thinner than that of the first layer within the first region. Field regions may be ion implanted prior to forming the insulating layers.

Abstract: Edge conduction in a silicon-on-sapphire transistor is minimized by a process which permits precise doping of the edge channel regions of the transistor. The silicon island (19) containing the transistor (24) is precisely doped around its edges by ion implanting an epitaxial silicon layer (13) on a sapphire substrate (11), with an oxide mask (29) covering, with the exception of a narrow peripheral edge (37), the portion of the silicon which is eventually to form the island (19') on which the transistor is to be constructed. The mask (29) is then expanded by the addition of a sleeve (43) to cover the additional peripheral edge region (37) in the silicon. When the silicon is subsequently etched using the expanded oxide pattern 45 as a mask, the periphery of the remaining silicon will be doped to a predetermined depth (37) corresponding to the width of the sleeve (43).

Abstract: A multiple-zone junction termination extension region is formed adjacent a reverse-blocking junction in a semiconductor device to increase the breakdown voltage of such device. A single mask is used to form the multiple-zone JTE region, with the mask having different patterns of openings in the different zones of the mask. Adjacent openings are maintained with a center-to-center spacing of less than 25 percent of the depletion width of the reverse-blocking junction in a voltage-supporting semiconductor layer adjoining the reverse-blocking junction at the ideal breakdown voltage of the junction. As a consequence, the resulting non-uniformities in doping of the various zones of the JTE region are negligibly small. An alternative JTE region is finely-graduated in dopant level from one end of the region to the other, as opposed to having multiple zones of discrete doping levels.

Abstract: An insulated-gate semiconductor device, such as an IGFET or IGT, with improved source-to-base shorts includes, in a semiconductor wafer, a drain region, a voltage-supporting region, a base region, and a source region. Generally parallel gate fingers of refractory material are insulatingly spaced above the wafer. Elongated base portions are provided between, and preferably registered to, a respective pair of adjacent gate fingers. Elongated source portions are each situated within a respective base portion and each is preferably registered to a respective pair of adjacent gate fingers. Generally parallel shorting portions are included in the wafer and are oriented transverse to the gate fingers, whereby the shorting portions can be formed without a critical alignment step. The shorting portions adjoin the base portions and also a source electrode so as to complete source-to-base electrical shorts.

Abstract: Method of producing two-layer metal interconnections in a semiconductor integrated circuit structure coated with silicon dioxide. Masking material is deposited on the silicon dioxide. Openings are formed in the masking material and then in the silicon dioxide to expose contact areas on the integrated circuit structure. A first metal, tungsten, is deposited on the masking material and on the contact areas exposed at the openings. The masking material and the overlying tungsten are stripped off leaving tungsten only on the contact areas. A second metal, aluminum, is deposited over the silicon dioxide and the tungsten on the contact areas. Aluminum is selectively removed to form a pattern of conductive members of tungsten-aluminum on the contact areas and of aluminum over the silicon dioxide.

Abstract: A molybdenum mask is used instead of a photoresist mask in defining and etching an oxide-encapsulated molybdenum gate in a VLSI manufacturing method. The molybdenum mask is first defined by a photoresist mask, then the photoresist is removed, leaving the molybdenum mask. A long over etch can then be tolerated so that oxide filaments can be avoided; this would be otherwise unreliable due to damage to photoresist during the over etch.

Abstract: A method for manufacturing a semiconductor device of the invention comprises the steps of(a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulating film;(b) forming a self-aligned insulating film at least on a side wall of said gate electrode;(c) forming a self-aligned metal or metal silicide film on a region on which an insulating film is not formed, said region including a source region, a drain region and a diffusion interconnection region which is an extended part of at least one of said source region and said drain region, or prospective regions for said source, drain and diffusion interconnection regions; and(d) forming said source region, said drain region and said diffusion interconnected region which is the extended part of at least one of said source region and said drain region, by doping at least one time said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate any time after st

Abstract: The present invention is to provide a method for manufacturing a semiconductor device of high efficiency and high integration density. The method for manufacturing a semiconductor device comprises the steps of forming semiconductive layers (30), (31) and (31') having on the surface thereof a concave portion, forming a nitride layer (35) within the concave portions forming with the nitride layer (35) as a mask an oxide layer (39) on the surface of the semiconductive layer (30), removing said nitride layer (35) and introducing an impurity into the semiconductive layers (31) and (31') with the oxide layer (39) as a mask. In accordance therewith, the elements can be made finer and hence the method of this invention is suitable for manufacturing an IC device high in efficiency and high in integration density.

Abstract: Apart from the base fingers (10), this transistor includes a titanium silicide coating, from which the base diffusions have been formed, and a silicon nitride coating (4). The edges of sandwiches made up of bands (3) and (4) are bordered by a silica bank (7) formed automatically by deposit and anisotropic attack, without additional masking. The emitter fingers (9) are overhung by a polycrystalline silicon layer (8) from which doping of these fingers has been obtained.The possibility is also obtained, automatically and without masks alignment, of having the emitter and base fingers brought firmly together with minimum protection distances.

Abstract: A process is described for fabricating self-aligned buried doped regions in semiconductor devices and integrated circuits which avoids any need for delineation of the buried doped regions in the active portions of the device. Avoiding delineation improves the quality of the epitaxial layer used to cover the buried doped regions thereby improving overall performance and yield. Multiple mask layers are used in connection with a single mask pattern to achieve self-alignment. One mask layer consists of a material with a modifiable etch rate, e.g. polysilicon. A portion of the single crystal substrate is rendered non-single crystal and used as an alignment key which is propagated through the epitaxial layer grown over the undelineated buried doped regions. The dimensions and separations of the self-aligned buried doped regions can be precisely controlled.

Abstract: A method for manufacturing semiconductor devices is presented. The method comprises the steps of opening two windows on an insulating layer covering a semiconductor substrate, and forming a polysilicon layer over the entire surface of the insulating layer and the windows. Donor and acceptor impurities are respectively implanted into the portions of the polysilicon layer corresponding to the two opening windows through the appropriate photoresists. The doped impurities are thereafter subjected to annealing to form two different conduction type regions under the two opening windows. Thereafter, a metal layer and a photoresist are deposited in order to make the metal electrodes for each conduction region. Thus, the patterning of the polysilicon can be made in self-alignment with the etching mask, and the formation of two different conduction type semiconductor regions are simultaneously attained.