Etch And Refill Patents (Class 148/DIG50)
  • Patent number: 6150233
    Abstract: An underlaid silicon oxide film (2) and a polycrystalline silicon film (5) are formed in this order on a surface (1S) of a silicon substrate (1). The polycrystalline silicon film (5) and the underlaid silicon oxide (2) are opened by anisotropic etching, to form a trench (21) extending to the inside of the semiconductor substrate (1). A silicon oxide film (11) formed by HDP-CVD is buried in the trench (21). A resist (41) is formed only on a surface of the silicon oxide film (11) in a device isolation region (20). The silicon oxide film (11) in an active region (30) is removed by dry etching with the resist (41) as a mask. After removing the resist (41), only the polycrystalline silicon film (5) is removed by dry etching. The underlaid oxide film (2) is removed by wet etching with hydrofluoric acid. By this method of manufacturing a semiconductor device, the surface of the semiconductor substrate and a trench-type device isolation are flattened effectively at low cost.
    Type: Grant
    Filed: July 20, 1998
    Date of Patent: November 21, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuyuki Horita, Takashi Kuroi, Maiko Sakai, Hiromichi Kobayashi
  • Patent number: 6146974
    Abstract: A method of fabricating shallow trench isolation (STI) forms a trench in a substrate and a liner oxide layer in the trench. A first high density plasma chemical vapor deposition (HDPCVD) is performed to form a conformal oxide layer on the liner oxide layer, without applying bias to the substrate. A second HDPCVD is then performed to form an oxide layer that fills the trench and covers the conformal oxide layer on the conformal oxide layer.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: November 14, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Cheng-Yuan Tsai, Gwo-Shii Yang, Juan-Yuan Wu
  • Patent number: 6143625
    Abstract: An isolation trench (60) may comprise a trench (20) formed in a semiconductor layer (12). A barrier layer (22) may be formed along the trench (20). A protective liner (50) may be formed over the barrier layer (22). The protective liner (50) may comprise a chemically deposited oxide. A high density layer of insulation material (55) may be formed in the trench (20) over the protective liner (50).
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: November 7, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Ih-Chin Chen, Amitava Chatterjee, Somnath S. Nag
  • Patent number: 6143623
    Abstract: A semiconductor device includes a semiconductor substrate in which a trench for element isolation is formed, and an element isolation oxide film buried into the trench in such a manner that the element isolation oxide film is projected from the surface of the semiconductor substrate. The element isolation oxide film which is an element isolation insulating film for defining an element forming region on the semiconductor substrate has a projection portion above the surface of the semiconductor substrate. The projection portion has the width wider than that of the trench. The projection portion and a contact portion made in contact with the semiconductor substrate within the trench are made of thermal oxide films, and a portion other than the projection portion and the contact portion is made of a CVD dioxide film.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: November 7, 2000
    Assignee: Nippon Steel Corporation
    Inventors: Nobuyuki Tsuda, Hideki Fujikake
  • Patent number: 6114220
    Abstract: A method of fabricating a shallow trench isolation includes formation of a trench in a substrate. An oxide layer is formed on the substrate to fill the trench. A barrier layer and a coating layer are formed in sequence over the substrate. A first etching step is performed to remove a portion of the coating layer and the oxide layer to at least expose the oxide layer on the mask layer. A second etching step is performed to remove the other portion of the coating layer and the oxide layer until exposing the mask layer. Thus, micro-scratches and defects do not happen and thus the invention prevents the occurrence of bridging effect and short circuits.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: September 5, 2000
    Assignee: United Microelectronics Corp.
    Inventor: Meng-Jin Tsai
  • Patent number: 6114217
    Abstract: Disclosed is a method for providing an insulation trench on a semiconductor substrate. The method includes the steps of depositing a pad oxide layer and a nitride layer on a semiconductor substrate; etching the nitride layer and the pad oxide layer and depositing a first insulating layer; forming spacers along sidewalls of the pad oxide layer and the nitride layer by anisotropic etching the first insulating layer; forming trenches by etching the semiconductor substrate; forming a trench insulating layer pattern by depositing a second insulating layer and etching the same; and polishing the trench insulating layer pattern.
    Type: Grant
    Filed: November 24, 1998
    Date of Patent: September 5, 2000
    Assignees: ANAM Semiconductor Inc., Amkor Technology Inc.
    Inventor: Young-Tack Park
  • Patent number: 6114223
    Abstract: In one aspect, the invention pertains to a method of forming a gettering region within an Si semiconductor wafer, the method including: a) providing a semiconductor material wafer; b) providing a background region within the semiconductor material wafer, the background region being doped with a first-type conductivity enhancing dopant, the first-type conductivity enhancing dopant being either n-type or p-type; c) implanting a second-type conductivity enhancing dopant into the background region to form a second-type implant region entirely contained within the background region, the second-type conductivity enhancing dopant being of an opposite type than the first-type conductivity enhancing dopant of the background region; and d) implanting a neutral-conductivity-type conductivity enhancing dopant into the second-type implant region to form a metals gettering damage region entirely contained within the second-type implant region. The invention also pertains to gettering region structures.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: September 5, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Jeffrey W. Honeycutt
  • Patent number: 6110801
    Abstract: A method of fabricating trench isolation is disclosed: firstly, the areas of trench isolation are formed on a silicon substrate, and then filled by depositing an oxide layer. Secondly, a process of planarization is performed to remove the extra oxide. After that, a layer of photo resist is coated and patterned, such that the areas of trench isolation are protected by the layer of photo resist. The oxide protected by the photo resist is not removed by the subsequent etching process. During the process of stripping the photo resist, the oxide at the edges of the areas of trench isolation will be also rounded and no more in the shape of right angle. Therefore, the kink effect in the prior arts is no more existent. Thereafter, a gate oxide layer and a polysilicon layer are formed in sequence. The trench isolation according to the present invention is thus accomplished.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: August 29, 2000
    Assignee: Mosel Vitelic Inc.
    Inventors: Chung-Shih Tsai, Der-Tsyr Fan
  • Patent number: 6093621
    Abstract: A method of fabricating a shallow trench isolation. A pad oxide and a dielectric layer are formed on a substrate. A trench is formed in the substrate penetrating through the pad oxide layer and the dielectric layer. The dielectric layer around the edge of the trench is removed to expose the substrate. The trench is filled to form a T-shaped insulation plug.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: July 25, 2000
    Assignee: Vanguard International Semiconductor Corp.
    Inventor: Horng-Huei Tseng
  • Patent number: 6090685
    Abstract: A semiconductor structure pad oxide layer is enlarged by local oxidation of silicon to form a field oxide. An etchback causes the thinnest portions of the field oxide to recede such that a portion of the semiconductor substrate is exposed. An etch through the exposed portion of the semiconductor substrate forms a microtrench between the field oxide and the nitride layer with a lateral dimension that is less than that currently achievable by conventional photolithography. The microtrench is then filled by oxide or nitride growth or by deposition of a dielectric material. In another embodiment, formation of the microtrench is carried out as set forth above, but the nitride layer is removed immediately following trench formation. Alternatively, the pad oxide layer is stripped and a new oxide layer is regrown that substantially covers all exposed surfaces of active areas of the semiconductor substrate.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: July 18, 2000
    Assignee: Micron Technology Inc.
    Inventors: Fernando Gonzales, Mike Violette, Nanseng Jeng, Aftab Ahmad, Klaus Schuegraf
  • Patent number: 6090684
    Abstract: A shallow groove isolation structure (SGI) electrically insulates adjoining transistors on a semiconductor substrate. A pad oxide film is formed on the semiconductor substrate and an oxidation inhibition film is formed on the pad oxide film. Parts of the oxide inhibition film and pad oxide film are removed to form the groove. In particular, the pad oxide film is removed from an upper edge of the groove within a range of 5 to 40 nm. A region of the groove is oxidized in an oxidation environment with a cast ratio of hydrogen (H.sub.2) to oxygen (O.sub.2) being less than or equal to 0.5. At this ratio, the oxidizing progresses under low stress at the upper groove edges of the substrate thereby enabling rounding of the upper groove edges without creating a level difference at or near the upper groove edge on the substrate surface.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: July 18, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Yasuko Yoshida, Norio Suzuki, Masayuki Kojima, Kota Funayama
  • Patent number: 6083808
    Abstract: A method for forming a trench isolation in a semiconductor device is provided in which a first heat treatment process is conducted on a thermal oxide layer previously formed in a trench at temperature range from about 1000.degree. C. to 1200.degree. C. for about 1 to 8 hours so as to remove defects in a semiconductor substrate and oxygen impurities within the semiconductor substrate resulting from a step of forming the trench in the semiconductor substrate. As a result, a subsequent second heat treatment process for densifying a trench filling material such as a CVD oxide layer can be performed at lower temperature of about 1000.degree. C. to 1050.degree. C., as compared with the temperature of the first annealing of the thermal oxide layer, thereby reducing distortions of the semiconductor substrate and reducing current leakages.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: July 4, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yu-Gyun Shin, Han-Sin Lee, Tai-su Park, Moon-Han Park
  • Patent number: 6080637
    Abstract: A process for creating an insulator filled, shallow trench, in a semiconductor substrate, in which the insulator layer in the shallow trench, is not exposed to procedures used to remove defining composite insulator layers, has been developed. The process features creating a lateral recess, in a thick silicon nitride layer, used as a component of a composite insulator layer, where the composite insulator layer is used for subsequent definition of the shallow trench, in the semiconductor substrate.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: June 27, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Kuo Ching Huang, Tse-Liang Ying, Wen-Chuan Chiang, Cheng-Yeh Shih
  • Patent number: 6069057
    Abstract: A method of fabricating a trench-isolation structure is provided. The fabricated trench-isolation structure in accordance with the present invention is formed on a semiconductor substrate. Sequentially, a buffer layer and a first isolating layer are formed to overlie the semiconductor substrate. After the first isolating layer is patterned to form an opening, the step of forming spacers on the sidewall of the opening follows. At the same time, within the range of the opening the portion of the buffer layer not covered by the spacers is removed to expose a portion of the semiconductor substrate. Then, the exposed semiconductor substrate is etched to form a trench. After a second isolating layer is formed on the peripherals of the trench, an isolation plug is filled in the trench.
    Type: Grant
    Filed: May 18, 1998
    Date of Patent: May 30, 2000
    Assignee: Powerchip Semiconductor Corp.
    Inventor: Shye-Lin Wu
  • Patent number: 6066544
    Abstract: A silicon-comprising layer is employed adjacent a trench during planarization of an oxide fill within the trench. An overhanging oxide sidewall is formed along a lateral edge of a trenched isolation region, the overhanging oxide sidewall overlapping an upper surface of a substrate immediately adjacent the trenched isolation region. An oxide plug is formed comprising a recessed portion below a substrate upper surface and an elevated portion above the substrate upper surface. The elevated portion comprising a ledge which extends over the substrate upper surface and has a top surface and a substantially vertical lateral edge side surface. Further, the plug may be within a substrate, the oxide plug having a recessed portion below a substrate upper surface and an elevated portion above the substrate upper surface, the elevated portion comprising a ledge extending over the substrate upper surface and abutting a polysilicon layer.
    Type: Grant
    Filed: July 8, 1998
    Date of Patent: May 23, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Pai-Hung Pan, Karl M. Robinson
  • Patent number: 6063689
    Abstract: A method for forming a shallow-trench isolation starts with forming a polysilicon layer, which has less stress, as the mask layer for patterning the trench on a provided substrate. An oxide layer is then formed to cover the polysilicon layer and fill the trench. The oxide layer is then removed by first performing a chemical mechanical polishing process to remove a portion of the oxide layer, wherein the remains of the oxide layer still covers the polysilicon layer and fills the trench. After that, an etching back process is performed to remove the oxide layer from the top of the polysilicon layer to form the oxide plug, which is used as an isolation.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: May 16, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Coming Chen, Water Lur
  • Patent number: 6057210
    Abstract: A silicon dioxide layer and a silicon nitride layer are formed on the wafer. Subsequently, a plurality of shallow trenches are generated in the wafer. A HDP-CVD oxide having protruding portions is refilled into the trenches and formed on the silicon nitride layer for isolation. A wet etch is performed to etch the HDP-CVD oxide layer such that the corners of the silicon nitride layer formed on the active area will be exposed. A cap silicon nitride layer is then conformally formed on the surface of the oxide layer. Then, a chemical mechanical polishing (CMP) process is used to remove the top of the cap silicon nitride layer, thereby exposing the residual protruding portions of the oxide layer. The residual protruding portions of the oxide layer are next removed. Then, the silicon nitride layer and the cap silicon nitride layer are both removed by conventional methods. Finally, the pad oxide is removed.
    Type: Grant
    Filed: April 21, 1998
    Date of Patent: May 2, 2000
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Fu-Liang Yang, Wei-Ray Lin, Ming-Hong Kuo
  • Patent number: 6051472
    Abstract: A semiconductor device of the present invention and using trench isolation includes contact holes. Spacers are formed on the shoulder portions of a device region exposed in the contact holes. To form the spacers, a silicon oxide film is formed and then etched by anisotropic etching such that the film does not fill up the contact holes. The anisotropic etching may be effected after oxidation. With this structure, it is possible to prevent junction leakage current from increasing.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: April 18, 2000
    Assignee: NEC Corporation
    Inventors: Hitoshi Abiko, Isami Sakai
  • Patent number: 6033970
    Abstract: A method for forming a device-isolating layer of a semiconductor device in which an APCVD oxide layer and an HDPCVD oxide layer are successively deposited to fill trenches. The method includes forming a thermal oxide layer on a semiconductor substrate including active regions and device-isolating regions, forming a nitride layer on the thermal oxide layer, selectively etching the nitride layer to be removed over the device-isolating regions and selectively etching the thermal oxide layer and the semiconductor substrate with the patterned nitride layer serving as a mask to form trenches. The method further includes forming another thermal oxide layer on the surface of the trenches, forming an APCVD oxide layer on the entire surface including the thermal oxide layer and the patterned nitride layer, forming and annealing an HDPCVD oxide layer on the entire surface of the APCVD oxide layer to fill the trenches. The HDPCVD oxide layer is then polished using a CMP process.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: March 7, 2000
    Assignee: LG Semicon Co., Ltd.
    Inventor: Jin Won Park
  • Patent number: 6033968
    Abstract: A method for forming a shallow trench isolation structure. A mask layer having an opening is formed over a substrate to pattern a shallow trench. A sloped spacer is formed on the sidewalls of the opening. The mask layer and the spacer are used as a hard mask, and a portion of the substrate is removed by anisotropic etching to form a shallow trench isolation structure. The sloped sidewalls of the shallow trench isolation structure and the substrate surface intersect at an obtuse angle. Therefore, the structure prevents stress and avoids leakage current.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: March 7, 2000
    Assignee: United Integrated Circuits Corp.
    Inventor: Kuo-Tung Sung
  • Patent number: 6027982
    Abstract: A method to form shallow trench isolation structures with improved isolation fill and surface planarity is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A thin oxide layer is deposited overlying the silicon nitride layer. An isolation trench is etched through the thin oxide layer, the nitride layer, and the pad oxide layer and into the substrate. The silicon nitride layer exposed within the trench is etched to form a lateral undercut leaving a projection of the thin oxide layer and exposing a portion of the underlying pad oxide layer. The thin oxide layer and the exposed portion of the pad oxide layer are etched away thereby exposing portions of the surface of the substrate. A liner oxide is grown on the exposed portions of the semiconductor substrate within the isolation trench and on the surface of the substrate.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: February 22, 2000
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Igor V. Peidous, Vladislav Y. Vassiliev, Chock H. Gan, Guang Ping Hua
  • Patent number: 6015726
    Abstract: A method of producing a semiconductor device having a bipolar transistor and a CMOS (Complementary Metal Oxide Semiconductor) transistor is disclosed. An epitaxial layer is formed on a semiconductor substrate having an n-type buried layer and a p-type buried layer thereinside. A field oxide film is formed on the epitaxial layer for delimiting active regions. An n-type and a p-type well region each is formed in a particular position. An insulation film playing the role of a gate oxide film at the same time is formed over the entire surface of the substrate. Subsequently, an emitter contact hole and a collector contact hole each extending to the epitaxial layer are formed at the same time. A polysilicon layer is formed over the entire surface of the substrate and then etched to form an emitter electrode and a gate electrode each having a preselected configuration. The resulting semiconductor device achieves a desirable current drive ability.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: January 18, 2000
    Assignee: NEC Corporation
    Inventor: Hiroshi Yoshida
  • Patent number: 6013559
    Abstract: A method of fabricating a trench isolation structure in a semiconductor devices. First, a mask layer is formed on a substrate and patterned. Then, a trench is formed in the substrate using the mask layer as a mask. An insulating layer is formed under the mask layer to fill the trench. The insulating layer is polished to expose a portion of the mask layer and an insulating plug is left in the trench. A RTP is performed to avoid mobile ions diffuse into the substrate. There are several operating conditions for the RTP. For example the operating temperature is ranged from about 600.degree. C. to about 1300.degree. C. The duration for performing the RTP is ranged from about 5 seconds to about 5 minutes. The operating gas can be selected from one of a group of N.sub.2, O.sub.2, or N.sub.2 O. Besides, before the RTP a cleaning step is performed using SC-1 or hydrogen fluoride (HF) solution as cleaning solution.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: January 11, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Lin Wu, Horng-Bor Lu
  • Patent number: 6010947
    Abstract: An end portion of a trench isolating region has a shape of steps so that a residual gate material can be easily removed and it is possible to prevent from conducting between gates. An oxide film 2, a first stopper 3 and a second stopper 4 are formed on a semiconductor substrate 1 (FIG. 1A). The materials of the first and second stoppers may be selected from materials having different oxidation rates, materials having different isotropic etching rates and the combinations thereof. Then, a resist is formed by patterning, and then, the anisotropic etching of the second stopper 4 of a silicon nitride layer, the first stopper 3 of a polycrystal silicon, the oxide film 2 and the semiconductor substance 1 is carried out (FIG. 1B). After peeling off the resist 7, oxidation is carried out by tens nm to form an oxide film 5 (FIG. 1C). At this time, since the first stopper 3 is made of a material which is easily oxidized, the oxide film 5 grows in a lateral direction to be formed therein. Then, a SiO.sub.
    Type: Grant
    Filed: July 11, 1997
    Date of Patent: January 4, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiyuki Kondo
  • Patent number: 6008108
    Abstract: A semiconductor fabrication method is provided for the fabrication of a shallow-trench isolation (STI) structure in integrated circuit. Conventionally, the insulating plug of the STI structure would be undesirably formed with microscratches in its top surface resulting from chemical-mechanical polishing (CMP) process, thus causing an undesired bridging effect thereacross when conductive layers are subsequently formed. This method can help solve this problem by forming a mending dielectric layer over the insulating plug of the STI structure to mend these microscratches. Since the mending dielectric layer is in a flowable state when it is being coated over the wafer, it can fill up all the microscratches in the top surface of the insulating plug, thereby mending the microscratches to prevent the bridging effect across the insulating plug that would other-wise occur in the case of the prior art.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: December 28, 1999
    Assignee: United Microelectronics Corp.
    Inventors: Chen-Nan Huang, Horng-Bor Lu
  • Patent number: 6004864
    Abstract: A method is described for forming trench isolation for integrated circuits on silicon wafers by selectively doping the trench regions by ion implantation and then etching these areas with a wet chemical etch. A dopant such as boron, is implanted in a sequence of energies and doses to provide a desired trench profile of heavily doped silicon. The implanted silicon etches far more rapidly than the surrounding silicon and is readily etched out forming a trench. The concentration of dopant diminishes rapidly in the periphery of the implanted region. As the etch front approaches the periphery, the silicon etch rate, likewise diminishes and the etch can be quenched to leave a uniform surface layer of enhanced boron concentration which lines the resultant trench to form an effective channel stop. Wet etched trenches provide advantages over trenches formed by RIE including smooth rounded trench profiles which reduce stress. In addition, trenches having widths below 0.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: December 21, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ji-Chung Huang, Han-Liang Tseng, Chia-Hsiang Chen, Kuo-Sheng Chuang
  • Patent number: 5998280
    Abstract: A trench is etched in a silicon substrate covered with an oxide/nitride stack and a field oxide layer is then grown through oxidation of the silicon in the substrate such that the trench is partly filled. There is reduced oxide encroachment into the active areas under the nitride layer because of the partial field oxide growth. Double oxide layers are deposited over the surface of the field oxide layer and the oxide/nitride stack such that the oxide layers fill the remainder of the trench and produce a nearly planar topology. The double oxide layers are then etched back to the nitride layer through chemical mechanical polishing, leaving the field isolation region. After stripping the oxide/nitride stack, a gate oxide layer is grown. A minimal amount of oxide is required to fill the trench because the trench is already almost filled with the field oxide layer and because of the shallow depth of the trench. Consequently, the etch back step causes minimal dishing.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: December 7, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Albert Bergemont, Alexander H. Owens
  • Patent number: 5994200
    Abstract: A semiconductor device isolation structure includes a trench formed in a substrate vertically from the major surface of the substrate, a trench plug for filling the trench, and a buried insulation region formed under the trench adjacent thereto, and a method of the same includes the steps of forming a trench in a substrate and vertically from the major surface of the substrate, selectively implanting oxide ions under the trench of the substrate, and forming a trench plug so as to fill the trench.
    Type: Grant
    Filed: July 22, 1997
    Date of Patent: November 30, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventor: Young-Gwan Kim
  • Patent number: 5994201
    Abstract: A method for manufacturing shallow trench isolation regions according to the invention uses a first stop layer and a second stop layer as two polishing stop layers, or a polishing stop layer and an etching stop layer, respectively. By performing chemical mechanical polishing twice, or performing chemical mechanical polishing one time and then etch back, the influence on subsequently formed shallow trench isolation regions caused by different sizes and densities thereof can be greatly alleviated.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: November 30, 1999
    Assignee: United Microelectronics Corp.
    Inventor: Tzung-Han Lee
  • Patent number: 5985735
    Abstract: A method of forming a trench isolation structure in a semiconductor substrate. After etching a trench into the semiconductor substrate, an oxide layer is formed within the trench. The surface of this oxide layer is subjected to a nitrogen plasma. Subsequently, another oxide layer is deposited over the nitrogen-rich surface of the first oxide layer. Deposition of this second oxide layer is accomplished by a chemical vapor deposition (CVD) process primarily using a reactant gas other than ozone.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: November 16, 1999
    Assignee: Intel Corporation
    Inventors: Peter K. Moon, David T. Krick, Kerry L. Spurgin
  • Patent number: 5981356
    Abstract: A method for forming trench isolation with spacers on the corners where the silicon and oxide intercept. A cavity is formed in silicon with a mask. Prior to completely removing the mask, the mask is further etched to enlarge the upper portion of the cavity. The cavity is filled with oxide, which is subsequently etched to produce a dome-shaped cap, protective of sharp silicon corners that would otherwise upset electrical characteristics of transistors.
    Type: Grant
    Filed: July 28, 1997
    Date of Patent: November 9, 1999
    Assignee: Integrated Device Technology, Inc.
    Inventors: Cheng-Chen Calvin Hsueh, Chu-Tsao Yen
  • Patent number: 5981357
    Abstract: An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches.
    Type: Grant
    Filed: June 16, 1997
    Date of Patent: November 9, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Fred N. Hause, Robert Dawson, Charles E. May, Mark I. Gardner, Kuang-Yeh Chang
  • Patent number: 5976948
    Abstract: A method for producing a semiconductor device using an improved trench isolation technique includes, first, forming a masking layer over a device layer. A first portion of the masking layer and an underlying portion of the device layer are removed to form at least one trench. A second portion of the masking layer is then selectively removed from a region adjacent the trench and above the device layer. A dielectric layer is formed in the trench so that the dielectric layer at least partially fills the trench and the region adjacent to the trench and above the device layer. The dielectric layer includes a trench cap above the trench isolation region and the device layer. The trench cap extends laterally and longitudinally above and beyond the trench isolation region, in accordance with the second portion of the masking layer which was removed.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: November 2, 1999
    Assignee: Advanced Micro Devices
    Inventors: Thomas Werner, Robert Dawson
  • Patent number: 5976951
    Abstract: A method for forming an isolating trench in a substrate is disclosed herein. The forgoing method includes the following steps. First, form a first dielectric layer and a second dielectric layer on the substrate subsequently, and then develop a photoresist pattern on the second dielectric layer. Then, etch the substrate, the first dielectric layer and the second dielectric layer to form a trench in the substrate. Next, form a first silicon dioxide layer in the trench followed by removing the photoresist pattern. The next step is to form a third dielectric layer on the second dielectric layer and the first silicon dioxide layer. Subsequently, fill the trench with silicon dioxide to from an oxide trench; then remove the second dielectric layer, a first portion of the third dielectric layer and a portion of the oxide trench with a chemical mechanical polishing (CMP) and a first solution.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: November 2, 1999
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Tai Huang, Chih-Hsiang Hsiao, Chao-Yen Chen
  • Patent number: 5960299
    Abstract: A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure in an integrated circuit, which can prevent the occurrence of microscratches in the oxide plugs of the STI structure, thus further preventing the occurrence of a bridging effect and short-circuits between the circuit components that are intended to be electrically isolated by the STI structure. This method is characterized by the use of a laser annealing process to remove the microscratches that formed on the top surface of the oxide plugs during the chemical-mechanical polishing (CMP) process used to remove the upper part of the oxide layer to form the oxide plugs This method can therefore prevent the occurrence of a bridging effect and short-circuits due to the forming of the microscratches that would otherwise occur in the prior art.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: September 28, 1999
    Assignee: United Microelectronics Corp.
    Inventors: Tri-Rung Yew, Water Lur, Shih-Wei Sun
  • Patent number: 5960298
    Abstract: A method of fabricating a semiconductor device having a trench isolation structure includes forming an isolation region including a trench and a trench plug for filling the trench so as to define active regions on a substrate, a part of the trench plug projecting upward from the surface of the substrate, forming sidewall spacers from an oxidative material on the sidewalls of the projecting portion of the trench plug, and oxidating the surface of the active region of the substrate and the sidewall spacers so as to form a gate insulating layer extending to the upper part of the active region of the substrate and the side surfaces of the trench plug.
    Type: Grant
    Filed: July 11, 1997
    Date of Patent: September 28, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventor: Young-Gwan Kim
  • Patent number: 5950094
    Abstract: The present invention provides a method of fabricating fully dielectric isolated silicon (FDIS) by anodizing a buried doped silicon layer through trenches formed between active areas to form a porous silicon layer; oxidizing the porous silicon layer through the trenches to form a buried oxide layer; and by depositing a dielectric in the trenches. The process begins by forming a buried doped layer in a silicon substrate defining a silicon top layer over the conductive buried doped layer. The silicon top layer and the buried doped layer are patterned to form trenches that extend into but not through the buried doped layer. The trenches define isolated silicon regions. The buried doped layer is anodized to form a porous silicon layer. The porous silicon layer is converted into a buried oxide layer by oxidation. The oxidation step also forms a liner oxide layer on the tops and sidewalls of the isolated silicon regions.
    Type: Grant
    Filed: February 18, 1999
    Date of Patent: September 7, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chi Lin, Hui-ju Yu, Yen-Ming Chen, Hui-Hua Chang
  • Patent number: 5945352
    Abstract: The present invention provides a method for fabricating shallow isolation trenches with sloped walls in semiconductor wafers. The method uses a conformal polysilicon layer to form an etch barrier over trench regions in a semiconductor substrate. This etch barrier has areas of varying thickness. The thickest areas of the etch barrier are located on the edges of trench structures and slow the etch process in the underlying substrate. The thinner regions of the etch barrier do not impede the etch process to as great an extent. This etch rate differential causes a sloped trench wall profile. The isolation trenches are completed by filling the surface with dielectric materials then planarizing.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: August 31, 1999
    Assignee: Advanced Micro Devices
    Inventors: Hung-Sheng Chen, Mark S. Chang
  • Patent number: 5943590
    Abstract: A method for improving the planarity of a semiconductor chip using chemical-mechanical polishing during a shallow trench isolation process is described. Specifically, an polish-stop layer, preferably of silicon nitride, is formed over a semiconductor wafer (or optionally formed over a pad oxide layer formed on the wafer). A cap layer, preferably of polysilicon, is then formed over the polish-stop layer. The active regions of the chip are defined, preferably using a photoresist mask by photolithography. The wafer, polish-stop and cap layers are then etched, between the active regions, to form shallow trenches. A lining dielectric layer, preferably an oxide, is formed over the etched and non-etched regions to fill the shallow trenches for isolation purposes. The dielectric layer has an etching rate at least three times greater than the etching rate of cap layer. When polysilicon is selected as the cap layer and oxide is selected as the dielectric layer, the selectivity rate is greater than ten.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: August 24, 1999
    Assignee: Winbond Electronics Corp.
    Inventors: Jyh-Lih Wang, Yung-Shun Chen
  • Patent number: 5940717
    Abstract: A method for reducing hot carrier reliability problems within an integrated circuit device. The method includes forming a shallow trench isolation structure incorporated with the device by filling a trench with a photoresist plug and removing a portion of the photoresist plug to a level below the depth of a channel also incorporated with the device. A nitride liner disposed within the trench under the photoresist plug is then recessed to a level substantially equal to the level of the photoresist material, which is then removed. The method further includes the deposition of oxide fill within the trench, thereby encapsulating the recessed nitride liner.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: August 17, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventors: Rajesh Rengarajan, Venkatachalam C. Jaiprakash
  • Patent number: 5937309
    Abstract: A method for fabricating a shallow trench isolation (STI) structure in a semiconductor substrate. A stop layer is formed on the substrate and a first sacrificial layer is formed on the stop layer. The first sacrificial layer and the stop layer are defined to form an opening on the substrate. A conformal second sacrificial layer with rounded corners is formed on the substrate. The second sacrificial layer, the first sacrificial layer, and a portion of the substrate are anisotropically removed to form a trench in the substrate using the stop layer as a removal stop layer. The substrate is over removed using the stop layer as a mask layer so that spacers of the second sacrificial layer are remained on the substrate to cover portions of sidewalls of the stop layer.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: August 10, 1999
    Assignee: United Semiconductor Corp.
    Inventor: Shu-Ya Chuang
  • Patent number: 5933749
    Abstract: A method for removing the top corner of the trench is disclosed. After the formation of an oxide layer and then a nitride layer over a substrate, a portion of the nitride layer, the oxide layer and the substrate are removed to form a trench. A mask is next formed on the nitride layer, wherein the opening of the mask is larger than the corresponding trench. A dry etching is performed to etch the exposed nitride layer and the substrate, using said mask. After removing the mask and the nitride layer, a liner oxide layer is then formed. The dry etching process removes the top corner to form a grading corner which consequently avoids charge accumulation and point discharging.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: August 3, 1999
    Assignee: United Microelectronics Corp.
    Inventor: Tzung-Han Lee
  • Patent number: 5923993
    Abstract: A fabrication process for manufacturing integrated circuits with isolation trenches. The process includes the use of two nitride layers and an oxide layer formed by high density plasma oxidation, to provide isolation trenches free of dishing. The isolated regions are useable for fabrication microelectronic circuit devices, such as MOS transistors or flash memory devices.
    Type: Grant
    Filed: December 17, 1997
    Date of Patent: July 13, 1999
    Assignee: Advanced Micro Devices
    Inventor: Kashmir S. Sahota
  • Patent number: 5920787
    Abstract: A semiconductor device isolating structure and method for forming such a structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall extending to the bottom surface of the trench, and a second sidewall extending to the bottom surface of the trench. Furthermore, the trench of the present invention also has a first field oxide region formed proximate to the interface of the first sidewall and the top surface of the semiconductor substrate, and a second field oxide region formed proximate to the interface of the second sidewall and the top surface of the semiconductor substrate.
    Type: Grant
    Filed: January 15, 1997
    Date of Patent: July 6, 1999
    Assignee: VLSI Technology, Inc.
    Inventors: Jake Haskell, Olivier Laparra, Jie Zheng
  • Patent number: 5915192
    Abstract: A method of forming a trench isolation is disclosed. The initial step includes forming a first dielectric layer on a substrate of a transistor followed by a second dielectric layer formed on the first dielectric layer. Next, the substrate, the first dielectric layer and the second dielectric layer is patterned and etched to form a trench in the substrate, the first dielectric layer and the second dielectric layer. Next, a third dielectric layer is formed on the surface of the side wall of the trench followed by isotropically etching the bottom of the trench. Finally, a fourth dielectric layer on the surface of the trench is formed and the trench is filled with a dielectric material.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: June 22, 1999
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jhon-Jhy Liaw, Jin-Yuan Lee
  • Patent number: 5910018
    Abstract: The present invention provides a method to achieve shallow trench isolation (STI) on the quarter-micron scale. A thin oxide layer, a thick nitride layer, a thick oxide layer and a thin nitride layer are formed sequentially on a silicon substrate. A photo-resist (PR) layer is then applied as a mask for the isolation regions. The top nitride layer, the top oxide layer and the bottom nitride layer are then etched away from the areas not covered by the PR layer. The PR layer is then removed. An isotropic oxide etch is then applied to create a recess along the bottom oxide layer. A thin oxide layer is then grown on the exposed silicon surface. A thin nitride layer is then deposited to fill the recess in the bottom oxide layer. An anisotropic nitride etch is applied to form a nitride spacer along the isolation edge. A thick oxide layer is then grown and removed. This step is repeated as necessary to obtain the desired trench slope.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: June 8, 1999
    Assignee: Winbond Electronics Corporation
    Inventor: Wen-Yueh Jang
  • Patent number: 5911110
    Abstract: A thin silicon dioxide layer and a silicon nitride layer are respectively formed on a wafer. A plurality of shallow trenches are formed in the wafer. A trench filling layer is successively refilled into the trenches for isolation. A reverse tone mask with a dummy pattern mask is patterned on top of the trench filling material. An etching is performed to etch the trench filling material using the reverse tone mask and the dummy pattern mask as etching masks. The reverse tone mask and the dummy pattern mask are then stripped away. A chemical mechanical polishing (CMP) technology is used to remove the trench filling layer to the surface of the silicon nitride layer for planarization.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: June 8, 1999
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chen-Hua Yu
  • Patent number: 5909628
    Abstract: A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: June 1, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, Theodore W. Houston, Ih-Chin Chen, Agerico L. Esquirel, Somnath Nag, Iqbal Ali, Keith A. Joyner, Yin Hu, Jeffrey Alan McKee, Peter Stewart McAnally
  • Patent number: 5904539
    Abstract: An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches.
    Type: Grant
    Filed: March 21, 1996
    Date of Patent: May 18, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Fred N. Hause, Robert Dawson, Charles E. May, Mark I. Gardner, Kuang-Yeh Chang
  • Patent number: 5904541
    Abstract: A semiconductor device having a shallow trench isolation structure, where the upper part of the trench is broader than the lower part of it, comprises an insulating layer on the sidewalls of the upper part of the trench, another insulating layer buried in the trench for isolating semiconductor devices and low-concentration doped regions near the upper part of the trench and high-concentration doped regions near the lower part of the trench. Therefore, the leakage current is prevented due to the sufficient amount of the ions in the high-concentration doped regions near the lower part of the trench and the narrow width effect is minimized owing to the insulating layer on the sidewalls of the upper part of the trench.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: May 18, 1999
    Assignee: Hyundai Electronics Industries Co., LTD.
    Inventors: Kwang Myoung Rho, Seong Min Hwang