Abstract: A method for forming a microelectronic structure includes the steps of forming a trench in a substrate and forming an insulating layer which fills the trench and covers the substrate. Ions can be implanted into the insulating layer which decrease an etch rate of the insulating layer, and portions of the insulating layer on the substrate can be removed while maintaining the insulating layer in the trench. In addition, the step of forming the insulating layer can include forming an undoped oxide layer on the substrate and forming a doped oxide layer on the undoped oxide layer wherein a void is formed in the doped oxide layer. The void can thus be reduced by reflowing the doped oxide layer.

Abstract: A manufacturing method of a semiconductor integrated circuit utilizing a trench isolated region to control the occurrence of parasitic transistors without narrowing the element region by forming first and second openings 4A, 4B on a silicon substrate for the purpose of element isolation, forming an amorphous silicon film thereon, then leaving the amorphous silicon film behind only a surface of a side wall of the opening by performing anisotropy etching. After oxidizing the surface of the amorphous silicon film and inside base, the opening is filled with a silicon oxide film.

Abstract: A trench 13 is formed to isolate a first region 11a and a second region 11b where elements of a semiconductor substrate 11 such as a silicon substrate are formed, and a lamination layer of a first silicon oxide layer 14 having a silicon excess stoichiometry (SiO.sub.x ; 2<x) and a second silicon oxide layer 15 (SiO.sub.2) having an equilibrium composition is filled in the trench 13. The second silicon oxide layer is hydrated. In addition, by heating the semiconductor substrate 11, the first silicon oxide layer 14 is oxidized into the second silicon oxide layer 15 (SiO.sub.2) having an equilibrium composition. At this time, the first silicon oxide layer 14 has its volume expanded while it is oxidized into the second silicon oxide layer 15 having an equilibrium composition, while the second silicon oxide layer 15 is contracted due to dehydration by the heating treatment and removal of a defective lattice.

Abstract: A method for forming a shallow trench isolation structure comprising the steps of sequentially forming a pad oxide layer and a mask layer over a substrate, then patterning the mask layer and the pad oxide layer. Next, an opening is formed in the mask layer, wherein the sidewall of the opening in the mask layer forms a sharp angle with the substrate layer below. Thereafter, the substrate is etched from the opening down to form a trench. In a subsequent step, insulating material is deposited into the trench forming an insulating layer rising to a level higher than the mask layer, and accompanying by the formation of a protuberance at the side of the insulating layer. Subsequently, the mask layer is removed, and then portions of the pad oxide layer is removed to form a spacer on the upper side of the insulating layer. Finally, the pad oxide layer above the substrate is removed to complete the formation of the shallow trench isolation structure.

Abstract: An InP-based opto-electronic integrated circuit including an active layer having one or more quantum wells (36, 38). According to the invention, a barrier layer (34) of AlGaInAs is formed, preferably between the quantum wells and the substrate (30) to prevent the migration of species from the substrate and lower InP layers that tend to shift the emission wavelengths of the quantum wells to shorter wavelengths, i.e., a blue shift. The barrier layer can be patterned so that some areas of the quantum wells exhibit blue shifting to a shorter wavelength while other areas retain their longer wavelength during annealing.

Abstract: In the case where ohmic electrodes are formed on a semiconductor wafer, first of all, an insulating layer is formed on the semiconductor wafer, then a resist layer is formed on the insulating layer. Next, apertures for forming electrodes are formed in first regions of the resist layer corresponding to regions where the electrodes are formed, while dummy apertures are also formed in a second region of the resist layer in a rest part other than the first regions. Thereafter, the insulating layer is etched using the resist layer as a mask. With the resist layer remaining, electrode material is accumulated on the surface of the semiconductor wafer, and thereafter, the resist layer is removed. As a result, electrodes with desirable ohmic characteristics are stably formed.

Abstract: A fabrication method for a horizontal direction semiconductor PN junction array which can be achieved when an epitaxial layer is grown by a metalorganic chemical vapor deposition (MOCVD method) by introducing (or doping) a small amount of CCl.sub.4 or CBr.sub.4 gas, includes forming a recess on an N type GaAs substrate by using a non-planar growth, performing a growth method of a P type epitaxial layer on the N type GaAs substrate by a metalorganic chemical vapor deposition method, and forming a horizontal direction PN junction array of P-GaAs/N-GaAs or P-AlGaAs/N-GaAs by introducing a gas comprising CCl.sub.4 or CBr.sub.4 .

Abstract: A process applicable to the production of monocrystalline films improves on the Smart-Cut.RTM. process by using an etch stop layer in conjunction with the Smart-Cut.RTM. process. Because of the etch stop layer, no chemical-mechanical polishing (CMP) is required after fabrication. Thus, the thickness and smoothness of the device layer in the fabricated silicon on insulator (SOI) substrate is determined by the uniformity and smoothness of the deposited layers and wet etch selectivity, as opposed to the CMP parameters. Therefore, the smoothness and uniformity of the device layer are improved.

Abstract: The present invention provides a method of manufacturing a semiconductor device to prevent the generation of crystalline defects due to shorting between interconnects resulting from etch residue as a result of the generation of vertical bird's beaks on top of the trench during field oxidation layer formation. The method includes forming an epitaxial layer over a semiconductor substrate, depositing a first SiO.sub.2 layer, an SiN layer and a second SiO.sub.2 layer in that order upon said epitaxial layer and forming a trench from the second SiO.sub.2 layer extending into the semiconductor substrate. A third SiO.sub.2 layer is formed coating said trench with a region of said third Si0.sub.2 layer removed adjacent to said first SiO.sub.2 layer to expose a portion of said epitaxial layer within said trench. The trench is then filled with a first polysilicon layer to coat the third SiO.sub.2 layer and the first SiO.sub.2 layer followed by removal of the second SiO.sub.

Abstract: A method of fabricating an integrated circuit with trenches, without parasitic edge transistors, for isolating FET transistors from each other without degrading the FETs operating characteristics by junction leakage, breakdown or shorting, when a metal silicide is used in the source/drain regions. A silicon wafer is formed with sidewalls on the sides of each area in which a groove is to be etched. In etching the silicon, the sidewalls define the lateral dimension of the trenches. After the trenches are etched, the sidewalls are removed and the trenched are filled with an insulating material using a high density plasma reactor, such as an electron cyclotron resonance (ECR) plasma reactor. This type of reactor simultaneously deposits and sputter etches so that silicon edges at the base of the now removed sidewalls become tapered at an angle of about 45.degree. during deposition.

Abstract: According to the present invention, there is disclosed a method for planarizing TEOS SiO.sub.2 filled shallow isolation trenches according to a planarization main step which is comprised of three processing steps. The starting structure (10) consists of a silicon substrate (11) coated by a patterned Si.sub.3 N.sub.4 layer (12) which delineates shallow trenches (20A, 20B) with a conformal layer (22) of TEOS SiO.sub.2 formed thereon. A planarizing medium, typically two superimposed photoresist layers (24.25) is formed onto the resulting structure to provide a substantially planar surface. At this stage of the fabrication, the structure is standard. Now, this planar surface is translated by a non selective two-steps plasma etching in the TEOS SiO.sub.2 layer (22). Next, should some photoresist material remain onto the structure it would be removed. Finally, a highly selective TEOS SiO.sub.2 /Si.sub.3 N.sub.4 RIE etching step is performed which stops on the Si.sub.3 N.sub.4 layer. The preferred chemistry is C.

Abstract: A semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass includes, a) forming a field isolation mass within a semiconductor substrate by a trench and refill technique, and a substrate masking layer over the substrate adjacent the field isolation mass, the field isolation mass being capped with an etch stop cap, the field isolation mass having a sidewall covered by the masking layer; b) removing the substrate masking layer away from the isolation mass to expose at least a portion of the isolation mass sidewall; c) forming an etch stop cover over the exposed isolation mass sidewall; d) forming an insulating layer over the isolation mass and substrate area adjacent the isolation mass; and e) etching a contact opening through the insulating layer to adjacent the isolation mass selectively relative to the isolation mass etch stop cap and cover. A semiconductor structure is also described.

Abstract: A method for forming shallow trench isolation (STI) (100) begins by forming an oxidizable layer (106) preferably made of polysilicon. An opening is patterned and etched through this layer (106) to define and form the trench isolation region (108). Silicon sidewalls of the trench (108) and the polysilicon layer (106) are then exposed to an oxidizing ambient to form a thermal oxide trench liner (107a) and an erosion-protection polysilicon-oxide layer (107b). A trench fill material (110a) is then deposited and chemically mechanically polished (CMP) utilizing the polysilicon layer (106) as a polish stop. The final polished trench fill plug comprises an ozone TEOS bulk material (110c) and an annular peripheral upper erosion-protection portion formed of the polysilicon-oxide (107d). The annular polysilicon-oxide protection regions (107d) either reduce or entirely eliminate adverse sidewall parasitic erosion which occurs in conventional trench technology when processing active areas (124).

Abstract: A method for forming an isolation region in a semiconductor substrate is disclosed. The present invention includes forming an insulating layer on the semiconductor substrate, and then forming a dielectric layer on the insulating layer. After patterning to etch portions of the dielectric layer, the insulating layer and the semiconductor substrate are etched using the patterned dielectric layer as a mask, thereby forming a trench in the semiconductor substrate. Next, a first silicon oxide layer is formed over the semiconductor substrate, and the first silicon oxide layer is then anisotropically etched to form a spacer on the sidewalls of the trench. Thereafter, the semiconductor substrate is thermally oxidized to form a field oxide region over the semiconductor substrate, and a second silicon oxide layer is then formed over the field oxide region. Finally, the second silicon oxide layer is etched back until surface of the dielectric layer is exposed.

Abstract: A silicon-comprising layer is employed adjacent a trench during planarization of an oxide fill within the trench. An overhanging oxide sidewall is formed along a lateral edge of a trenched isolation region, the overhanging oxide sidewall overlapping an upper surface of a substrate immediately adjacent the trenched isolation region. An oxide plug is formed comprising a recessed portion below a substrate upper surface and an elevated portion above the substrate upper surface. The elevated portion comprising a ledge which extends over the substrate upper surface and has a top surface and a substantially vertical lateral edge side surface. Further, the plug may be within a substrate, the oxide plug having a recessed portion below a substrate upper surface and an elevated portion above the substrate upper surface, the elevated portion comprising a ledge extending over the substrate upper surface and abutting a polysilicon layer.

Abstract: A method, using multi-trench formation techniques, to define the respective depths of trenches having different widths. The method includes forming a buffer oxide layer and a polishing stop layer, in sequence, above a semiconductor substrate. Then, the buffer oxide layer, the polishing stop layer and the semiconductor substrate are defined to form at least one narrow trench. Thereafter, the buffer oxide layer, the polishing stop layer and the semiconductor substrate are again defined to form at least one wide trench whose depth is less than that of the narrow trench. Alternatively, the wide trench may be etch-defined first, followed by the narrow trench. However, in both cases the depth of the wide trench will be less than that of the narrow trench. Subsequently, an oxide layer is formed, which fills the narrow and wide trenches. Next, a portion of the oxide layer and a portion of the polishing stop layer are removed to form a planarized surface.

Abstract: An improved method for implementing shallow trench isolation in integrated circuits is described. The method begins with the formation of trenches, through patterning and etching. These trenches are then filled with a conformal layer of silicon oxide. This is followed by overcoating with a layer of a hard material such as silicon nitride or boron nitride. Next, chemical-mechanical polishing is used to remove the hard layer everywhere except where it has filled the depressions that overlie the trenches. Then, a non-selective etch is used to remove the remaining hard layer material as well as some of the silicon oxide, so that a planar surface is maintained. Finally, chemical-mechanical polishing is used a second time to remove excess silicon oxide from above the trenches' surface.

Abstract: A semiconductor device isolating structure and method for forming such a structure. In one embodiment, an opening is formed through a mask layer overlying a semiconductor substrate. A trench of a desired depth is then etched into the semiconductor substrate at the area of the semiconductor substrate underlying the opening in the mask layer. The trench is then filled with a dielectric material. After an oxide planarizing process, the present invention exposes the dielectric-filled trench to an oxidizing environment. By filling the trench with dielectric material prior to the oxidization step, the present invention selectively oxidizes the semiconductor substrate at corners formed by the intersection of the sidewalls of the trench and the top surface of the semiconductor substrate. In so doing, the present invention forms smoothly rounded semiconductor substrate corners under the mask layer.

Abstract: A method of forming and planarizing a deep isolation trench in a silicon-on-insulator (SOI) structure begins with a base semiconductor substrate, a buried insulator layer formed on the base semiconductor substrate, and an active silicon layer formed on the buried insulator layer. First, an ONO layer is formed on the active silicon layer. The ONO layer includes a layer of field oxide, a first layer of silicon nitride and a layer of deposited hardmask oxide. A trench having sidewalls that extend to the buried oxide layer is formed. A layer of trench lining oxide is then formed on the exposed sidewalls of the trench. Then, a second layer of silicon nitride is conformally formed on the substrate.

Abstract: A semiconductor laser diode apparatus has a substrate of a first conduction type, a first clad layer of the first conduction type which is formed on the substrate, a current block layer which is formed on the first clad layer, a V groove stripe which is formed in a vertical direction so that a tip of the V groove can arrive at the first clad layer in depth, an active layer which is formed on the first clad layer and the current block layer along the V groove stripe without a low resistance layer, a second clad layer of a second conduction type which is formed on the active layer, a contact layer of the second conduction type which is formed on the second clad layer, a first electrode which is formed on a surface of the substrate which is reverse side of a surface on which the first clad layer is formed and a second electrode which is formed oil a surface of the contact layer. Therefore a low threshold current level can be achieved.

Abstract: A method for forming insulator filled, shallow trench isolation regions, with rounded corners, has been developed. The process features the use of a polymer coated opening, in an insulator layer, used as a mask to define the shallow trench region in silicon. After completion of the shallow trench formation the polymer spacers are removed, exposing a region of unetched semiconductor, that had been protected by the polymer spacers, during the shallow trench dry etching procedure. The sharp corner, at the intersection between the shallow trench and the unetched region of semiconductor, is then converted to a rounded corner, via thermal oxidation of exposed silicon surfaces. The polymer spacers also eliminate the top corner wraparound.

Abstract: A method is achieved for making improved shallow trench isolation (STI) regions surrounding and electrically isolating device areas on a substrate using dielectric studs, spin-on-glass (SOG), and an isotropic wet etchback. The method consists of forming trenches in a silicon substrate using a pad oxide and silicon nitride mask. A thermal oxide is grown in the silicon trenches and a CVD silicon oxide is deposited and chemical/mechanically polished back to the silicon nitride masking layer to form dielectric studs (or plugs) in the silicon trenches that extend above the silicon substrate surface. The silicon nitride is removed in hot phosphoric acid, and a thin SOG is deposited to form disposable sidewall spacers on the raised studs. The thin SOG and the pad oxide are wet etched in HF acid to the device areas while isotropically etching back the disposable SOG sidewall spacers and dielectric studs to form shallow trench isolation regions having a raised convex surface.

Abstract: An improved method for fabricating a heterojunction bipolar transistor which includes the steps of forming a buried collector, a collector thin film, and a collector sinker on a semiconductor substrate in order, forming a first silicon oxide film, a base electrode polysilicon layer, a nitride film, and an oxidation film on a resulting substrate exposing the first silicon oxidation film, forming a spacer insulation film at the lateral side of the exposed region, and defining an activation region, exposing the collector thin film of the activation region using a mask, and forming an auxiliary lateral film for an isolation of the device, forming a selective collector region by ion-implantating a dopant to the activation region which is limited by the auxiliary lateral film, removing the auxiliary lateral film, etching the exposed portion in an anisotropic etching method, and forming a shallow trench for a device isolation, forming a polysilicon lateral film to have a height which is the same as the height of the

Abstract: A new method is disclosed to form a shallow trench isolation with a ozone-TEOS as a gapfilling material. The formation of the shallow trench isolation described herein includes a pad layer, a silicon nitride layer formed on a semiconductor substrate. A thermal oxide layer is subsequently formed on the silicon nitride layer. Then a shallow trench is created via photolithography and dry etching steps to etch the thermal oxide layer, the silicon nitride layer and the pad layer. After photoresist is removed, an ozone-TEOS layer is form in the shallow trench and on the top of the thermal oxide layer for the purpose of isolation. A CMP is perform to make the surface of the substrate with a planar surface. Then, a thermal annealing is used for densification of the ozone-TEOS layer and for forming a lining oxide to provide better isolation.

Abstract: A BiCMOS manufacturing process for fabricating an emitter of a bipolar transistor includes the steps of forming footings on a silicon substrate for prospectively bearing edges of the emitter, forming a polysilicon emitter having a medial portion overlying the silicon substrate and lateral edges on the footings, removing the footings leaving notches at the lateral edges of the polysilicon emitter and refilling the notches with a thin polysilicon film. The bipolar transistor in a BiCMOS integrated circuit resulting from this process includes a silicon semiconductor substrate having a substantially flat surface, a field oxide film laterally bounding the silicon semiconductor substrate and a polysilicon emitter abutting the flat surface of the silicon semiconductor substrate.

Abstract: A method for isolation between semiconductor devices includes the steps of: forming sequentially a first oxide film and silicon nitride layer on a silicon substrate; forming a first photoresist pattern on the nitride layer where field oxide is not to be formed; etching the exposed nitride to predetermined depth; stripping the first photoresist film; oxidizing the resultant wafer of the above step until a second oxide grows on the etched silicon substrate and extends itself from the region of the patterned nitride and first oxide layer to a predetermined outward distance; forming a second photoresist film at the portions excepting the surface of the nitride layer; etching the nitride layer, the first oxide layer and a portion of second oxide positioned at the vertical downward direction under the first oxide; stripping the second photoresist film, growing epitaxially the exposed portion of the etched silicon substrate; depositing an insulating layer on the resultant structure of the above step and polishing th

Abstract: Warpage in a bonded wafer is limited by maintenance of a stress compensation layer on the backside of the bonded wafer during device fabrication processing. One embodiment applies a sacrificial polysilicon layer over a stress compensation silicon dioxide layer for bonded silicon wafers. The fabrication processing consumes the polysilicon layer but not the stress compensation silicon dioxide.

Abstract: A method of fabricating a laser diode with reverse mesa structure has the following processes. A buffer layer of a first conductivity type, an active layer, a clad layer of a second conductivity type and a high-concentration contact layer of the second conductivity type are sequentially formed on a compound semiconductor substrate of the first conductivity type. Predetermined portions of the contact layer and of the clad layer are etched to form a reverse mesa structure. A passivation layer is formed on the overall substrate and the passivation existing on the reverse mesa structure is removed to expose the contact layer. A metal layer is formed on the exposed contact layer to contact therewith and a conductive metal layer is uniformly formed on the metal layer and the passivation layer. A pad metal layer is formed on the conductive metal layer to fill the etched portions of either side of the reverse mesa structure.

Abstract: The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by reducing the mobility of carriers between the devices. The preferred embodiment uses an implant formed beneath trench isolation between n-channel and p-channel devices. This implant preferably comprises relatively large/heavy elements implanted into the wafer beneath the trench isolation. The implant elements reduce the mobility of the charge carriers. This increases the latch-up holding voltage and thus reduces the likelihood of latch-up. The implants can be formed without the need for additional photolithography masks.

Abstract: A process for stripping thin layers of oxide such as sacrificial pad oxide employs etching chemistry that widens cracks to remove shallow cracks and limit the widening of deep cracks, thereby producing a final oxide surface on thick layers of oxide that is less rough than prior art methods and enabling the fabrication of oxide-filled trenches that have geometries and/or surface smoothness that were previously impossible.

Abstract: A method for filling a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then oxidized thermally the silicon substrate to form within the trench a thermal silicon oxide trench liner layer. There is then formed upon the thermal silicon oxide trench liner layer a conformal silicon oxide intermediate layer formed through a plasma enhanced chemical vapor deposition (PECVD) method employing a silane silicon source material. Finally, there is then formed upon the conformal silicon oxide intermediate layer a gap filling silicon oxide trench fill layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material.

Abstract: The present invention discloses an isolation method in a semiconductor device.

Abstract: The present invention provides a method of manufacturing a sacrificial self aligned sub-atmospheric chemical vapor deposition (SACVD) O.sub.3 TEOS layer 50 70 over a trench oxide 40 to protect the trench oxide from excessive subsequent etch steps. The SACVD O.sub.3 TEOS layer has a higher deposition rate over the trench oxide layer 40 than over the surrounding non-trench thermally grown pad oxides. The trench oxide is preferably formed using a process of PECVD, LPTEOS, or O.sub.3 -TEOS. The invention provides two preferred embodiments: (1) a first self aligned sacrificial O.sub.3 TEOS oxide layer 50 deposited before the pad oxide etch and (2) a second self aligned sacrificial O.sub.3 TEOS oxide layer 70 deposited before the sacrificial implant oxide etch. The invention can be applied in a variety of situations where the trench oxide is exposed to damaging etches.

Abstract: The invention is a process for filling narrow isolation trenches with thermal oxide using a nitride spacer and a second trench etch. The method begins by providing forming a pad oxide layer 20 and a first nitride layer 30 over a substrate. A first opening is formed in the pad oxide layer 20 and first nitride layer 30. The substrate is then etched through the first opening forming a first trench 40 in the substrate. A thin oxide film 50 is then grown over the substrate in the bottom and sidewalls of the first trench 40. Nitride spacers 60 are grown over the sidewalls of the first trench and over the thin oxide layer 40 on the sidewalls of the trench. A portion of the thin oxide film 50 on the bottom of the trench is etched. The substrate in the bottom of the first trench is etched forming a second trench 70. The etch exposes portions of the substrate on the bottom of the deeper second trench.

Abstract: A method of forming a trench isolation region. The method of the present invention comprises the steps of forming an opening in a semiconductor substrate, oxidizing the opening a first time, and then etching the oxidized opening with a wet etchant comprising HF. The opening is then oxidized a second time.

Abstract: A single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independently of crystal orientation.

Abstract: A method for forming within a trench within a substrate within an integrated circuit a planarized trench fill layer. There is first provided a substrate having a trench formed therein. There is formed upon the substrate at regions other than those within the trench a first integrated circuit layer which has a composition which inhibits formation upon the first integrated circuit layer of a trench fill layer which is subsequently formed upon the substrate and within the trench. There is also formed within the trench but not upon the substrate at regions other than those within the trench a second integrated circuit layer which has a composition which promotes formation within the trench of the trench fill layer which is subsequently formed upon the substrate and within the trench. Finally, there is formed upon the substrate and within the trench the trench fill layer.

Abstract: A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced wench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.

Abstract: Using sub-micron technology, silicon on insulator (SOI) rows and islands are formed in a silicon substrate. Trenches are directionally-etched in the silicon substrate, leaving rows of silicon between the trenches. Silicon nitride is then deposited over the trenches, extending partly down the sides of the trenches. An isotropic chemical etch is then used to partially undercut narrow rows of silicon in the substrate. A subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas. Devices, such as transistors for CMOS and DRAMs, are then formed in active areas, wherein the active areas are defined on the silicon rows by LOCal Oxidation of Silicon (LOCOS).

Abstract: A method for forming high aspect ratio, deep trenches in a semiconductor substrate with a composite etch mask structure including a thermally grown oxide surface layer as a plasma etch mask.

Abstract: An improved device isolation method for a semiconductor device capable of independently and compatibly providing an isolation film in the interior of well and an isolation film between wells during a consistent process, so that latch-up characteristic can be improved even in a device requiring a design rule of below 0.5 .mu.m, which includes a first step which combines a second step which forms a device isolation film within a well and a third step which forms a device isolation film between wells, the second and third steps being compatible to each other during the same step.

Abstract: A procedure for forming uniformly recessed fills of trench structures that maintains a planar wafer surface without need of any intermediate or final planarization technique. The procedure relies on isotropical etches with high selectivities and the presence of a sacrificial layer. Its only design requirement is that all trenches must at least have one dimension smaller than twice the recess depth.

Abstract: Device isolation is provided for a MOSFET circuit by providing channel stop regions comprising a distribution of dopants localized beneath and adjacent to corresponding field oxide regions. Channel stop regions are not formed under the channel regions of the MOSFETs and are selectively formed under the narrower field oxide regions which are most likely to provide inadequate device isolation. The channel stop regions are formed subsequent to the formation of field oxide regions, beginning by forming polysilicon spacers so that the polysilicon spacers extend over the bird's beak regions of the field oxide regions. Next, a channel stop mask having openings over selected field oxide regions is formed. Trenches are etched near the center of the exposed field oxide regions, leaving approximately 500 .ANG. of oxide on the bottom of the trench. Ions are implanted through the bottom of the trenches to form channel stop regions beneath the field oxide regions.

Abstract: When an isolating oxide is formed in a silicon substrate, a side wall is formed on the inner wall of a mask consisting of a lower silicon oxide layer and an upper silicon nitride layer for forming a groove in the silicon substrate in such a manner as to be laterally spaced from the inner wall of the upper silicon nitride layer, and the isolating oxide is formed from a silicon oxide layer deposited over the mask after removal of the side wall by using a polishing, thereby preventing the isolating oxide from undesirable side etching during an etching step for the lower silicon oxide layer.

Abstract: The present invention provides a method of manufacturing a trench having rounded top corners 28 in a substrate. The rounded top edges allow the formation of a gate oxide with a uniform thickness around the trench thereby reducing parasitic field FET problems. The method begins by forming a pad layer 14 over a semiconductor substrate 10. Next, an insulating layer 18 composed of silicon nitride is formed over the pad layer 14. A first opening 19 is formed in the insulating layer 18 and the pad layer 14 exposing the surface of the substrate. The first opening is defined by sidewalls of the pad layer 14 and of the insulating layer 18. An etch buffer layer 20 composed of polysilicon is formed over the resultant surface. In one etch step, the etch buffer layer 20 is anisotropically etched forming spacers 22 on the sidewalls of the pad layer 14 and of the insulating layer 18.

Abstract: Polysilicon (20) in a trench (21) is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall (26) of the trench (21) closest the beam source. Specifically, when the first side wall (26) is closest the beam source and the second side wall (27) is furthest from the beam source, the polysilicon on the first side wall (26) is almost as high as the first side wall (26), while the polysilicon on the more exposed side wall (27) is considerably lower than the first side wall (26) and approximates the shadow of the first side wall (26) on the second side wall (27) relative to the beam.

Abstract: A field effect transistor has a short gate and is fabricated by: doping the bottom surface of a depression to form a relatively lightly doped region in the bottom of the depression; forming the gate of the field effect transistor on the sidewall of the depression such that the gate is insulated from the sidewall by a thin insulating layer; and implanting dopants to form the drain region and the source region of the transistor using the gate to mask a part of the relatively lightly doped region. The part of the relatively lightly doped region which is masked by the gate during implanting of the source and drain regions constitutes a lightly doped drain region of the transistor. The drain of the transistor is formed into the bottom of the depression. The length of the gate is primarily determined by the depth and/or profile of the sidewall. The source-to-drain on-resistance of the transistor is low because the transistor does not have a lightly doped source region.

Abstract: An insulating film is formed on a main surface of a semiconductor substrate. A resist layer is formed on the entire surface of insulating film. An opening is formed in resist layer. By using resist layer as a mask, insulating film is etched, an opening is formed, and then resist is removed. By using insulating film as a mask, an impurity is introduced by ion implantation, and thus an ion-implanted impurity layer is formed. Heat treatment is performed so that ions included in ion-implanted impurity layer are diffused, forming an impurity layer. Etching is performed using insulating film as a mask, and trench is formed with an impurity layer left on the side and bottom surfaces of the trench, which impurity layer serves as a channel stopper. Then, a buried insulating layer is formed in the trench. Consequently, a method of forming an element isolating region is provided by which an impurity layer constituting the element isolating region can be formed minutely with easier control.

Abstract: A semiconductor structure includes isolation regions fabricated by a hybrid local oxidation of silicon (LOCOS) technique and a trench isolation technique. Wide and narrow gaps or spacings are etched in a multilayer silicon structure. The wide gaps are covered by a photoresist, and the narrow gaps are further etched to form deep trenches. The wide spacing and deep trenches are filled with an insulative material such as TEOS. The TEOS is etched and the structure is heated to cause local oxidation of silicon in the deep trench and wide spacing. The hybrid fabrication technique is particularly useful in complementary metal oxide semiconductor (CMOS) technology where wide isolation units are utilized to separate transistors sharing the same gate and trenches are utilized to isolate transistors sharing the same well.

Abstract: Silicon integrated circuits use a crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation (STI) structures as an O.sub.2 -barrier film. The crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared with as-deposited, amorphous Si.sub.3 N.sub.4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si.sub.3 N.sub.4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si.sub.3 N.sub.4 film is deposited at temperatures of 720.degree. C. to 780.degree. C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050.degree. C. to 1100.degree. C. for 60 seconds.