Heterojunctions Patents (Class 148/DIG72)
  • Patent number: 6033232
    Abstract: A method of fabricating a photodiode and at least one MOS device within a first active region and a second active region, respectively, of a substrate is disclosed. First, a gate structure is formed on the substrate within the second active region, and lightly-doped regions are formed by introducing first dopants into the substrate through the gate structure as masking. Then, a diffusion region is formed in the substrate within the first active region by ion implantation. Then, an insulating layer is formed to overlie the first and second active region, a portion of which within the second active region is thereafter patterned to sidewall spacers on the sidewalls of the gate structure. Subsequently, heavily-doped regions are formed by introducing second dopants throughout the second active region into the substrate by the gate structure and sidewall spacers as masking. In addition, the insulating layer can be thinned before the step of patterning the insulating layer to form the sidewall spacers is performed.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: March 7, 2000
    Assignee: Powerchip Semiconductor Corp.
    Inventors: James H. C. Lin, Chih-Wei Hsiung
  • Patent number: 5994194
    Abstract: A relatively simple method for providing relatively close spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) on a relatively uniform basis. An emitter and base layer are epitaxially grown on a substrate. An emitter mesa is patterned with an i-line negative photoresist using conventional photolithography. Baking before and after exposure is used to form a resist pattern with a re-entrant profile having about a 0.1 .mu.m resist overhang. The emitter layer is then etched with a wet etch and or isotropic dry etch to expose a portion of the base ohmic metal to make contact with the base. A second layer of an i-line negative photoresist is applied over the first photoresist. The second layer is used to pattern the base ohmic metal mask. The base ohmic metal is deposited by evaporation.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: November 30, 1999
    Assignee: TRW Inc.
    Inventor: Michael D. Lammert
  • Patent number: 5943577
    Abstract: In a method manufacturing a semiconductor device, a semiconductor layer having a device forming region is formed on substrate. Next, a region except for the device forming region is changed into an insulator. In this case, a conducting path is left across the semiconductor device to electrically connect the semiconductor device with an adjacent semiconductor device. Subsequently, the device forming region is etched on the condition that the conducting path is left. Finally, the conducting path is disrupted after the etching process. Thus, the semiconductor device and the adjacent semiconductor device are left in an electrical contact via the conducting path during the etching process. Consequently, the uniformity of the etching between the semiconductor devices is largely improved.
    Type: Grant
    Filed: December 1, 1997
    Date of Patent: August 24, 1999
    Assignee: NEC Corporation
    Inventors: Walter Contrata, Naotaka Iwata
  • Patent number: 5920773
    Abstract: An integrated circuit technology combines heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs) and other components along with interconnect metallization on a single substrate. In a preferred embodiment a flat substrate is patterned, using dry etching, to provide one or more mesas in locations which will eventually support HEMTs. A device stack including HEMT and HBT layers is built up over the substrate by molecular beam epitaxy, with the active HEMT devices located on the mesas within openings in the HBT layer. In this way the active HEMT is aligned with the HBT layer to planarize the finished integrated circuit.
    Type: Grant
    Filed: June 16, 1997
    Date of Patent: July 6, 1999
    Assignee: Hughes Electronics Corporation
    Inventors: Madjid Hafizi, Julia J. Brown, William E. Stanchina
  • Patent number: 5888843
    Abstract: A light-emitting diode having improved moisture resistance characteristics comprises a p-type gallium arsenide substrate and four epitaxial layers of Al.sub.x Ga.sub.1-x As (22, 23, 24 and 25). These epitaxial layers comprises an intervening layer (22) of p-type Al.sub.x Ga.sub.1-x As, a cladding layer (23) of p-type Al.sub.x2 Ga.sub.1-x2 As, an active layer (24) of Al.sub.x3 Ga.sub.1-x3 As, and a window layer (25) of Al.sub.x4 Ga.sub.1-x4 As so as to form a double-hetero structure, where x1, x2, x3 and x4 represent mixed crystal ratios of aluminum to arsenic of the layers, respectively, and meet the condition that:x2.gtoreq.x4>x1.gtoreq.x3 (0.ltoreq.x1, x2, x3, x4.ltoreq.1).
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: March 30, 1999
    Assignee: Hitachi Cable, Ltd.
    Inventors: Tooru Kurihara, Toshiya Toyoshima, Seiji Mizuniwa, Masahiro Noguchi
  • Patent number: 5846867
    Abstract: A method of producing a bipolar transistor includes the step of forming an emitter contact layer containing a high concentration of impurity by means of plasma doping or solid-state diffusion without causing diffusion of impurity in a base layer. This makes it possible to realize a thin base layer having a high impurity concentration.The invention also provides a method of producing a semiconductor device including a bipolar transistor and another device element such as a resistor element including a polysilicon layer containing an activated impurity in such a manner that both the bipolar transistor and the device element are disposed on the same single substrate, the method including the steps of: forming a polysilicon layer containing an activated impurity on the surface of a substrate; and then forming a base layer of the bipolar transistor. This method prevents the base layer from being affected by heat treatment on the polysilicon layer.
    Type: Grant
    Filed: December 17, 1996
    Date of Patent: December 8, 1998
    Assignee: Sony Corporation
    Inventors: Takayuki Gomi, Hiroaki Ammo
  • Patent number: 5801071
    Abstract: A semiconductor laser diode apparatus has a substrate of a first conduction type, a first clad layer of the first conduction type which is formed on the substrate, a current block layer which is formed on the first clad layer, a V groove stripe which is formed in a vertical direction so that a tip of the V groove can arrive at the first clad layer in depth, an active layer which is formed on the first clad layer and the current block layer along the V groove stripe without a low resistance layer, a second clad layer of a second conduction type which is formed on the active layer, a contact layer of the second conduction type which is formed on the second clad layer, a first electrode which is formed on a surface of the substrate which is reverse side of a surface on which the first clad layer is formed and a second electrode which is formed oil a surface of the contact layer. Therefore a low threshold current level can be achieved.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: September 1, 1998
    Assignee: Ricoh Company, Ltd.
    Inventor: Takashi Takahashi
  • Patent number: 5798277
    Abstract: An improved method for fabricating a heterojunction bipolar transistor which includes the steps of forming a buried collector, a collector thin film, and a collector sinker on a semiconductor substrate in order, forming a first silicon oxide film, a base electrode polysilicon layer, a nitride film, and an oxidation film on a resulting substrate exposing the first silicon oxidation film, forming a spacer insulation film at the lateral side of the exposed region, and defining an activation region, exposing the collector thin film of the activation region using a mask, and forming an auxiliary lateral film for an isolation of the device, forming a selective collector region by ion-implantating a dopant to the activation region which is limited by the auxiliary lateral film, removing the auxiliary lateral film, etching the exposed portion in an anisotropic etching method, and forming a shallow trench for a device isolation, forming a polysilicon lateral film to have a height which is the same as the height of the
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: August 25, 1998
    Assignees: Electronics and Telecommunications Research Institute, Korea Telecommunication Authority
    Inventors: Byung-Ryul Ryum, Tae-Hyeon Han, Deok-Ho Cho, Soo-Min Lee, Kwang-Eui Pyun
  • Patent number: 5789301
    Abstract: This is a method of fabricating a heterojunction bipolar transistor on a wafer. The method can comprise: forming a doped subcollector layer 31 on a semiconducting substrate 30; forming a doped collector layer 32 on top of the collector layer, the collector layer doped same conductivity type as the subcollector layer; forming a doped base epilayer 34 on top of the collector layer, the base epilayer doped conductivity type opposite of the collector layer; forming a doped emitter epilayer 36, the emitter epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming a doped emitter cap layer 37 on top of the emitter epilayer, the emitter cap layer doped same conductivity as the emitter epilayer; forming an emitter contact 38 on top of the emitter cap layer; forming a base contact on top of the base layer; forming a collector contact on top of the collector layer; and selective etching the collector layer to produce an undercut 45 beneath the base layer.
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: August 4, 1998
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: Darrell Glenn Hill
  • Patent number: 5736417
    Abstract: A heterejunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.
    Type: Grant
    Filed: May 13, 1996
    Date of Patent: April 7, 1998
    Assignee: TRW Inc.
    Inventors: Aaron K. Oki, Donald K. Umemoto, Liem T. Tran, Dwight C. Streit
  • Patent number: 5702958
    Abstract: The invention described herein includes, in one of its forms, a method for fabricating a semiconductor device having ledge material (148, 150, 152, 162) extending over an undercut region. The method comprises the step of forming a layer of material 164 in tensile stress over the undercut region, or region to be undercut. The layer of material in tensile stress can be a dielectric, such as silicon nitride, and provides support for the ledge material in subsequent processing steps.
    Type: Grant
    Filed: August 9, 1994
    Date of Patent: December 30, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: William U. Liu, Darrell G. Hill
  • Patent number: 5698460
    Abstract: A self-aligned planar heterojunction bipolar transistor (10) is fabricated by forming a base layer (18) and forming an emitter layer (20) on the base layer (18). An emitter cap layer (22) is formed on the emitter layer (20) and an interface layer (24) is formed on the emitter cap layer (22). A first implantation layer (26) is formed through the interface layer (24), the emitter cap layer (22), and the emitter layer (20) to the base layer (18). A second implantation layer (30) is formed through the interface layer (24), the emitter cap layer (22), and the emitter layer (20) to the base layer (18) and overlaps the first implantation layer (26). A portion of the interface layer (24), the emitter cap layer (22), and the implantation layers (26, 30) are removed and replaced by an insulating region (33). An emitter contact (38) is formed on the remaining emitter cap layer (22) and is isolated from the implantation layers (26, 30) by the insulating region (33).
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 16, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Jau-Yuann Yang, Donald L. Plumton, Francis J. Morris
  • Patent number: 5696007
    Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth and a polycide base electrode without using a trench for isolating between elements, thereby enhancing the performance thereof, which comprises the steps of: forming sequently a first oxidation film, an electrically conducting thin film and a second oxidation film on top of a substrate; patterning the second oxidation film and the conducting thin film to form a preliminary spacer; removing an exposed portion of the first oxidation film, and selectively growing a collector layer; oxidizing the collector layer to form a thermal oxidation film, and removing the preliminary spacer; depositing a polysilicon and forming a silicon oxidation film and a polysilicon spacer on the second oxidation film and the removed portion of the preliminary spacer, respectively; exposing the bas
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: December 9, 1997
    Assignees: Electronics and Telecommunications Research Institute, Korea Telecommunication Authority
    Inventors: Byung-Ryul Ryum, Tae-Hyeon Han, Deok-Ho Cho, Soo-Min Lee, Kwang-Eui Pyun
  • Patent number: 5681766
    Abstract: Generally, and in one form of the invention, an integrated circuit is disclosed for providing low-noise and high-power microwave operation comprising: an epitaxial material structure comprising a substrate 10, a low-noise channel layer 14, a low-noise buffer layer 16, a power channel layer 18, and a moderately doped wide bandgap layer 20; a first active region 24 comprising a first source contact 32 above the wide bandgap layer 22, a first drain contact 36 above the wide bandgap layer 22, wherein the first source contact 32 and the first drain contact 36 are alloyed and thereby driven into the material structure to make contact with the low-noise channel layer 14, and a first gate contact 28 to the low-noise buffer layer 16; and a second active region 26 comprising a second source contact 34 above the wide bandgap layer 22, a second drain contact 38 above the wide bandgap layer 22, wherein the second source contact 34 and the second drain contact 38 are alloyed and thereby driven into the material structure t
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 28, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Hua Quen Tserng, Paul Saunier
  • Patent number: 5672522
    Abstract: A method for fabricating an HBT in which the subcollector-base junction, which contributes to the base-collector capacitance of the device, is reduced by using a selective subcollector. In particular, subcollector areas of the device that do not contribute to collector resistance reduction are eliminated, thereby reducing the subcollector area, which, in turn, reduces the base-collector capacitance. As such, the maximum power-gain frequency f.sub.max is increased.
    Type: Grant
    Filed: March 5, 1996
    Date of Patent: September 30, 1997
    Assignee: TRW Inc.
    Inventors: Dwight Christopher Streit, Michael Lammert, Aaron Kenji Oki
  • Patent number: 5628834
    Abstract: The present invention broadly concerns layered structures of substantially-crystalline materials and processes for making such structures. More particularly, the invention concerns epitaxial growth of a substantially-crystalline layer of a first material on a substantially-crystalline second material different from the first material utilizing an approximately one monolayer thick monovalent surfactant element.
    Type: Grant
    Filed: May 9, 1995
    Date of Patent: May 13, 1997
    Assignee: International Business Machines Corporation
    Inventors: Matthew W. Copel, Rudolf M. Tromp
  • Patent number: 5610086
    Abstract: An epitaxial structure and method of manufacture for a single heterojunction bipolar transistor capable of being utilized in high-speed and high-power applications. Preferably, the epitaxial structure comprises an N-type collector made from InP, a P-type base made from InP, and an N-type emitter made from a semiconductor material of approximately 39 mole percent AlP and approximately 61 mole percent Sb.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: March 11, 1997
    Assignee: Hughes Aircraft Company
    Inventors: Takyiu Liu, Chanh Nguyen, Mehran Matloubian
  • Patent number: 5587327
    Abstract: A process for preparing a bipolar transistor for very high frequencies is described, which is especially advantageous for the preparation of heterobipolar transistors and leads to components with low parasitic capacities and low base lead resistance. The process includes forming a structured first layer with collector zone and insulation areas surrounding the collector zone on a monocrystalline lead layer. A series of monocrystalline transistor layers are grown on the first layer over the collector zone by differential epitaxy and a series of polycrystalline layers is grown at the same time over the insulation areas. A series of polycrystalline layers is designed as a base lead.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: December 24, 1996
    Assignees: Daimler Benz AG, Temictelefunken Microelectronic GmbH
    Inventors: Ulf Konig, Andreas Gruhle, Andreas Schuppen, Horst Kibbel, Harry Dietrich, Heinz-Achim Hefner
  • Patent number: 5583059
    Abstract: A SiGe-HBT structure for device integration on thin-SOI substrates is disclosed. The emitter and base regions are vertical while the collector contact is lateral in the otherwise MOS-like device structure. This allows one to integrate a SiGe base, the device capacitances are reduced, and the transistor can be combined with fully-depleted CMOS in a SOI-BiCMOS technology.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: December 10, 1996
    Assignee: International Business Machines Corporation
    Inventor: Joachim N. Burghartz
  • Patent number: 5573960
    Abstract: A method of manufacturing a semiconductor layer includes preparing a first semiconductor substrate; forming an etching stop layer on the surface of the first substrate; forming an active layer on the etching stop layer; forming a crystal defect reducing layer on the active layer; preparing a second semiconductor substrate having a heat conductivity higher than the heat conductivity of the first substrate; bonding the crystal defect reducing layer to the second substrate; selectively etching the first substrate to expose the etching stop layer; selectively etching the etching stop layer to expose the active layer, whereby the active layer is disposed on the second substrate with the crystal defect reducing layer therebetween. The heat dissipation property is significantly improved by the second substrate having a high heat conductivity and by reducing the thicknesses of the active layer and the crystal defect reducing layer.
    Type: Grant
    Filed: July 10, 1995
    Date of Patent: November 12, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigekazu Izumi, Norio Hayafuji
  • Patent number: 5571732
    Abstract: In one form of the invention, a bipolar transistor is disclosed, the transistor comprising a GaAs substrate in the (111) orientation 100, and an InGaAs region 106 over the substrate 100, the InGaAs region 106 having a first surface and a second surface, wherein the mole fraction of In in the InGaAs region 106 varies from said first surface to said second surface.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 5, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: William U. Liu
  • Patent number: 5525541
    Abstract: A method of making a component presenting at least one integrated electro-optical and/or photonic function, in which at least one dielectric layer of doped SiO.sub.x is deposited on a quantum well layer based on III/V materials, and in which the resulting sample is heat treated. The thickness of said dielectric layer, the nature of the dopant [isoelectronic, activating or blocking, and/or electronically active of n-type or of p.sub.-- type], and the concentration of the doping, and also the conditions of heat treatment, in such a manner as to confer the desired electro-optical and/or photonic properties to the component.
    Type: Grant
    Filed: January 30, 1995
    Date of Patent: June 11, 1996
    Assignee: France Telecom
    Inventors: Philippe Krauz, Elchuri K. Rao
  • Patent number: 5512496
    Abstract: A collector-up bipolar transistor having an undercut region (522) beneath extrinsic regions of a base layer (510) and an emitter layer (508). The extrinsic emitter region is depleted of charge carriers and provides passivation for the extrinsic portion of the base layer (508). Contact to the emitter layer may be made by forming contacts on the top surface of the substrate (500) or in a recess in the backside of the substrate.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 30, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Hin F. Chau, Hua Q. Tserng
  • Patent number: 5496745
    Abstract: Disclosed is a fabrication of a bipolar transistor using an enhanced trench isolation so as to improve integration and performance thereof, comprising the steps of sequentially etching back portions corresponding to a trench using a trench forming mask to a predetermined depth of the buried collector to form the trench; filling an isolation insulating layer into the trench; polishing the isolation insulating layer up to a surface of the silicon oxide layer; sequentially forming a second insulating layer on the isolating insulating layer and the silicon oxide layer; removing the first polysilicon layer and the first insulating layer formed on an inactive region other than an active region defined by the trench; thermal-oxidizing the collector layer formed on the inactive region to form a thermal oxide layer; removing the second insulating layer and sequentially forming a third polysilicon, a third insulating layer and a second nitride layer; etching back layers formed on a portion of the first insulating layer
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: March 5, 1996
    Assignees: Electronics and Telecommunications Research Institute, Korea Telecommunications Authority
    Inventors: Byung-Ryul Ryum, Tae-Hyeon Han, Soo-Min Lee, Deok-Ho Cho, Seong-Hearn Lee, Jin-Young Kang
  • Patent number: 5494836
    Abstract: The invention provides a heterojunction bipolar transistor which has a low reistance SiGe base and is high in current gain and cutoff frequency even at low temperatures near the liquid nitrogen temperature. The transistor fabrication process comprises forming an n-type collector layer on a silicon substrate and a dielectric film on the collector layer, forming a base electrode of p.sup.+ -type polysilicon having an opening on the dielectric film, isotropically etching the dielectric film on the collector layer by using the opening of the base electrode to form a window, forming an external base layer of p.sup.+ -type silicon on the collector layer exposed by the window, selectively etching the external base layer to form an aperture in a central region, forming a p-type SiGe intrinsic base layer in the aperture of the external base layer and then forming an n.sup.+ -type emitter on the intrinsic base layer.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: February 27, 1996
    Assignee: NEC Corporation
    Inventor: Kiyotaka Imai
  • Patent number: 5482875
    Abstract: A low power heterojunction field effect transistor (10, 30, 50, 60) capable of operating at low drain currents while having a low intermodulation distortion. A channel restriction region (9, 38, 51) is formed between the gate electrodes (24, 41, 69) and the drain electrodes (25, 46, 65). The channel restriction region (9, 38, 51) depletes the channel layer (13, 33) thereby constricting a channel and lowering a drain saturation current. The channel restriction region (9, 38, 51) may be used to set a desired drain saturation current such that a second derivative of the transconductance with respect to the gate-source voltage is approximately zero and a first derivative of the transconductance with respect to the gate-source voltage is, approximately, a relative maximum at the desired operating point.
    Type: Grant
    Filed: April 18, 1994
    Date of Patent: January 9, 1996
    Assignee: Motorola, Inc.
    Inventors: Rimantas L. Vaitkus, Saied N. Tehrani, Vijay K. Nair, Herbert Goronkin
  • Patent number: 5468658
    Abstract: This is a p-n junction device and the device comprises: a substrate 10 composed of a semiconductor material; a heavily doped n type sub-collector layer 14 over the substrate; a n type collector layer 16 over the sub-collector layer; a heavily doped p type first base layer 18, over the collector layer; a p type second base layer 20, substantially thinner than the first base layer, over the first base layer, with the second base layer being less heavily doped than the first base layer; and a n type emitter layer 24 over the second base layer, whereby, the second base layer serves as a diffusion barrier between the base and the emitter. Other devices and methods are also disclosed.
    Type: Grant
    Filed: December 7, 1993
    Date of Patent: November 21, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Burhan Bayraktaroglu
  • Patent number: 5459084
    Abstract: Disclosed is a fabrication of a hetero-junction bipolar transistor in which a base parasitic capacitance is fully reduced by using a metallic silicide as a base, comprising the steps of injecting an impurity in a silicon substrate to form a conductive buried collector region; growing a collector epitaxial layer on the buried collector region and forming a field oxide layer; selectively injecting an impurity into the collector epitaxial layer to form a collector sinker; sequentially forming a base layer and an first oxide layer thereon; patterning the first oxide layer to define an extrinsic base region; ion-implanting an impurity in the extrinsic base region using a patterned oxide layer as a mask and removing the patterned oxide layer; depositing a metallic silicide film thereon to form a base electrode thin film; forming a capping oxide layer of about 500 .ANG.
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: October 17, 1995
    Assignees: Electronics and Telecommunications Research Institute, Korea Telecommunication Authority
    Inventors: Byung-Ryul Ryum, Deok-Ho Cho, Tae-Hyeon Han, Soo-Min Lee, Oh-Joon Kwon
  • Patent number: 5445976
    Abstract: The invention described herein includes, in one of its forms, a method for fabricating a bipolar transistor having a reduced base-collector capacitance. A specific embodiment includes forming a selectively etchable material 44 over a highly doped subcollector layer 42, removing portions of the selectively etchable material 44 and then growing collector 46, base 48, and emitter 50 layers over the structure. The selectively etchable material 44 may then be removed to form an undercut region between the highly doped subcollector layer 42 and the highly doped base 48. The structure provides the advantage of improved high-frequency and high-power operation.
    Type: Grant
    Filed: August 9, 1994
    Date of Patent: August 29, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy S. Henderson, Darrell G. Hill
  • Patent number: 5436181
    Abstract: A method of self aligning an emitter contact includes forming a base layer (18) on a portion of a collector layer (16). An interface layer (22) is formed on the base layer (18) such that a portion of the base layer (18) remains exposed. An emitter layer (24) is formed on the collector layer (16), the interface layer (22), and the exposed portion of the base layer (18). An emitter cap layer (26) is formed on the emitter layer (24) over the previously exposed area of the base layer (18). An insulating layer (28) is formed on the interface layer (22). An emitter contact (36) is formed on the emitter cap layer (26) at the previously exposed area of the base layer (18). The insulating layer (28) isolates the emitter contact (36) from the base layer (18) and a subsequently formed base contact (38). The insulating layer (28) ensures isolation between the emitter contact ( 36) and the base contact (38) despite misalignment of the emitter contact (36) during formation.
    Type: Grant
    Filed: April 18, 1994
    Date of Patent: July 25, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Francis J. Morris, Jau-Yuann Yang, Donald L. Plumton, Han-Tzong Yuan
  • Patent number: 5434091
    Abstract: This is a method of fabricating a bipolar transistor on a wafer. The method can comprise: forming a doped emitter contact layer 31 on a substrate 30; forming a doped emitter layer 32 on top of the emitter contact layer, the emitter layer doped same conductivity type as the emitter contact layer; forming a doped base epilayer 34 on top of the emitter layer, the base epilayer doped conductivity type opposite of the emitter layer; forming a doped collector epilayer 36, the collector epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming an collector contact 38 on top of the collector layer; forming a base contact 40 on top of the base layer; forming a emitter contact 44 on top of the emitter contact layer; and selective etching the emitter layer to produce an undercut 45 beneath the base layer.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: July 18, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Darrell Hill, Shou-Kong Fan, Ali Khatibzadeh
  • Patent number: 5429957
    Abstract: A base layer interposed between an n-type GaAs collector layer and an n-type AlGaAs emitter layer is composed of a p-type InAlGaAs. From a collector/base interface to an emitter/base interface, an InAs composition of the base layer is decreased and a concentration of carbon as a p-type impurity thereof is increased so as to obtain a built-in internal field intensity in the base layer by a cooperative effect of the graded-bandgap and the impurity concentration gradient, thus reducing a base transit time of electrons. The base layer is fabricated according to MOMBE using TMG as a gallium source, controlling the InAs composition, so that a desired carbon concentration gradient is automatically formed. Thereby, a high performance, heterojunction bipolar transistor with an increased built-in internal field intensity in the base layer is obtained.
    Type: Grant
    Filed: August 8, 1994
    Date of Patent: July 4, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshinobu Matsuno, Atsushi Nakagawa, Takashi Hirose, Kaoru Inoue
  • Patent number: 5427965
    Abstract: A heterojunction device including a first semiconductive layer on a substrate, a barrier layer on the first layer, a second semiconductive layer on the barrier layer and a multi-layer cap, on the second semiconductive layer. First and second gates positioned on layers of the cap to define first and second transistors, with the cap layers being selected and etched to pin the Fermi level in a first transistor conduction channel in the second semiconductive layer such that the number of carriers in the first conduction channel are substantially less than the number of carriers in surrounding portions of the second semiconductive layer and the Fermi level in a second transistor conduction channel in the first semiconductive layer such that the number of carriers in the second conduction channel are substantially less than the number of carriers in surrounding portions of the first semiconductive layer.
    Type: Grant
    Filed: June 20, 1994
    Date of Patent: June 27, 1995
    Assignee: Motorola, Inc.
    Inventors: Saied N. Tehrani, X. T. Zhu, Herbert Goronkin, Jun Shen
  • Patent number: 5420059
    Abstract: A superheterojunction Field Effect Transistor (FET) with a multi-region channel on a Silicon (Si) substrate. The FET is a Metal Semiconductor FET (MESFET) or, alternatively, a Junction FET (JFET). The multi-region channel has: A first region of Si extending from the FET's source to a point under the FET's gate, beyond the gate's midpoint; a second region extending from the first region to the FET's drain, comprised of a superlattice of alternating Si and SiGe layers; and, a third region of Si extending under the first two regions from the source to the drain. The first region has a laterally graded dopant that creates an accelerating electric field. The superlattice structure increases electron mobility and transit velocity.
    Type: Grant
    Filed: February 18, 1994
    Date of Patent: May 30, 1995
    Assignee: International Business Machines Corporation
    Inventors: S. Noor Mohammad, Robert B. Renbeck
  • Patent number: 5420052
    Abstract: A method of fabricating a semiplanar heterojunction bipolar transistor (10) includes forming a subcollector layer (12) and a collector layer (16) onto a substrate layer (14). A collector implant plug (18) is selectively implanted to connect the subcollector layer (12) to the surface of the heterojunction bipolar transistor (10). A second epitaxial growth process causes a base layer (22), an emitter layer (24), and an emitter cap layer (26) to form on the collector layer (16) and the collector implant plug (18). By this process, the base layer (22) is not exposed to subsequent harmful fabrication steps. A base plug region (28) is selectively implanted to connect the base layer (22) to the surface of the heterojunction bipolar transistor (10). A base contact (32) and an emitter contact (30) are selectively formed within the heterojunction region on the base plug region (28) and the emitter cap layer (26), respectively.
    Type: Grant
    Filed: April 19, 1994
    Date of Patent: May 30, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Francis J. Morris, Jau-Yuann Yang, Donald L. Plumton, Han-Tzong Yuan
  • Patent number: 5411903
    Abstract: Self-aligned HFETS are fabricated by providing a semi-insulating substrate and forming a low bandgap III-V semiconductor layer thereon. A first dielectric layer of a first dielectric material is formed on the III-V layer and first and second openings are formed through the first dielectric layer and the III-V layer. After forming dielectric spacers of a second dielectric material on the sidewalls of the first and second openings, gates are formed therein. The first dielectric layer is subsequently removed and source and drain regions are formed in the III-V layer and substrate adjacent to each of the gates. The formation of the source and drain regions is self-aligned to the gates. After forming isolation regions between devices, ohmic contacts to the source and drain regions, all being of a like material, are formed. This formation is also self-aligned to the gates.
    Type: Grant
    Filed: June 1, 1993
    Date of Patent: May 2, 1995
    Assignee: Motorola, Inc.
    Inventors: Schyi-yi Wu, Jenn-Hwa Huang, Faivel Pintchovski
  • Patent number: 5407842
    Abstract: This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.
    Type: Grant
    Filed: June 8, 1994
    Date of Patent: April 18, 1995
    Assignee: Texas Intruments Incorporated
    Inventors: Francis J. Morris, Jau-Yuann Yang, Donald L. Plumton, Han-Tzong Yuan
  • Patent number: 5405793
    Abstract: In one form of the invention, a field effect transistor is disclosed, the transistor comprising: a channel between a source and a drain, the channel comprising: a first region 22 of a first semiconductor material having a first doping concentration; a second region 20 of a second semiconductor material having a second doping concentration, the second region 20 lying above the first region 22; a third region 18 of the first semiconductor material having a third doping concentration, the third region lying above the second region 20, wherein the first doping concentration is higher than the second and third doping concentrations; and a gate electrode 12 lying above the third region 18, whereby an electrical current flows in the channel primarily in the first region 22 or primarily in the second region 20 by varying a voltage on the gate electrode 12.
    Type: Grant
    Filed: June 28, 1994
    Date of Patent: April 11, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Pertti K. Ikalainen, Larry C. Witkowski
  • Patent number: 5391512
    Abstract: A multistage amplifier device including an amplifier at the first stage or each of active elements of amplifiers at plural stages containing the first stage and excluding the last stage which is formed of FETs 1a and 1b including a gate having a self-alignment structure, and amplifiers at the remaining subsequent stages which are formed of FETs 1c and 1d including a gate electrode on an operating layer sandwiched between source and drain high impurity density regions, one edge portion at a source side of the gate electrode being overlapped through an insulating layer with the source high impurity density region while the other edge portion at a drain side of the gate electrode does not expand to the drain high impurity density region.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: February 21, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Nobuo Shiga
  • Patent number: 5391504
    Abstract: Generally, and in one form of the invention, an integrated circuit comprising a bipolar transistor and a field effect transistor, wherein a channel of the field effect transistor and a base of the bipolar transistor are formed from a base epitaxial layer 16, and whereby field effect and bipolar transistors are formed within a common material structure is disclosed. In another form of the invention, an integrated circuit comprising a substrate 10, an epitaxial subcollector layer 12, an epitaxial collector layer 14, an epitaxial base layer 16, an epitaxial emitter layer 18, a bipolar transistor formed with an emitter electrical contact 20, 28, 35 to the emitter layer 18, a base contact 34 to the base layer 16, and a collector contact 42 to the subcollector layer 12, and a field effect transistor formed with a first gate contact 20, 30, 39 to the emitter layer 18, a first source contact 36 to the base layer 16, and a first drain contact 37 to the base layer 16, is disclosed.
    Type: Grant
    Filed: November 3, 1993
    Date of Patent: February 21, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Darrell Hill, Albert H. Taddiken
  • Patent number: 5389554
    Abstract: In one form of the invention, an emitter structure for a bipolar transistor is disclosed. The structure is comprised of an emitter layer 6 of Al.sub.x Ga.sub.1-x As, where x>0.4, abutting a base layer 8.
    Type: Grant
    Filed: November 30, 1993
    Date of Patent: February 14, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: William U. C. Liu, Darrell G. Hill
  • Patent number: 5369042
    Abstract: This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.
    Type: Grant
    Filed: March 5, 1993
    Date of Patent: November 29, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Francis J. Morris, Jau-Yuann Yang, Donald L. Plumton, Han-Tzong Yuan
  • Patent number: 5362657
    Abstract: A method of fabricating a heterojunction bipolar transistor and the transistor by providing a substrate of a group III-V semiconductor material, doping a first selected region at a surface of the substrate a predetermined first conductivity type, concurrently or separately incorporating a group III element into a portion of the first selected region, doping the portion of the first selected region to a second conductivity type with a laser beam to cause melting and subsequent recrystallization of said substrate and forming contacts to the portion of the first selected region and to the first selected region. The portion of the first selected region extends farther into the substrate than the remainder of the first selected region. A complementary transistor can be concurrently fabricated using the same steps except that p-implants replace the n-implants and n-doped InGaAs instead of p-doped InGaAs forms the base layer.
    Type: Grant
    Filed: January 10, 1994
    Date of Patent: November 8, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy S. Henderson, Donald L. Plumton, Han-Tzong Yuang
  • Patent number: 5346855
    Abstract: Disclosed is a method of making InP-based DFB lasers that can reliably mitigate or substantially prevent erosion of the grating during overgrowth. The method comprises contacting, prior to overgrowth, the grating with a sulfurcontaining aqueous medium, e.g., 80 parts by weight H.sub.2 O/20 parts by weight ammonium sulfide.
    Type: Grant
    Filed: January 19, 1993
    Date of Patent: September 13, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Erin K. Byrne, Utpal K. Chakrabarti, Todd R. Hayes
  • Patent number: 5346840
    Abstract: A heterojunction bipolar transistor includes a tungsten layer formed on a base layer. An insulating sidewall is formed on the base layer and along a vertical wall of an emitter layer formed on the base layer. An end of the tungsten layer faces a base-emitter heterojunction through the sidewall.
    Type: Grant
    Filed: December 7, 1992
    Date of Patent: September 13, 1994
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Fujioka
  • Patent number: 5344786
    Abstract: A method of fabricating heterojunction bipolar transistors (HBTs) including epitaxial growth of collector, base and emitter layers, allowing for self-aligned emitter-base contacts to minimize series base resistance and to reduce total base-collector capacitance.
    Type: Grant
    Filed: September 9, 1992
    Date of Patent: September 6, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Burhan Bayraktaroglu
  • Patent number: 5340755
    Abstract: A planar heterobipolar transistor and its methods for manufacture provide that the transistor has the base-emitter region separated from the collector terminal by a collector parting trench and the parting trench structure may be used to separate the transistor from adjoining function components.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: August 23, 1994
    Assignee: Siemens Aktiegensellschaft
    Inventors: Hans-Peter Zwicknagl, Joachim Hoepfner, Lothar Schleicher
  • Patent number: 5324671
    Abstract: An integrated circuit including both bipolar and field effect devices is disclosed, comprising a first continuous layer 102/104 of semi-insulating semiconductor material having a continuous first surface, a doped channel region 108 in the first layer 102/104 at the first surface of the first layer 102/104, a doped collector region 114 in the first layer 102/104 at the first surface spaced from the channel region 108, a doped base layer 122 on the collector region 114, the base layer 122 of conductivity type opposite that of the collector region 114, a doped emitter region 124 on the base layer 122, the emitter region 124 of the same conductivity type as the collector 114 to provide a bipolar device, the emitter region 124 made of semiconductor material with a wider bandgap than the base layer 122 semiconductor material, source and drain contacts 138 on the channel region 108, a gate 146 on the channel region 108 between the source and drain contacts 138 to provide a field effect device, and electrical couplin
    Type: Grant
    Filed: January 23, 1992
    Date of Patent: June 28, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Burhan Bayraktaroglu
  • Patent number: 5322808
    Abstract: A donor layer (17) including an undoped wide bandgap material (14) and an n-type dopant (16) is deposited on a substrate (12) by molecular beam epitaxy (MBE) at a first temperature which is high enough for optimal growth of the donor layer (17). The dopant (16) is silicon or another material which exhibits surface segregation in the wide bandgap material (14) at the first temperature. An undoped spacer layer (18) of the wide bandgap material is deposited on the donor layer (17) at a second temperature which is sufficiently lower than the first temperature that surface segregation of the dopant material from the donor layer (17) into the spacer layer (18) is substantially suppressed. A channel layer (20) of a narrow bandgap material is formed on the spacer layer (18) at a third temperature which is higher than the second temperature and selected for optimal growth of the channel layer (20).
    Type: Grant
    Filed: February 19, 1993
    Date of Patent: June 21, 1994
    Assignee: Hughes Aircraft Company
    Inventors: April S. Brown, Joseph A. Henige, Mark Lui, Loi Nguyen, Robert A. Metzger, William E. Stanchina
  • Patent number: 5322814
    Abstract: A method is provided for forming selective electrical contacts on a structure of alternating ultrathin semiconductor layers of two different types, so that electrical connection can be made separately to the layers of a given type. Selective etching of first one type of layers at one side of the structure and then the second type of layers at another side produces digitate edge patterns suitable for deposition of ohmic contacts. Any method can be used which directs particles of a conducting material onto the digitate edge portions at an angle to build up material on only one set of layers at a time. The gaps between adjacent protruding layers of the same doping type are filled in as the deposition continues. In this way the high-temperature steps required for diffusion or ion implantation activation are avoided. For a mesa-etched n-i-p-i chip the contact is allowed to extend onto adjacent regions of the supporting wafer so that further electrical contacting can be done in those regions.
    Type: Grant
    Filed: August 5, 1987
    Date of Patent: June 21, 1994
    Assignee: Hughes Aircraft Company
    Inventors: Irving D. Rouse, Wei-yu Wu