Heterojunctions Patents (Class 148/DIG72)
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Patent number: 4777148Abstract: A distributed feedback (DFB) type laser and a method and apparatus for forming same wherein a quaternary semiconductor active lasing strip of material is buried between a substrate of binary compound of one type conductivity material and a mesa binary compound body of opposite type conductivity and a periodic grating structure is etched into the plateau of the mesa. In one embodiment, ohmic contacts are provided on either side of the grating structure and the mesa is undercut adjacent the active strip to partly isolate the ohmic contacts from the homojunction formed when the active strip is buried, preferably using a mass-transport process. In another embodiment, the ohmic contacts are formed on the top of a deeply etched grating structure. A buried layer double heterostructure (DH) laser is also described with DFB grating formed on the side walls of the layer. Additionally, a surface emitting diode laser with DFB is described.Type: GrantFiled: September 1, 1987Date of Patent: October 11, 1988Assignee: Massachusetts Institute of TechnologyInventors: Zong-Long Liau, Dale C. Flanders, James N. Walpole
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Patent number: 4774205Abstract: Monolithic integration of Si MOSFETs and gallium arsenide MESFETs on a silicon substrate is described herein. Except for contact openings and final metallization, the Si MOSFETs are first fabricated on selected areas of a silicon wafer. CVD or sputtering is employed to cover the wafer with successive layers of SiO.sub.2 and Si.sub.3 N.sub.4 to protect the MOSFET structure during gallium arsenide epitaxy and subsequent MESFET processing. Gallium arsenide layers are then grown by MBE or MOCVD or VPE over the entire wafer. The gallium arsenide grown on the bare silicon is single crystal material while that on the nitride is polycrystalline. The polycrystalline gallium arsenide is etched away and MESFETs are fabricated in the single crystal regions by conventional processes. Next, the contact openings for the Si MOSFETs are etched through the Si.sub.3 N.sub.4 /SiO.sub.2 layers and final metallization is performed to complete the MOSFET fabrication.Type: GrantFiled: June 13, 1986Date of Patent: September 27, 1988Assignee: Massachusetts Institute of TechnologyInventors: Hong K. Choi, Bor-Yeu Tsaur, George W. Turner
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Patent number: 4769341Abstract: A semiconductor device comprising an epitaxially grown tin and Group IV compound semiconductor region on which at least one other semiconductor is grown lattice matched to the adjacent portion of the tin containing region. A large number of semiconductors may thus be grown.Type: GrantFiled: December 29, 1986Date of Patent: September 6, 1988Assignee: American Telephone and Telegraph Company, AT&T Bell LaboratoriesInventor: Sergey Luryi
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Patent number: 4766092Abstract: When a semiconductor device is produced by growing epitaxially a compound semiconductor layer on a Si or Ge substrate, lattice matching between the substrate crystal and the compound semiconductor layer to be formed on the substrate can be improved by ion-implanting an ion species element, which increases the lattice constant of Si or Ge as the substrate, into the Si or Ge substrate in order to increase its lattice constant. In comparison with conventional semiconductor devices using Si or Ge into which ion implantation is not made, the semiconductor device produced by the method described above can improve remarkably its characteristics. In the case of a semiconductor laser device, for example, its threshold value drops drastically and its service life can be prolonged remarkably.Type: GrantFiled: December 2, 1986Date of Patent: August 23, 1988Assignee: Hitachi, Ltd.Inventors: Takao Kuroda, Kenji Hiruma, Hiroyoshi Matsumura
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Patent number: 4758534Abstract: A process for fabricating a semiconductor-metal-semiconductor electronic device and the device formed thereby from a semiconductor substrate is described. The substrate forms a first active region of the device. A porous layer of conductive material is deposited on the substrate preferably by molecular beam epitaxy forming a control region. A layer of a semiconductor material epitaxially matched to the substrate is then grown on the layer of conductive material so that the layer of semiconductor material forms a second active region of an electronic device.Type: GrantFiled: November 13, 1985Date of Patent: July 19, 1988Assignee: Bell Communications Research, Inc.Inventors: Gustav E. Derkits, Jr., James P. Harbison
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Patent number: 4748132Abstract: As a process for fabricating uniform patterns fine enough to produce a quantum size effect, the use of electron halography is proposed. Disclosed examples employing a process are methods of manufacturing a semiconductors laser whose threshold current is approximately 1 mA, and a permeable transistor and bistable device whose response rates are 100 GHz.Type: GrantFiled: December 15, 1986Date of Patent: May 31, 1988Assignee: Hitachi, Ltd.Inventors: Tadashi Fukuzawa, Akira Tonomura, Naoki Chinone
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Patent number: 4728616Abstract: A heterojunction transistor doped to form a specially-shaped emitter-base conduction band step or spike is disclosed. The potential barrier is then utilized to accelerate electrons across the base region at the maximum velocity obtainable without scattering electrons to the upper valleys. In this manner the electrons may be transported across the base region virtually without collisions and at a velocity approximately 10 times that of normal electron diffusion across the base region, thus increasing the frequence response of the transistor.Type: GrantFiled: February 20, 1987Date of Patent: March 1, 1988Assignee: Cornell Research Foundation, Inc.Inventors: David G. Ankri, Lester F. Eastman, Walter H. Ku
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Patent number: 4720309Abstract: This absorbant is of the type formed by superlattice constituted by a stack of films of two different semiconductor materials having gaps of different heights. Thus, a potential well is produced in each film corresponding to the semiconductor with the smallest gap and a potential barrier in each film corresponding to the semiconductor with the largest gap. This saturatable absorbant is characterized in that the films corresponding to the semiconductor with the smallest gap have a thickness, which can assume two values, one small and the other large.Application in optics to the production of mode locking lasers and all optical logic gates.Type: GrantFiled: July 9, 1986Date of Patent: January 19, 1988Inventors: Benoit Deveaud, Andre Chomette, Andre Regreny
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Patent number: 4716445Abstract: The heterojunction bipolar transistor has a structure of wide band-gap transistor and comprises a collector region having an N-type GaAs layer, a base region having a P-type germanium layer formed on the N-type GaAs layer, and an emitter region having an N-type semiconductor layer of mixed crystal of silicon and germanium formed on the P-type germanium layer. The mixed crystal of the N-type semiconductor layer may have a uniform distribution of silicon or a graded distribution of silicon in which a content of silicon is zero at the surface facing the P-type germanium layer and is continuously increased with distance from the surface facing the P-type germanium layer.Type: GrantFiled: January 20, 1987Date of Patent: December 29, 1987Assignee: NEC CorporationInventor: Jun'ichi Sone
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Patent number: 4707197Abstract: Described is a method for producing metal silicide/silicon heterostructures. The method comprises depositing a very thin Si "template" layer on a relatively cold (<200.degree. C.) silicide substrate, raising the substrate temperature into the approximate range 500.degree.-800.degree. C. and maintaining it there while depositing further Si onto the template. The resulting Si layer can be of high crystalline perfection. The silicide advantageously is CoSi.sub.2, Co.sub.x Ni.sub.1-x Si.sub.2, CoSi.sub.y Ge.sub.2-y, or NiSi.sub.2, with 0<x<1,1<y<2.Type: GrantFiled: January 17, 1986Date of Patent: November 17, 1987Assignee: American Telephone and Telegraph Company, AT&T Bell LaboratoriesInventors: John C. Hensel, Anthony F. J. Levi, Raymond T. Tung
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Patent number: 4698652Abstract: Herein disclosed is a semiconductor device in which control means for carriers migrating in a first semiconductor includes an interface state layer lying on the first semiconductor and a second conductor layer lying on the interface state layer. The interface state layer has its Fermi level pinned to that of the second semiconductor layer. By thus constructing an FET or the semiconductor device, an inversion or accumulation layer can be easily formed in the interface merely by applying a voltage to the control means.Type: GrantFiled: May 8, 1985Date of Patent: October 6, 1987Assignee: Hitachi, Ltd.Inventors: Yasunari Umemoto, Susumu Takahashi, Yuichi Ono
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Patent number: 4695857Abstract: The superlattice type semiconductor material has a multilayered structure of first layers of semiconductor containing impurities and having a thickness thinner than electron or hole wavelength and second layers of semiconductor free from impurities or insulator having such a thickness that electrons or holes may penetrate by tunneling effect, the first and second layers being alternately piled. Electrons or holes distribute uniformly over the entire of the multilayered structure to show a property of uniform semiconductor material.Type: GrantFiled: June 25, 1984Date of Patent: September 22, 1987Assignee: NEC CorporationInventors: Toshio Baba, Takashi Mizutani, Masaki Ogawa
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Patent number: 4675709Abstract: A semiconductor quantized layered structure comprising first and second different semiconductor materials comprising compound semiconductors from both the Group III and Group V elements and forming a plurality of alternate layers, each interfaced to its adjacent layer in a semiconductor homojunction or heterojunction. The bottom of the conduction bands of the first and second materials are at different energy levels and the tops of the valence bands of the first and second materials are at different energy levels. The bottoms of the conduction bands of the first and second materials form a plurality of serially arranged potential wells and barriers due to differences in the band structures of the different materials forming alternate layers and the interfacing of the layers forming heterojunctions so that the thinness of the layers will spatially localize electrons to obtain quantized electron states in one dimension transverse to the longitudinal extent of said layers.Type: GrantFiled: January 21, 1986Date of Patent: June 23, 1987Assignee: Xerox CorporationInventors: Donald R. Scifres, Robert D. Burnham
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Patent number: 4644381Abstract: An integrated injection logic (I.sup.2 L) semiconductor structure is disclosed which may be advantageously implemented in a group III-V compound semiconductor such as gallium arsenide. The base region of the lateral transistor is made extremely thin (less than one-tenth micron) by use of "regrowth" techniques. The structure of the vertical transistor is simplified by using a Schottky collector.Type: GrantFiled: April 8, 1985Date of Patent: February 17, 1987Assignee: Siemens Corporate Research & Support, Inc.Inventor: Chan-Long Shieh
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Patent number: 4637122Abstract: An integrated quantum well laser structure which has a plurality of quantum well lasers for providing a plurality of light beams each having a different wavelength for use in wavelength division multiplexing.Type: GrantFiled: July 29, 1985Date of Patent: January 20, 1987Assignee: Honeywell Inc.Inventors: James K. Carney, Robert M. Kolbas
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Patent number: 4611388Abstract: A heterojunction bipolar transistor having an n- type epitaxial indium phosphide collector layer grown on a semi-insulating indium phosphide substrate with an n+ buried layer, a p- type indium phosphide base and an epitaxial, n- type boron phosphide wide gap emitter. The p- type base region is formed by ion implantation of magnesium ions into the collector layer. The transistor is applicable to millimeter wave applications due to the high electron mobility in the indium phosphide base. The wide gaps of both the boron phosphide (2.2 eV) and indium phosphide (1.34 eV) permit operation up to 350.degree. C. The transistor is easily processed using metal organic-chemical vapor deposition (MO-CVD) and standard microelectronic techniques.Type: GrantFiled: April 15, 1985Date of Patent: September 16, 1986Assignee: Allied CorporationInventor: Krishna P. Pande
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Patent number: 4588451Abstract: Expitaxial composite comprising thin films of a Group III-V compound semiconductor such as gallium arsenide (GaAs) or gallium aluminum arsenide (GaAlAs) on single crystal silicon substrates are disclosed. Also disclosed is a process for manufacturing, by chemical deposition from the vapor phase, epitaxial composites as above described, and to semiconductor devices based on such epitaxial composites. The composites have particular utility for use in making light sensitive solid state solar cells.Type: GrantFiled: April 27, 1984Date of Patent: May 13, 1986Assignee: Advanced Energy Fund Limited PartnershipInventor: Stanley M. Vernon
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Patent number: 4578127Abstract: Single GaAs quantum well or single GaAs active layer or single reverse interface structures with Al.sub.x Ga.sub.1-x As barrier layers have improved qualities when one or more narrow bandgap GaAs getter-smoothing layers, which are thin, are grown and are incorporated in the barrier layer before and in close proximity to the active layer.Type: GrantFiled: August 13, 1982Date of Patent: March 25, 1986Assignee: AT&T Bell LaboratoriesInventors: Arthur C. Gossard, Robert C. Miller, Pierre M. Petroff
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Patent number: 4575919Abstract: A method of making a ridge waveguide laser with the ridge being grown through a stripe opened in an oxide layer covering one of the cladding layers is described. In one embodiment, the cladding layer is corrugated and the ridge waveguide laser is a distributed feedback laser.Type: GrantFiled: May 24, 1984Date of Patent: March 18, 1986Assignee: AT&T Bell LaboratoriesInventors: Ralph A. Logan, Won-Tien Tsang
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Patent number: 4573255Abstract: Prior to packaging, semiconductor lasers are purged by being subjected first to high temperature and high current simultaneously so as to suppress stimulated emission and stress the shunt paths which allow leakage current to flow around the active region. A prudent, but nonessential, second step is to lower the temperature and/or current so that the lasers emit stimulated emission (preferably strongly, near the peak output power), thereby stressing the active region. Lasers subjected to such a purge exhibit stabilized degradation rates in short times (of the order of a few hours) and provide a robust population which meets the performance criteria of long lifetime systems.Type: GrantFiled: March 22, 1984Date of Patent: March 4, 1986Assignee: AT&T Bell LaboratoriesInventors: Eugene I. Gordon, Robert L. Hartman, Franklin R. Nash
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Patent number: 4566171Abstract: In the fabrication of buried heterostructure InP/InGaAsP lasers, mask undercutting during the mesa etching step is alleviated by a combination of steps which includes the epitaxial growth of a large bandgap InGaAsP cap layer (1.05 eV.ltorsim.E.sub.g .ltorsim.1.24 eV) and the plasma deposition of a SiO.sub.2 etch masking layer. Alternatively, the cap layer may be a bilayer: an InGaAs layer or narrow bandgap InGaAsP (E.sub.g .ltorsim.1.05 eV), which has low contact resistance, and a thin InP protective layer which reduces undercutting and which is removed after LPE regrowth is complete. In both cases, etching at a low temperature with agitation has been found advantageous.Type: GrantFiled: June 20, 1983Date of Patent: January 28, 1986Assignee: AT&T Bell LaboratoriesInventors: Ronald J. Nelson, Randall B. Wilson
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Patent number: 4561916Abstract: A method for the growth of a compound semiconductor comprises growing on a silicon substrate a polycrystalline layer of a desired Group III-V compound semiconductor or a crystal layer of the desired Group III-V compound semiconductor having inferior crystallinity, growing on the formed layer at least one layer of the same semiconductor as the desired Group III-V compound semiconductor and at least one layer of a Group III-V compound semiconductor having a lattice constant approximating the lattice constant of the desired Group III-V compound semiconductor, which layers are alternately disposed, and growing on the alternately disposed layers a layer of the desired Group III-V compound semiconductor.Type: GrantFiled: July 2, 1984Date of Patent: December 31, 1985Assignees: Agency of Industrial Science and Technology, Ministry of International Trade and IndustryInventors: Masahiro Akiyama, Yoshihiro Akiyama
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Patent number: 4551394Abstract: Localized epitaxial growth of GaAs from a silicon monocrystalline substrate to provide a three-dimensional Si-GaAs structure and method. The silicon has an insulating layer deposited thereover and a window is opened through the layer to expose a small area of the underlying silicon from which silicon is epitaxially grown until the window is nearly full whereupon a thin buffer layer such as germanium is epitaxially grown over the epi-silicon to fill the window. Al.sub.x Ga.sub.1-x As (where x.gtoreq.0) is then locally epitaxially grown from the buffer layer and it grows laterally as well as vertically to cover the surrounding insulating layer surface and provide a site for high frequency electronics.Type: GrantFiled: November 26, 1984Date of Patent: November 5, 1985Assignee: Honeywell Inc.Inventors: Regis J. Betsch, Michael S. Liu, Obert N. Tufte
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Patent number: 4548658Abstract: A method is disclosed for growing an epitaxial layer composed of semiconductor material belonging to the cubic crystal system on a substrate, where the lattice constant of the epitaxial layer is graded from an initial lattice constant adjacent to the substrate to a final lattice constant on the surface of the epitaxial layer. Growth surfaces are formed on the substrate, and the epitaxial layer is grown as its lattice constant changes from the initial lattice constant to the final lattice constant.Type: GrantFiled: January 30, 1985Date of Patent: October 22, 1985Inventor: Melvin S. Cook
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Patent number: 4532694Abstract: Integration of optoelectronic component and electronic components in a planar surface of a semi-insulating substrate such as gallium arsenide. A depression is etched into the planar surface to contain the transverse junction stripe laser structure which is grown by epitaxial layers. In the resulting structure the surface of the epitaxial layers forms a portion of the planar surface, thus placing the electrical and optical elements on or at the planar surface to facilitate fabrication and testing.Type: GrantFiled: June 27, 1983Date of Patent: August 6, 1985Assignee: Honeywell Inc.Inventor: Robert M. Kolbas
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Patent number: 4529455Abstract: A molecular beam epitaxy method of growing Ge.sub.x Si.sub.1-x films on silicon substrate is described.Type: GrantFiled: October 28, 1983Date of Patent: July 16, 1985Assignee: AT&T Bell LaboratoriesInventors: John C. Bean, Leonard C. Feldman, Anthony T. Fiory
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Patent number: H29Abstract: A TUNNETT (tunneling transit time) electronic device comprising a very thin injector uniformly doped at a high concentration, a thin drift region of lower doping of the same semiconductivity type, and a collector of high doping of the same semiconductivity type. A Schottky barrier is formed by placing a metal electrode on the injector and an ohmic contact may be made on the collector. In a preferred embodiment the injector is made of Ge grown on the drift region by vacuum epitaxy. The drift region is preferably GaAs grown by epitaxy on a GaAs collector.Type: GrantFiled: January 4, 1983Date of Patent: March 4, 1986Assignee: The Government of the United StatesInventors: Aristos Christou, John E. Davey