Reversing Current Or Voltage Patents (Class 205/103)
  • Publication number: 20110256356
    Abstract: Variable property deposit, at least partially of fine-grained metallic material, optionally containing solid particulates dispersed therein, is disclosed. The electrodeposition conditions in a single plating cell are suitably adjusted to once or repeatedly vary at least one property in the deposit direction. In one embodiment denoted multidimension grading, property variation along the length and/or width of the deposit is also provided. Variable property metallic material deposits containing at least in part a fine-grained microstructure and variable property in the deposit direction and optionally multidimensionally, provide superior overall mechanical properties compared to monolithic fine-grained (average grain size: >20 micron) or entirely amorphous metallic material deposits.
    Type: Application
    Filed: September 25, 2008
    Publication date: October 20, 2011
    Applicant: Integran Technologies, Inc.
    Inventors: Klaus Tomantschger, Glenn Hibbard, Gino Palumbo, Iain Brooks, Jonathan McCrea, Fred Smith
  • Publication number: 20110198227
    Abstract: Disclosed is a solution for an electrochemical process, the solution containing a sulfonic acid and having a low concentration of sulfur compounds, either low or high valence, that are susceptible to reduction and which is intended for use in electrodeposition, batteries, conductive polymers and descaling processes.
    Type: Application
    Filed: March 23, 2011
    Publication date: August 18, 2011
    Applicant: Arkema Inc.
    Inventors: Nicholas M. Martyak, Martin Nosowitz, Gary S. Smith, Patrick Kendall Janney, Jean-Marie Ollivier
  • Publication number: 20110155579
    Abstract: A method of depositing contiguous, conformal submonolayer-to-multilayer thin films with atomic-level control is described. The process involves the use of underpotential deposition of a first element to mediate the growth of a second material by overpotential deposition. Deposition occurs between a potential positive to the bulk deposition potential for the mediating element where a full monolayer of mediating element forms, and a potential which is less than, or only slightly greater than, the bulk deposition potential of the material to be deposited. By cycling the applied voltage between the bulk deposition potential for the mediating element and the material to be deposited, repeated desorption/adsorption of the mediating element during each potential cycle can be used to precisely control film growth on a layer-by-layer basis. This process is especially suitable for the formation of a catalytically active layer on core-shell particles for use in energy conversion devices such as fuel cells.
    Type: Application
    Filed: June 23, 2009
    Publication date: June 30, 2011
    Applicant: BROOKHAVEN SCIENCE ASSOCIATES
    Inventors: Jia Xu Wang, Radoslav R. Adzic
  • Publication number: 20110132765
    Abstract: An electroplating bath and a process for electrodepositing a crystalline chromium deposit on a substrate, in which the electroplating bath comprising trivalent chromium and a source of divalent sulfur, and substantially free of hexavalent chromium; immersing a substrate in the electroplating bath; and applying an electrical current to deposit a crystalline chromium deposit on the substrate, wherein the chromium deposit is crystalline as deposited, and/or has a lattice parameter of 2.8895+/?0.0025 ?, and/or the crystalline chromium deposit has a {111} preferred orientation.
    Type: Application
    Filed: February 14, 2011
    Publication date: June 9, 2011
    Inventors: Craig V. Bishop, Agnes Rousseau, Zoltan Mathe
  • Publication number: 20110115167
    Abstract: A structured chromium solids particles layer with a network of cracks in which solids particles are embedded, wherein the crack density is 10-250 per mm, the particle size of the solids particles lies in the range of from 0.01-10 ?m, the proportion of solids particles in the overall layer is 1-30 vol.-% and the chromium solids particles layer has a microstructure with depressions in the surface of the layer, wherein the proportion of the surface area accounted for by the depressions is 5-80%. A method for producing the structured chromium solids particles layer on a workpiece includes introducing the workpiece into an electrolyte containing a Cr(VI) compound and electrolytically depositing a chromium layer at a current density of 20-100 A/dm2 and a current yield of 12% or less and then reversing the current direction wherein the solid particles are embedded within the network of cracks.
    Type: Application
    Filed: January 22, 2009
    Publication date: May 19, 2011
    Applicant: FEDERAL-MOGUL BURSCHEID GMBH
    Inventors: Rudolf Linde, Stefan Duerdoth
  • Patent number: 7850836
    Abstract: An initial pulse current cycle is supplied to at least one through-hole via. The pulse current cycle includes a forward pulse current. The magnitude of the forward pulse current is lower than the magnitude of the reverse pulse current. A corresponding forward and reverse current density is generated across the via causing conductive material to be deposited within the via, thereby reducing the effective aspect ratio of the via. At least one subsequent pulse current cycle is supplied. The magnitudes of the forward and reverse pulse currents of the subsequent pulse current cycle are determined in relation to the reduced effective aspect ratio. A subsequent corresponding forward and reverse current density is generated across the through-hole via causing conductive material to be deposited within the via, thereby further reducing the effective aspect ratio of the via.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: December 14, 2010
    Assignee: Nanyang Technological University
    Inventors: Pradeep Dixit, Jianmin Miao
  • Publication number: 20100307925
    Abstract: There is provided a method of well filling copper in a conductivity-rendered non-through hole having an aspect ratio (depth/hole diameter) of 5 or more on a substrate in a short period of time, and the method comprises using an acidic copper plating bath comprising a water-soluble copper salt, sulfuric acid, chlorine ion, a brightener and a copolymer of diallylamines and sulfur dioxide and filling copper in the non-through hole by periodic current reversal copper plating.
    Type: Application
    Filed: May 18, 2010
    Publication date: December 9, 2010
    Applicants: OSAKA PREFECTURE UNIVERSITY PUBLIC CORPORATION, NITTO BOSEKI CO., LTD.
    Inventors: Kazuo KONDO, Takeyasu Saito, Naoki Okamoto, Masaru Bunya, Minoru Takeuchi
  • Patent number: 7837841
    Abstract: Electrochemical plating (ECP) apparatuses with auxiliary cathodes to create uniform electric flux density. An ECP apparatus for electrochemical deposition includes an electrochemical cell with an electrolyte bath for electrochemically depositing a metal on a substrate. A main cathode and an anode are disposed in the electrolyte bath to provide a main electrical field. A substrate holder assembly holds a semiconductor wafer connecting the cathode. An auxiliary cathode is disposed outside the electrochemical cell to provide an auxiliary electrical field such that a flux line density at the center region of the substrate holder assembly substantially equals that at the circumference of the substrate holder assembly.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: November 23, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kei-Wei Chen, Mu-Han Cheng, Jian-Sin Tsai, Ying-Lang Wang
  • Publication number: 20100116675
    Abstract: Electrodeposition baths, systems and methods are provided. In some embodiments, the baths, systems and methods are used to deposit metal alloy coatings.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 13, 2010
    Applicant: Xtalic Corporation
    Inventors: Glenn Sklar, John Cahalen, Nazila Dadvand, Alan C. Lund
  • Publication number: 20090308755
    Abstract: The invention relates to an electrolyte for the electrodeposition of aluminium from aprotic solvents containing a compound of the formula: N(R1)4X.(m-n-o)Al(C2H5)3.nAlR23oAlR33, wherein R1 is a C1 to C4 alkyl group, X is F, Cl or Br, m is equal to 1 to 3, preferably 1.7 to 2.3, n is equal to 0.0 to 1.5, preferably 0.0 to 0.6, o is equal to 0.0 to 1.5, preferably 0.0 to 0.6, R2, R3 is a C1 or C3 to C6 alkyl group, wherein R2 is unequal to R3, in an organic solvent. A further object of the invention is a method for producing the electrolyte, a method for coating and the coated material parts.
    Type: Application
    Filed: October 16, 2007
    Publication date: December 17, 2009
    Applicant: ALUMINAL OBERFLACHENTECHNIK GMBH & CO. KG
    Inventors: Hans De Vries, Matthias Hartel
  • Publication number: 20090283410
    Abstract: Coated articles and related methods are described. In some cases, the coated articles may exhibit high strength, hardness, brightness, abrasion resistance, corrosion resistance, and other desirable structural and functional properties. In some embodiments, the coatings may include an alloy, such as a nickel-tungsten alloy and/or metal oxides.
    Type: Application
    Filed: May 14, 2008
    Publication date: November 19, 2009
    Applicant: Xtalic Corporation
    Inventors: Glenn Sklar, Alan Lai, Alan C. Lund
  • Publication number: 20090236230
    Abstract: The present invention relates to a galvanic process for filling through-holes with metals. The process is particularly suitable for filling through-holes of printed circuit boards with copper.
    Type: Application
    Filed: August 30, 2005
    Publication date: September 24, 2009
    Inventors: Bert Reents, Thomas Pliet, Bernd Roelfs, Toshiya Fujiwara, Rene Wenzel, Markus Youkhanis, Soungsoo Kim
  • Publication number: 20090223827
    Abstract: Pulse reverse electrolysis of acid copper solutions is used for applying copper to printing cylinders, especially gravure printing cylinders. The plating composition generally comprising copper ions, counter ions, chloride ions, a polyalkylene glycol, and a bath-soluble divalent sulfur compound. The benefits include an improved thickness distribution of the copper electrodeposited on the plated article, reduced metal waste, reduced plating times and increased production capacity.
    Type: Application
    Filed: May 21, 2009
    Publication date: September 10, 2009
    Inventors: Roderick D. Herdman, Trevor Pearson, Ernest Long, Alan Gardner
  • Patent number: 7544282
    Abstract: Disclosed are a method and a device for filling material separations on the surface. In methods known in prior art, which are used for filling material separations, the substrate is often influenced in a negative manner by high processing temperatures and dissimilar additives. The inventive method overcomes said disadvantage, taking place at low temperatures and allowing the material separation to be completely filled without using dissimilar substances.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: June 9, 2009
    Assignee: Siemens Aktiengesellschaft
    Inventors: Marc De Vogelaere, Ursus Krüger, Daniel Körtvelyessy, Ralph Reiche
  • Patent number: 7501050
    Abstract: A method of coating a carbon article with a metal by cyclic voltammetrically electrodepositing the metal on the carbon article, thereby forming a metal coating on the carbon article and the metal-coated carbon article made by the method. A metal-coated carbon article having a carbon article and a metal coating disposed on an exterior surface of the carbon article, the coating being present in an amount less than about 0.1 mg/cm2.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: March 10, 2009
    Assignee: Northern Illinois University
    Inventors: Rathindra N. Bose, Anima B. Bose
  • Publication number: 20080283404
    Abstract: A method for manufacturing a semiconductor device is provided which includes performing an electroplating step to fill concavities formed on a substrate. The electroplating step further includes: performing a first electroplating step; performing a first reverse bias step; performing a second electroplating step; performing a second reverse bias step; and a third electroplating step. The polarity of the first and the second reverse bias steps is different from that of the first electroplating step. A difference between the third current density and the fourth current density is larger than a difference between the first current density and the second current density.
    Type: Application
    Filed: May 12, 2008
    Publication date: November 20, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Akira FURUYA, Shinsuke Kozumi, Koji Arita
  • Patent number: 7425255
    Abstract: Bipolar wave current, with both positive and negative current portions, is used to electrodeposit a nanocrystalline grain size deposit. Polarity Ratio is the ratio of the absolute value of the time integrated amplitude of negative polarity current and positive polarity current. Grain size can be precisely controlled in alloys of two or more chemical components, at least one of which is a metal, and at least one of which is most electro-active. Typically, although not always, the amount of the more electro-active material is preferentially lessened in the deposit during times of negative current. The deposit also exhibits superior macroscopic quality, being relatively crack and void free.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: September 16, 2008
    Assignee: Massachusetts Institute of Technology
    Inventors: Andrew J. Detor, Christopher A. Schuh
  • Publication number: 20080217180
    Abstract: The invention relates to a surface comprising a microstructure that reduces adhesion and to a method for producing said microstructure. Microstructures of this type that reduce adhesion are known and are used, for example, to configure self-cleaning surfaces that us the Lotus effect. According to the invention, the surface is produced electrochemically by means of reverse pulse plating, the known microstructure being first produced and a nanostructure that is overlaid on the microstructure is produced at the same time or in a subsequent step. To achieve this for example, the pulse length of the current pulse that is used during the reverse pulse plating lies in the millisecond range and has a pulse length ratio greater than 1:3. The microstructure that has been produced, consisting of peaks and troughs is then overlaid with peaks and troughs of a smaller size order belonging to the nanostructure.
    Type: Application
    Filed: August 8, 2005
    Publication date: September 11, 2008
    Applicant: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Christian Doye, Ursus Kruger, Manuela Schneider
  • Patent number: 7381318
    Abstract: Disclosed herein are a biaxially textured pure metal or alloy layer deposited by electroplating process on the surface of a single-crystalline or quasi-single-crystalline metal substrate, and a method for manufacturing the biaxially textured pure metal or alloy layer.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: June 3, 2008
    Assignee: Korea Institute of Machinery and Materials
    Inventors: Jai-Moo Yoo, Young-Kuk Kim, Jae-Woong Ko, Kyu-Hwan Lee, Do-Yon Chang
  • Patent number: 7374654
    Abstract: A method of making an organic memory cell which comprises two electrodes with a controllably conductive media between the two electrodes is disclosed. The present invention involves providing a dielectric layer having formed therein one or more first electrode pads; removing a portion of the first electrode pad to form a recessed area on top of the pads and in the dielectric layer using reverse electroplating; forming a controllably conductive media over the first electrode pad in the recessed area; and forming a second electrode over the conductive media. The controllably conductive media contains an organic semiconductor layer and a passive layer.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: May 20, 2008
    Assignee: Spansion LLC
    Inventors: Mark S. Chang, Sergey D. Lopatin, Ramkumar Subramanian
  • Patent number: 7329334
    Abstract: Pulse reverse electrolysis of acid copper solutions is used for applying copper deposits of a controlled hardness for applications such as producing printing cylinders. The benefits include improved production capacity. Hardness of the deposit is controlled by varying at least one factor selected from the group consisting of (i) cathodic pulse time, (ii) anodic pulse time, (iii) cathodic pulse current density, and (iv) anodic pulse current density. Preferably the ratio of cathodic pulse time to anodic pulse time is varied.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: February 12, 2008
    Inventors: Roderick D. Herdman, Trevor Pearson, Ernest Long, Alan Gardner
  • Patent number: 7323095
    Abstract: A method and apparatus is provided for depositing and planarizing a material layer on a substrate. In one embodiment, an apparatus is provided which includes a partial enclosure, a permeable disc, a diffuser plate and optionally an anode. A substrate carrier is positionable above the partial enclosure and is adapted to move a substrate into and out of contact or close proximity with the permeable disc. The partial enclosure and the substrate carrier are rotatable to provide relative motion between a substrate and the permeable disc. In another aspect, a method is provided in which a substrate is positioned in a partial enclosure having an electrolyte therein at a first distance from a permeable disc. A current is optionally applied to the surface of the substrate and a first thickness is deposited on the substrate. Next, the substrate is positioned closer to the permeable disc. During the deposition, the partial enclosure and the substrate are rotated relative one another.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: January 29, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Yung Hsu, Liang-Yuh Chen, Ratson Morad, Daniel A. Carl, Sasson Somekh
  • Patent number: 7323094
    Abstract: An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that plates on electrical current density modifier portions (364) of structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: January 29, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cindy Reidsema Simpson, Matthew T. Herrick, Gregory S. Etherington, James Derek Legg
  • Patent number: 7264704
    Abstract: It is described an electrolysis cell wherein the anodic dissolution of metals is carried out, in particular of metals characterised by a relatively high oxidation potential, such as copper, or metals with high hydrogen overpotential, for example tin, aimed at restoring both the concentration of said metals, and the pH in galvanic baths used in electroplating processes with insoluble anodes. The cell of the invention comprises an anodic compartment, wherein the metal to be dissolved acts as a consumable anode, and a cathodic compartment, containing a cathode for hydrogen evolution, separated by a cation-exchange membrane. The coupling of the cell of the invention with the electroplating cell allows a strong simplification of the overall process and a sensible reduction in the relevant costs.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: September 4, 2007
    Assignee: De Nora Elettrodi S.p.A.
    Inventors: Ulderico Nevosi, Paolo Rossi
  • Patent number: 7254885
    Abstract: A method is used for fabricating sliders for use in a disc drive actuation system, the sliders having bonds pads formed on either a top surface or side faces of the slider. The method comprises providing a substrate having a top surface. Trenches are formed in the substrate and filled with a bond pad material to form slider bond pads. Excess bond pad material is removed from the trenches such that the slider bond pads are flush with the top surface of the substrate. A transducer is fabricated on the top surface of the substrate. Finally, the slider bond pads are exposed.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: August 14, 2007
    Assignee: Seagate Technology, LLC
    Inventors: Roger L. Hipwell, Jr., Wayne A. Bonin, Kyle M. Bartholomew, John R. Pendray, Zine-Eddine Boutaghou
  • Patent number: 7200920
    Abstract: The substrate (2) containing the via-hole (3) is inserted into an electrophoretic cell (1) and an electrode (6) (the “first electrode”) is placed on top of a first orifice of the via-hole(s) (3), to be implemented with electrical component(s), so that the electrode (6) totally covers the first orifice. Electrically charged either conductive and/or non-conductive particles are provided by immersing the volume of the via-hole(s) (3) in a conductive medium (17) consisting of the electrically charged particles. An electric field is created between the first electrode (6) and a second electrode (4) through the via-hole(s) (3) and the conductive medium (17) and the electrically charged particles are precipitated on the inner surface of the first electrode (6) that is directed to the second orifice of the via-hole(s) (3), until a desired portion of the volume of the via-hole(s) (3) is filled with a first layer of the charged particles having a desired thickness.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: April 10, 2007
    Inventor: Israel Schuster
  • Patent number: 7150818
    Abstract: A process for electrochemical deposition of tantalum on an article in an inert, non-oxidizing atmosphere, or under vacuum, in a molten electrolyte containing tantalum ions, comprising the steps of: immersing the article into the molten electrolyte heated to a working temperature, passing an electric current through the electrolyte to thereby deposit a tantalum coating on the article, wherein the process of tantalum deposition at least in an initial phase deposits pure ?-tantalum.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: December 19, 2006
    Assignee: Danfoss A/S
    Inventors: John Christensen, Erik Christensen
  • Patent number: 6960370
    Abstract: Medical devices that include oxidizable portions can be plated after a two step activation process that includes successive applications of two aqueous solutions of ammonium bifluoride. Once plated, such materials can be soldered using conventional solders and fluxes. Medical devices can be assembled by soldering together plated materials. Oxidizable materials can be plated with radiopaque materials to yield medical devices that are more visible to fluoroscopy.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: November 1, 2005
    Assignee: SciMed Life Systems, Inc.
    Inventors: Vittorino Monni, Verivada Chandrasekaran, Outhay Voraphet
  • Patent number: 6946065
    Abstract: Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: September 20, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Vijay Bhaskaran, Evan E. Patton, Robert L. Jackson, Jonathan Reid
  • Patent number: 6919011
    Abstract: A method of electroplating an object includes providing a electroplating bath solution with one or more anodes therein, disposing an object to be electroplated in the bath, and passing a complex current waveform between the anode nodes and the object. The waveform is a cyclic alternating type having two portions, a positive triangular shaped portion including one or more spikes and a negative portion. The method further includes vibrating the object and/or agitating the bath solution.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: July 19, 2005
    Assignee: The Hong Kong Polytechnic University
    Inventors: Kang Cheung Chan, Kam Chuen Yung, Tai Men Yue
  • Patent number: 6913680
    Abstract: A method and associated apparatus includes depositing metal on a plating surface of an object immersed in an electrolyte solution prior to bulk deposition on the plating surface. In one aspect, the method further includes applying a voltage between an anode and the plating surface to enhance the concentration of metal ions in the electrolyte solution that is contained in a feature on the plating surface prior to the bulk deposition on the plating surface.
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: July 5, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Bo Zheng, Hougong Wang, Girish Dixit, Fusen Chen
  • Patent number: 6893550
    Abstract: The present invention relates to a copper electroplating bath composition and method of using it for microelectronic device fabrication. In particular, the present invention relates to copper electroplating in the fabrication of interconnect structures in semiconductor devices. By use of the inventive copper electroplating bath composition, the incidence of voids in the interconnect structures is reduced.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: May 17, 2005
    Assignee: Intel Corporation
    Inventors: Valery Dubin, Kimin Hong, Nate Baxter
  • Patent number: 6881318
    Abstract: A method for depositing a metal on a substrate is provided. The metal is deposited by sequentially applying a electrodeposition pulse followed by an electrodissolution pulse to the substrate. After each electrodissolution pulse an before the next electrodeposition pulse there is provided at least one time interval of zero electrical voltage or current, also known as an “off-time”, between the pulses. The first two electrodeposition pulses should preferably have the same time durations. Thereafter, the time durations of subsequent electrodeposition pulses are gradually decreased to provide a void-free and seam-free deposition of metal in high aspect ratio features.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: April 19, 2005
    Assignee: Applied Materials, Inc.
    Inventors: H. Peter W. Hey, Yezdi Dordi
  • Patent number: 6878259
    Abstract: A smooth layer of a metal is electroplated onto a microrough electrically conducting substrate by immersing the substrate and a counterelectrode in an electroplating bath of the metal to be electroplated and passing a modulated reversing electric current between the electrodes. The current contains pulses that are cathodic with respect to said substrate and pulses that are anodic with respect to said substrate. The cathodic pulses have a duty cycle less than about 50% and said anodic pulses have a duty cycle greater than about 50%, the charge transfer ratio of the cathodic pulses to the anodic pulses is greater than one, and the frequency of said pulses ranges from about 10 Hertz to about 12000 Hertz. The plating bath is substantially devoid of levelers and may be devoid of brighteners.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: April 12, 2005
    Assignee: Faraday Technology Marketing Group, LLC
    Inventors: E. Jennings Taylor, Chengdong Zhou, Jenny J. Sun
  • Patent number: 6875332
    Abstract: The present invention relates to a to-be-mounted electronic component to which functional alloy plating using a bonding material for mounting is applied with a substitute bonding material for solder (tin-lead alloy), and aims at providing alloy plating which has been put to a practical use in such a way that the function of existing alloy plating of this type has been significantly improved to eliminate toxic plating from various kinds of electronic components for use in electronic devices so that it is useful in protecting the environment.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: April 5, 2005
    Assignee: Nishihara Rikoh Corporation
    Inventor: Masaaki Ishiyama
  • Patent number: 6863793
    Abstract: A continuous layer of a metal is electrodeposited onto a substrate having both hydrodynamically inaccessible recesses and hydrodynamically accessible recesses on its surface by a twostep process in which the hydrodynamically inaccessible recesses are plated using a pulsed reversing current with cathodic pulses having a duty cycle of less than about 50% and anodic pulses having a duty cycle of greater than about 50% and the hydrodynamically accessible recesses are then plated using a pulsed reversing current with cathodic pulses having a duty cycle of greater than about 50% and anodic pulses having a duty cycle of less than about 50%.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: March 8, 2005
    Assignee: Faraday Technology Marketing Group, LLC
    Inventors: E. Jennings Taylor, Jenny J. Sun, Maria E. Inman
  • Patent number: 6863794
    Abstract: A method of forming a metal layer on a substrate is disclosed. The metal layer is formed using a combined electrochemical plating/electrochemical mechanical polishing (ECP/EMP) process. In the ECP/EMP process, the metal layer is deposited on the substrate by contacting the substrate with a porous pad and then alternately applying a first electrical potential and a second electrical potential to an electrolyte plating solution. The first electrical potential functions to deposit metal on the substrate while the second electrical potential functions to remove metal from topographic portions thereof.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: March 8, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Stan Tsai, Shijian Li
  • Patent number: 6855240
    Abstract: A cobalt-iron alloy film having saturation magnetization of at least about 2.30 Telsa. The film alloy includes about 55 wt % to about 75 wt. % iron and the remainder cobalt. The film is made by a process in which the film is electrodeposited from an aqueous medium which includes one or more ferrous salts, one or more cobaltous salts, a buffer having a pKa of about 6 to about 8, at least one carboxylic acid having a pKa of between about 3.5 and about 5.5, an aromatic sulfinic acid or its salt and optionally, a halide salt and/or a surfactant. The alloy film is useful as a write head in magnetic recording.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: February 15, 2005
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Emanuel Israel Cooper, Thomas Edward Dinan, Lubomyr Taras Romankiw, Hong Xu
  • Patent number: 6852208
    Abstract: Deposition of conductive material on or removal of conductive material from a workpiece frontal side of a semiconductor workpiece is performed by providing an anode having an anode area which is to face the workpiece frontal side, and electrically connecting the workpiece frontal side with at least one electrical contact, outside of the anode area, by pushing the electrical contact and the workpiece frontal side into proximity with each other. A potential is applied between the anode and the electrical contact, and the workpiece is moved with respect to the anode and the electrical contact. Full-face electroplating or electropolishing over the workpiece frontal side surface, in its entirety, is thus permitted.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: February 8, 2005
    Assignee: NuTool, Inc.
    Inventors: Jalal Ashjaee, Boguslaw Nagorski, Bulent M. Basol, Homayoun Talieh, Cyprian Uzoh
  • Patent number: 6835294
    Abstract: Electrolytic copper plating methods are provided, wherein copper is electrolytically deposited on a substrate, and the electrolytic copper plating solution supplied to the electrolytic copper plating is subjected to dummy electrolysis using an insoluble anode. The method described above can maintain and restore the electrolytic copper plating solution so as to maintain satisfactory appearance of plated copper, fineness of deposited copper film, and via-filling.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: December 28, 2004
    Assignee: Shipley Company, L.L.C.
    Inventors: Hideki Tsuchida, Masaru Kusaka, Shinjiro Hayashi
  • Patent number: 6827833
    Abstract: The interior of cavities and through-holes in electrically conductive substrates having high-aspect ratios of 8:1 or greater can be electroplated with a uniform layer of metal on their interior surfaces by using a pulse reverse voltage waveform having a pulse train of long cathodic pulses followed by short anodic pulses even in the absence of conventional additives such as levelers and brighteners.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: December 7, 2004
    Assignee: Faraday Technology Marketing Group, LLC
    Inventors: E. Jennings Taylor, Jenny J. Sun
  • Patent number: 6811675
    Abstract: This invention employs a novel approach to the copper metallization of a workpiece, such as a semiconductor workpiece. In accordance with the invention, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: November 2, 2004
    Assignee: Semitool, Inc.
    Inventor: Linlin Chen
  • Patent number: 6808612
    Abstract: A method and apparatus for electrochemically depositing a metal into a high aspect ratio structure on a substrate are provided. In one aspect, a method is provided for processing a substrate including positioning a substrate having a first conductive material disposed thereon in a processing chamber containing an electrochemical bath, depositing a second conductive material on the first conductive material as the conductive material is contacted with the electrochemical bath by applying a plating bias to the substrate while immersing the substrate into the electrochemical bath, and depositing a third conductive material in situ on the second conductive material by an electrochemical deposition technique to fill the feature. The bias may include a charge density between about 20 mA*sec/cm2 and about 160 mA*sec/cm2. The electrochemical deposition technique may include a pulse modulation technique.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: October 26, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Peter Hey, Byung-Sung Leo Kwak
  • Publication number: 20040195105
    Abstract: Disclosed herein are a biaxially textured pure metal or alloy layer deposited by electroplating process on the surface of a single-crystalline or quasi-single-crystalline metal substrate, and a method for manufacturing the biaxially textured pure metal or alloy layer. Specifically, the biaxially textured pure metal or alloy layer is deposited by electroplating process on the surface of a pure metal or alloy substrate having single-crystalline or quasi-single-crystalline orientation. The biaxially textured pure metal or alloy layer has a misorientation on the c-axis of 4° or less and a misorientation on the plane formed by the a-axis and b-axis of 5.2° or less in which the misorientation on the c-axis is determined by a Full Width at Half Maximum of peaks on the &thgr;-rocking curve and the misorientation on the plane formed by the a-axis and b-axis is determined by a Full Width at Half Maximum of peaks on the &PHgr;-scan.
    Type: Application
    Filed: June 27, 2003
    Publication date: October 7, 2004
    Applicant: Korea Institute of Machinery and Materials
    Inventors: Jai-Moo Yoo, Young-Kuk Kim, Jae-Woong Ko, Kyu-Hwan Lee, Do-Yon Chang
  • Publication number: 20040188261
    Abstract: Medical devices that include oxidizable portions can be plated after a two step activation process that includes successive applications of two aqueous solutions of ammonium bifluoride. Once plated, such materials can be soldered using conventional solders and fluxes. Medical devices can be assembled by soldering together plated materials. Oxidizable materials can be plated with radiopaque materials to yield medical devices that are more visible to fluoroscopy.
    Type: Application
    Filed: March 27, 2003
    Publication date: September 30, 2004
    Applicant: SCIMED LIFE SYSTEMS, INC.
    Inventors: Vittorino Monni, Verivada Chandrasekaran, Outhay Voraphet
  • Patent number: 6797145
    Abstract: An electrochemical processing method is provided for forming a current carrying device for semiconductor chip packaging and similar applications. The method comprises selecting sections of a substrate to carry current wherein a selected section is at least partly covered with a voltage switchable dielectric material, rendering the voltage switchable dielectric material conductive, and electrochemically forming a current carrying material directly on the voltage switchable dielectric material. The voltage switchable dielectric material can have a characteristic voltage, such that when a voltage having a magnitude exceeding the characteristic voltage is applied to the voltage switchable dielectric material, the voltage switchable dielectric material switches from a dielectric material to a conductive material. When conductive, the voltage switchable dielectric material is amenable to electrochemical processing such as electroplating.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: September 28, 2004
    Inventor: Lex Kosowsky
  • Patent number: 6793797
    Abstract: A method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal including a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: September 21, 2004
    Assignee: Taiwan SEmiconductor Manufacturing Co., Ltd
    Inventors: Shih-Wei Chou, Ming-Hsing Tsai, Winston Shue, Mong-Song Liang
  • Patent number: 6793795
    Abstract: A method is disclosed for electrolytically forming conductor structures from highly pure copper on surfaces of semiconductor substrates, which surfaces are provided with recesses, when producing integrated circuits. The method includes the steps of coating the surfaces of the semiconductor substrates with a full-surface basic metal layer in order to achieve sufficient conductance for the electrolytic depositions, depositing full-surface deposition of copper layers of uniform layer thickness on the basic metal layer by an electrolytic metal deposition method, and structuring the copper layer.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: September 21, 2004
    Assignee: Atotech Deutschland GmbH
    Inventors: Heinrich Meyer, Andreas Thies
  • Patent number: 6793796
    Abstract: Electroplating methods using an electroplating bath containing metal ions and a suppressor additive, an accelerator additive, and a leveler additive, together with controlling the current density applied to a substrate, avoid defects in plated films on substrates having features with a range of aspect ratios, while providing good filling and thickness distribution. The methods include, in succession, applying DC cathodic current densities optimized to form a conformal thin film on a seed layer, to provide bottom-up filling, preferentially on features having the largest aspect ratios, and to provide conformal plating of all features and adjacent field regions. Including a leveling agent in the electroplating bath produces films with better quality after subsequent processing.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: September 21, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, David Smith, Steven T. Mayer, Jon Henri, Sesha Varadarajan
  • Patent number: RE40218
    Abstract: The invention provides an apparatus and a method for achieving reliable, consistent metal electroplating or electrochemical deposition onto semiconductor substrates. More particularly, the invention provides uniform and void-free deposition of metal onto metal seeded semiconductor substrates having sub-micron, high aspect ratio features. The invention provides an electrochemical deposition cell comprising a substrate holder, a cathode electrically contacting a substrate plating surface, an electrolyte container having an electrolyte inlet, an electrolyte outlet and an opening adapted to receive a substrate plating surface and an anode electrically connect to an electrolyte. Preferably, a vibrator is attached to the substrate holder to vibrate the substrate in at least one direction, and an auxiliary electrode is disposed adjacent the electrolyte outlet to provide uniform deposition across the substrate surface.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: April 8, 2008
    Inventor: Uziel Landau