Utilizing Specified Mask Material Patents (Class 205/135)
  • Patent number: 10822711
    Abstract: A final injection molded assembly and process for making same that eliminates paint and reduces areas of wasted chrome material. The final injection molded assembly has at least one first injection molded part of a non-plateable first material, at least one overmolded part of plateable second material, at least one pathway through the assembly and integrated features operable for selectively applying an electric current. The pathway creates a predetermined surface path arrangement for applying chrome to desired predetermined plateable areas. A shot of each material is delivered to an injection molding rotary device to produce the injection molded assembly which is then affixed to a chroming process line where electric current is applied. As the electric current is applied and chrome is delivered only the plateable second material will accept the chrome.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: November 3, 2020
    Assignee: Magna International Inc.
    Inventors: Ryan R. Case, Michael A. West, Lastawork Araya
  • Patent number: 10661499
    Abstract: A method for printing a three-dimensional part with an additive manufacturing system, the method comprising generating and printing a planarizing part having a substantially-planar top surface relative to a build plane, and a bottom surface that substantially mirrors a topography of a platen surface, and printing the three-dimensional part over the substantially-planar top surface of the printed planarizing part.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 26, 2020
    Assignee: STRATASYS, INC.
    Inventors: Joseph E. LaBossiere, Michael D. Bosveld, Dominic F. Mannella, William J. Swanson
  • Patent number: 10473204
    Abstract: The present invention discloses a heavy-duty drive axle comprising a reduction gearbox and a drive motor; a differential case is provided within the reduction gearbox; a motor output shaft of the drive motor is linked with a first output shaft and a second output shaft via the differential case; the differential case consists of a differential holder, a connecting pole, a linkage gear and four bevel gears; each bevel gear is meshed with two bevel gears; the bevel gears comprise a first bevel gear, a second bevel gear, a third bevel gear and a fourth bevel gear, the first bevel gear and the second bevel gear are arranged oppositely, and the third bevel gear and the fourth bevel gear are arranged oppositely and sheathed on the connecting pole; the connecting pole is fixed with the differential holder; a cavity is formed within the differential holder; a through hole for fitting with the connecting pole is formed on each of an upper side and a lower side of the differential holder, and a third shaft hole and an
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: November 12, 2019
    Assignee: ZHEJIANG LINIX MOTOR CO., LTD.
    Inventor: Jun Shentu
  • Patent number: 10349836
    Abstract: Disclosed is an optoacoustic probe with a coated transducer assembly. The probe includes a transducer assembly with a multi-layer coating on the active end thereof. The multi-layer coating includes a layer of parylene and at least two layers of metal. In an embodiment, the multi-layer coating includes a layer of nickel, at least one layer of parylene, and a layer of gold.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: July 16, 2019
    Assignee: Seno Medical Instruments, Inc.
    Inventors: Donald G. Herzog, William Ackerman, Justin Casas
  • Patent number: 10151042
    Abstract: A coating forming device for forming a metal coating on a surface of a substrate includes: an anode; a power supply; and a solid electrolyte membrane disposed between the anode and the substrate and contains metal ions. The solid electrolyte membrane includes: a contact surface that is a region contacting a coating-forming region where the metal coating is formed; and a concave portion recessed relative to the contact surface such that, when the contact surface contacts the coating-forming region, the solid electrolyte membrane is not in contact with a portion of the surface of the substrate excluding the coating-forming region. The metal ions are reduced to form the metal coating on the coating-forming region by the power supply applying a voltage between the anode and the substrate.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: December 11, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroki Usui, Hiroshi Yanagimoto, Motoki Hiraoka, Yuki Sato
  • Patent number: 9897912
    Abstract: The present invention provides a color filter film manufacturing method and a color filer film. The color filter film manufacturing method of the present invention includes forming transparent photoresist layers in blue sub-pixel zones and forming first and second recesses respectively in red and green sub-pixel zones and subjecting bottoms thereof to a treatment for hydrophilicity/hydrophobicity. The difference of hydrophilicity/hydrophobicity between the bottoms of the first and second recesses and a surface of the photoresist layer, in combination with altitude differences, makes the red and green quantum dot materials to respectively form red and green quantum dot layers in the first and second recesses through autonomous flowing.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: February 20, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Min Tang
  • Patent number: 9761514
    Abstract: Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventors: Qing Ma, Chuan Hu, Patrick Morrow
  • Patent number: 9664111
    Abstract: A method for filling cooling holes in a component of a gas turbine engine is disclosed. The component may include a plurality of first cooling holes penetrating the wall of the component. The method may comprise the steps of exposing the outer surface of the component, filling the plurality of first cooling holes of the component with a filling agent, curing the filling agent to block the passage of air through the cooling holes, and applying a thermal barrier coating over the surface of the component. The method may further include installing a second plurality of cooling holes, the second plurality of cooling holes penetrating the thermal barrier coating and the wall of the component and allow air to pass therethrough.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: May 30, 2017
    Assignee: UNITED TECHNOLOGIES CORPORATION
    Inventors: William Bogue, Ron I. Prihar
  • Patent number: 9238581
    Abstract: An integrated circuit structure includes a triple-axis accelerometer, which further includes a proof-mass formed of a semiconductor material; a first spring formed of the semiconductor material and connected to the proof-mass, wherein the first spring is configured to allow the proof-mass to move in a first direction in a plane; and a second spring formed of the semiconductor material and connected to the proof-mass. The second spring is configured to allow the proof-mass to move in a second direction in the plane and perpendicular to the first direction. The triple-axis accelerometer further includes a conductive capacitor plate including a portion directly over, and spaced apart from, the proof-mass, wherein the conductive capacitor plate and the proof-mass form a capacitor; an anchor electrode contacting a semiconductor region; and a transition region connecting the anchor electrode and the conductive capacitor plate, wherein the transition region is slanted.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: January 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Hau Wu, Chun-Ren Cheng, Shang-Ying Tsai, Jiou-Kang Lee, Jung-Huei Peng
  • Publication number: 20150056427
    Abstract: A system and a method for selectively coating a substrate includes a removable mask including a magnetic member having a first surface contour shaped to conform to the outside surface of the substrate and a magnetizable member having a second surface contour shaped to conform to the inside surface of the substrate. The method for coating the substrate includes magnetically coupling a removable mask to at least one surface of the substrate; forming a coating of a coating material on the at least one surface of the substrate with the magnetically coupled removable mask using a bath containing the coating material; and selectively decoupling the removable mask from the at least one coated surface to reveal a portion of the coated surface without the coating.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Applicant: Sikorsky Aircraft Corporation
    Inventors: Robert Guillemette, John Bartalotta, Linda Fabian, Gregory C. Papachristos
  • Patent number: 8864966
    Abstract: The invention relates to a coating mask (1) for electrolytically coating the piston ring groove (39) of a piston (38), which is made of an elastically deformable material and has openings (3 to 10) that are arranged axially and are distributed in a uniform manner over the periphery, into which rods (11 to 18) of an expansion device (19) can be introduced, the rods being arranged in a displaceable manner such that the expansion device (19) can increase the radial diameter of the coating mask (1) and also the inner opening (2) so that the piston (38) can be introduced into the inner opening (2). The radial diameter of the coating mask (1) is selected in such a manner that after the reduction of radial diameter of the coating mask (1) and the inner opening, the elastically tensed coating mask (1) presses sealing lips (44, 45) of the coating groove (37) against the piston (38), on both sides of the piston ring groove (39).
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: October 21, 2014
    Assignee: MAHLE International GmbH
    Inventors: Rudolf Bergmann, Christopher Rotsch, Franz Gessler
  • Publication number: 20140238865
    Abstract: Electrochemical fabrication processes and apparatus for producing single layer or multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers includes operations for reducing stress and/or curvature distortion when the structure is released from a sacrificial material which surrounded it during formation and possibly when released from a substrate on which it was formed. Six primary groups of embodiments are presented which are divide into eleven primary embodiments. Some embodiments attempt to remove stress to minimize distortion while others attempt to balance stress to minimize distortion.
    Type: Application
    Filed: February 28, 2014
    Publication date: August 28, 2014
    Inventors: Ananda H. Kumar, Jorge S. Alberron, Adam L. Cohen, Kieun Kim, Michael S. Lockard, Uri Frodis, Dennis R. Smalley
  • Patent number: 8790504
    Abstract: There is provided a method of manufacturing a wiring substrate. The method includes: (a) forming a first resist layer having first openings therein on a first surface of a support plate, forming first plated films in the first openings by an electrolytic plating method, and removing the first resist layer; (b) forming a second resist layer having second openings therein on the first surface of the support plate, forming second plated films in the second openings by an electrolytic plating method, and removing the second resist layer; (c) forming a wiring layer and an insulating layer such that the wiring layer is electrically connected to the first and second plated films; and (d) removing the support plate to expose the first and second plated films.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: July 29, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Kotaro Kodani
  • Publication number: 20140183050
    Abstract: Tin or tin alloy plating liquid with a sufficient plated deposit can be formed in the opening without causing burns on the plated film surface or abnormal deposits, and which has a good via filling effect. When a specific ?,?-unsaturated carbonyl compound is added into the tin or tin alloy plating liquid, the plating liquid with good via filling performance can be obtained, and the deposit which is substantially free of voids and burns or abnormal deposits on the deposit surface are reduced.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Inventors: Hiroki OKADA, Li SHENGHUA, Makoto KONDO
  • Publication number: 20140174941
    Abstract: A method of depositing nano-dots on a substrate includes forming a template on the base, the template defining nano-pores, at least partially filling the nano-pores with a pillar material to define nano-pillars, depositing a dot material on the nano-pillars to define nano-dots on the nano-pillars, and contact printing the substrate with the array of nano-dots.
    Type: Application
    Filed: August 30, 2011
    Publication date: June 26, 2014
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Peter Mardilovich, Qingqiao Wei, Anthony M. Fuller
  • Publication number: 20140140647
    Abstract: A high strength, low friction engineered material includes a low friction material filling interstices of a metal microlattice. The metal typically comprises 5 volume % to 25 volume % and the interstices typically comprise 75 volume % to 95 volume %, based on the total volume of the metal microlattice and the interstices. The low friction material preferably fills 100 volume % of the interstices. The metal microlattice can be formed of a single layer, or multiple layers, for example layers of nickel, copper, and tin. The low friction material is typically a polymer, such as polytetrafluoroethylene (PTFE), polyamide (PAI), polyetheretherketone (PEEK), polyethylene (PE), or polyoxymethylene (POM). The low friction material can also include additive particles to modify the material properties. The engineered material can be used in various automotive applications, for example as a bearing, or non-automotive applications.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 22, 2014
    Applicant: Federal-Mogul Corporation
    Inventor: David Saxton
  • Publication number: 20140120261
    Abstract: A method of forming a tool marking structure includes: a coloring step of coloring a predetermined position of the first protective layer so as to form a marking area with a color layer and forming the first protective layer on a bottom surface of the marking area, and a second-time surface processing step of forming a second protective layer on a non-marking area of the tool and forming the first protective layer on a bottom surface of the second protective layer; wherein the color of the first protective layer is different from that of the second protective layer.
    Type: Application
    Filed: December 13, 2012
    Publication date: May 1, 2014
    Inventor: Leo Shih
  • Publication number: 20140080274
    Abstract: A method of forming a channel layer of an electric device according to an embodiment is provided. First, a conductive substrate including an insulating layer on the substrate is provided. The conductive substrate and a metal to be plated are used as respective electrodes to carry out electroplating within an electrolyte solution. In this case, electrons provided by a tunneling current passing through the insulating layer from the conductive substrate are bonded with ions of the metal within the electrolyte solution to form a metal channel layer on the insulating layer.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: SNU R&DB FOUNDATION
    Inventors: Young June PARK, Seok Ha LEE, Jun Ho CHUN, Yeonkyu CHOI
  • Publication number: 20140014522
    Abstract: Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed.
    Type: Application
    Filed: July 23, 2013
    Publication date: January 16, 2014
    Applicant: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, John Stephen Drewery, Eric G. Webb
  • Publication number: 20140008235
    Abstract: Electrochemical fabrication processes and apparatus for producing multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers including operations for providing coatings of dielectric material that isolate at least portions of a first conductive material from (1) other portions of the first conductive material, (2) a second conductive material, or (3) another dielectric material, and wherein the thickness of the dielectric coatings are thin compared to the thicknesses of the layers used in forming the structures. In some preferred embodiments, portions of each individual layer are encapsulated by dielectric material while in other embodiments only boundaries between distinct regions of materials are isolated from one another by dielectric barriers.
    Type: Application
    Filed: October 22, 2012
    Publication date: January 9, 2014
    Applicant: Microfabrica Inc.
    Inventor: Microfabrica Inc.
  • Publication number: 20130313011
    Abstract: A manufacturing method of an interposed substrate is provided. A photoresist layer is formed on a metal carrier. The photoresist layer has plural of openings exposing a portion of the metal carrier. Plural of metal passivation pads and plural of conductive pillars are formed in the openings. The metal passivation pads cover a portion of the metal carrier exposed by openings. The conductive pillars are respectively stacked on the metal passivation pads. The photoresist layer is removed to expose another portion of the metal carrier. An insulating material layer is formed on the metal carrier. The insulating material layer covers the another portion of the metal carrier and encapsulates the conductive pillars and the metal passivation pads. An upper surface of the insulating material layer and a top surface of each conductive pillar are coplanar. The metal carrier is removed to expose a lower surface of the insulating material layer.
    Type: Application
    Filed: July 9, 2012
    Publication date: November 28, 2013
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Dyi-Chung Hu, Ming-Chih Chen, Tzyy-Jang Tseng
  • Publication number: 20130313122
    Abstract: A method for fabricating a conductive structure of a substrate includes the steps of: providing an insulating substrate having opposite first and second surfaces and forming an insulating adhesive film on the second surface of the insulating substrate; forming at least a through hole penetrating the insulating substrate and the insulating adhesive film and forming a conductive foil on the insulating adhesive film so as to cover the through hole; and forming a shielding material on the conductive foil and the second surface of the insulating substrate and performing an electrochemical deposition process through the conductive foil so as to fill the through hole with a conductive material along a direction towards the first surface of the insulating substrate, thereby preventing the formation of voids in the through hole and hence reducing the overall resistance and preventing a blister effect from occurring.
    Type: Application
    Filed: August 1, 2012
    Publication date: November 28, 2013
    Applicant: Viking Tech Corporation
    Inventors: Shih-Long Wei, Shen-Li Hsiao, Chien-Hung Ho, Yuan-Chiang Lin, Chen-Shen Kuo
  • Patent number: 8580100
    Abstract: Methods of forming a conductive metal layers on substrates are disclosed which employ a seed layer to enhance bonding, especially to smooth, low-roughness or hydrophobic substrates. In one aspect of the invention, the seed layer can be formed by applying nanoparticles onto a surface of the substrate; and the metallization is achieved by electroplating an electrically conducting metal onto the seed layer, whereby the nanoparticles serve as nucleation sites for metal deposition. In another approach, the seed layer can be formed by a self-assembling linker material, such as a sulfur-containing silane material.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: November 12, 2013
    Assignees: Massachusetts Institute of Technology, The Trustees of Boston College, GMZ Energy, Inc.
    Inventors: Hsien-Ping Feng, Gang Chen, Yu Bo, Zhifeng Ren, Shuo Chen, Bed Poudel
  • Patent number: 8535508
    Abstract: A coating method for forming a pattern on a workpiece is provided. First, a workpiece surface is provided. Second, a mask having a shape conforming to a predetermined pattern is provided. Next, the workpiece surface includes a first portion exposed outside and a second portion shielded by the mask. A shielding layer is formed on the exposed first portion of the workpiece surface. The mask is removed from the workpiece to expose the second portion. A coating layer over the shielding layer and the exposed second portion is formed. The coating layer consists of a first part overlaying the shielding layer and a second part overlaying the second portion. The mask is attached onto the coating layer and aligned with the second portion of the workpiece surface. The first part of the coating layer, the shielding layer, and the mask are then removed.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: September 17, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Chung-Pei Wang
  • Publication number: 20130192993
    Abstract: An article is provided, the article including a substrate having a surface with a first wettability characteristic. A nano-structure array is formed on the surface of the substrate to provide a nano-structured surface having a second wettability characteristic. A thin-layer surface coating is formed on the nano-structured surface, the thin-layer surface coating being configured to tune the nano-structured surface to a target wettability characteristic.
    Type: Application
    Filed: October 21, 2010
    Publication date: August 1, 2013
    Inventors: Peter Mardilovich, Anthony M. Fuller, Qingqiao Wei, Rio Rivas, David Kamp
  • Publication number: 20130177738
    Abstract: A method of forming a micro-structure (100, 100?, 100?, 100??) involves forming a multi-layered structure (10) including i) an oxidizable material layer (14) on a substrate (12) and ii) another oxidizable material layer (16) on the oxidizable material layer (14). The oxidizable material layer (14) is formed of an oxidizable material having an expansion coefficient, during oxidation, that is more than 1. The method further involves forming a template (16?), including a plurality of pores (18), from the other oxidizable material layer (16), and growing a nano-pillar (20) inside each pore (18). The nano-pillar (18) has a predefined length (L) that terminates at an end (21). A portion of the template (16?) is selectively removed to form a substantially even plane (23) that is oriented in a position opposed to the substrate (12).
    Type: Application
    Filed: October 21, 2010
    Publication date: July 11, 2013
    Inventors: Peter Mardilovich, Anthony M. Fuller, Qingqiao Wei
  • Patent number: 8475633
    Abstract: Provided is a method for preparing an epoxy substrate having a nanopattern, including: (a) forming a titanium oxide film by anodizing a titanium substrate; (b) obtaining a titanium substrate having a concave shape formed on the surface by removing the titanium oxide film from the titanium substrate on which the titanium oxide film has been formed; (c) coating an epoxy resin onto the titanium substrate on which the concave shape has been formed; and (d) obtaining an epoxy substrate having a nanopattern of convex surfaces by removing the titanium substrate.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: July 2, 2013
    Assignee: BioBud Co., Ltd.
    Inventors: Kwang Hoe Chung, Sung Yu Hong, Hyun Ju Doh, Jin Sub Choi, Jae Hoon Lim, Sung Joong Kim
  • Publication number: 20130161809
    Abstract: A substrate structure, a semiconductor package device and a manufacturing method of substrate structure are provided. The substrate structure comprises a conductive structure comprising a first metal layer, a second metal layer and a third metal layer. The second metal layer is disposed on the first metal layer. The third metal layer is disposed on the second metal layer. Each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface. The first surface of the third metal layer is connected to the second surface of the second metal layer. The surface area of the first surface of the third metal layer is larger than that of the second surface of the second metal layer. A substrate structure, semiconductor package device, and a manufacturing method of substrate structure are provided. The substrate structure includes a conductive structure, comprising a first metal layer, a second metal layer, and a third metal layer.
    Type: Application
    Filed: November 29, 2012
    Publication date: June 27, 2013
    Applicant: ADVANPACK SOLUTIONS PTE LTD.
    Inventor: ADVANPACK SOLUTIONS PTE LTD.
  • Publication number: 20130068506
    Abstract: Disclosed herein are a plating pattern and a method of manufacturing the same. The plating pattern includes: a base substrate; a conductive polymer formed on the base substrate and patterned to be selectively deactivated by having a deactivator added thereto; and a plating layer formed on portions of the conductive polymer except for the deactivated portions.
    Type: Application
    Filed: December 21, 2011
    Publication date: March 21, 2013
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Il Kim, Jong Young Lee, Sang Hwa Kim
  • Publication number: 20130026386
    Abstract: Disclosed is an electrolytic plating method which includes forming plating films 5 and 6 having predetermined thicknesses in a plurality of regions 14 and 15 on a substrate 1. The electrolytic plating method includes arranging a resistive element 4 having ohmic characteristics in at least one of paths through which electrolytic plating currents flow into the plurality of the regions 14 and 15 on the substrate 1, respectively, and simultaneously growing the plating films 5 and 6 in the plurality of the regions 14 and 15 by electrolytic plating. The electrolytic plating method can form the plating films having different or same thicknesses in the plurality of the regions on the substrate.
    Type: Application
    Filed: June 1, 2012
    Publication date: January 31, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Kazushige Utsumi
  • Publication number: 20120222960
    Abstract: Electrochemical fabrication processes and apparatus for producing single layer or multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers includes operations for reducing stress and/or curvature distortion when the structure is released from a sacrificial material which surrounded it during formation and possibly when released from a substrate on which it was formed. Six primary groups of embodiments are presented which are divide into eleven primary embodiments. Some embodiments attempt to remove stress to minimize distortion while others attempt to balance stress to minimize distortion.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 6, 2012
    Inventors: Ananda H. Kumar, Jorge Sotelo Albarran, Adam L. Cohen, Kieun Kim, Michael S. Lockard, Uri Frodis, Dennis R. Smalley
  • Publication number: 20120225251
    Abstract: Lithographic and nanolithographic methods that involve patterning a first compound on a substrate surface, exposing non-patterned areas of the substrate surface to a second compound and removing the first compound while leaving the second compound intact. The resulting hole patterns can be used as templates for either chemical etching of the patterned area of the substrate or metal deposition on the patterned area of the substrate.
    Type: Application
    Filed: May 16, 2012
    Publication date: September 6, 2012
    Inventors: Chad A. Mirkin, Khalid Salaita
  • Publication number: 20120217165
    Abstract: Methods of forming a conductive metal layers on substrates are disclosed which employ a seed layer to enhance bonding, especially to smooth, low-roughness or hydrophobic substrates. In one aspect of the invention, the seed layer can be formed by applying nanoparticles onto a surface of the substrate; and the metallization is achieved by electroplating an electrically conducting metal onto the seed layer, whereby the nanoparticles serve as nucleation sites for metal deposition. In another approach, the seed layer can be formed by a self-assembling linker material, such as a sulfur-containing silane material.
    Type: Application
    Filed: February 24, 2011
    Publication date: August 30, 2012
    Applicants: Massachusetts Institute of Technology, GMZ Energy, Inc., The Trustees of Boston College
    Inventors: Hsien-Ping Feng, Gang Chen, Yu Bo, Zhifeng Ren, Shuo Chen, Bed Poudel
  • Patent number: 8246808
    Abstract: One exemplary embodiment includes a method of selectively electroplating an electrically conductive coating on portions of a first face of a bipolar plate for use in a proton exchange membrane (PEM) fuel cell. The first face of the bipolar plate defines at least one reactant gas flow channel and a plurality of lands adjacent the at least one channel. The electrically conductive coating may be selectively electroplated on a plurality of first portions of the lands leaving second portions of the lands uncoated by the electrically conductive coating.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: August 21, 2012
    Assignee: GM Global Technology Operations LLC
    Inventors: Mahmoud H. Abd Elhamid, Gayatri Vyas Dadheech, Youssef M. Mikhail
  • Publication number: 20120189962
    Abstract: The present invention relates to a method for manufacturing a stamper for injection molding, and more particularly, to a method for manufacturing a stamper for injection molding which can prevent a scratch from forming thereon and has an excellent durability owing to high hardness even after manufacturing of the metal stamper with micro patterns formed thereon is finished. The method for manufacturing a stamper for injection molding includes a pattern forming step for forming a predetermined micro pattern on a substrate, a metal plating step for making metal plating on the substrate to form a stamper having the micro pattern transcribed thereto, a stamper separating step for separating the stamper of the metal plating from the substrate, and a protective layer coating step for coating a protective layer on the stamper for maintaining a mirror surface.
    Type: Application
    Filed: September 6, 2010
    Publication date: July 26, 2012
    Inventors: Young Kyu Kim, Seok Jae Jeong
  • Patent number: 8211595
    Abstract: A metal identification platelet equipped with an identification code, while the identification code comprises a hologram. A method of producing the identification platelet with the identification code, including the following steps: A shield from an electro-insulation material is formed on a shim with a holographic motif. Then, the shim is galvanized in the places not covered by the shield from the electro-insulation material. And the completed metal identification platelets are removed from the shim.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: July 3, 2012
    Assignee: Optaglio, Ltd.
    Inventor: Igor Jermolajev
  • Publication number: 20120121928
    Abstract: Metalized plastic substrates, and methods thereof are provided herein. The method includes providing a plastic substrate having a plurality of accelerators dispersed in the plastic substrate. The accelerators have a formula selected from the group consisting of: CuFe2O4-?, Ca0.25Cu0.75TiO3-?, and TiO2-?, wherein ?, ?, ? denotes oxygen vacancies in corresponding accelerators and 0.05???0.8, 0.05???0.5, and 0.05???1.0. The method further includes removing at least a portion of a surface of the plastic substrate to expose at least a first accelerator. The method further includes plating the exposed surface of the plastic substrate to form at least a first metal layer on the at least first accelerator, and then plating the first metal layer to form at least a second metal layer.
    Type: Application
    Filed: January 20, 2012
    Publication date: May 17, 2012
    Inventors: Qing Gong, Liang Zhou, Weifeng Miao, Xiong Zhang
  • Publication number: 20120103932
    Abstract: A method includes providing a voltage switchable dielectric material having a characteristic voltage, exposing the voltage switchable dielectric material to a source of ions associated with an electrically conductive material, and creating a voltage difference between the source and the voltage switchable dielectric material that is greater than the characteristic voltage. Electrical current is allowed to flow from the voltage switchable dielectric material, and the electrically conductive material is deposited on the voltage switchable dielectric material. A body comprises a voltage switchable dielectric material and a conductive material deposited on the voltage switchable dielectric material using an electrochemical process. In some cases, the conductive material is deposited using electroplating.
    Type: Application
    Filed: January 10, 2012
    Publication date: May 3, 2012
    Inventor: Lex Kosowsky
  • Patent number: 8163156
    Abstract: The inventive method and device for vacuum-compression micro plasma oxidation relate to electrochemical processing of metal, in particular to micro plasma treatment in electrolyte solutions. The aim of said invention is to develop a method for obtaining qualitatively homogeneous coatings by micro-plasma oxidation on large-sized parts, including irregular shaped parts, or simultaneously on a great number of small parts. The second aim of the invention is to design a device for processing parts, having an extended surface area, by using low-power supplies. The inventive method for vacuum-compression micro-plasma oxidation of parts consists in dipping a processable part into an electrolyte solution pre-filled in a sealed container, in generating micro-plasma discharges on the surface of said part and, subsequently, in forming a coating, wherein the micro-plasma discharges are formed in low-pressure conditions above the electrolyte solution.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: April 24, 2012
    Assignees: Tomsk State University (TSU), Sibspark, Limited Liability Company
    Inventors: Anatoli Ivanovich Mamaev, Vera Aleksandrovna Mamaeva, Pavel Igorevich Butyagin
  • Publication number: 20110266156
    Abstract: A method includes forming a first substrate by (a) applying an electrodepositable dielectric coating onto a conductive surface; (b) curing the dielectric coating; (c) depositing an adhesion layer and a seed layer onto the dielectric coating; (d) applying a layer of a first removable material to the seed layer; (e) forming openings in the first removable material to expose areas of the seed layer; (f) electroplating a first conductive material to the exposed areas of the seed layer; (g) applying a layer of a second removable material; (h) forming openings in the second removable material to expose areas of the first conductive material; (i) plating a second conductive material to the exposed areas of the first conductive material; (j) removing the first and second removable materials; (k) removing unplated portions of the seed layer; repeating steps (a) through (k) to form a second substrate; and laminating the first and second substrates together with a layer of dielectric material between the first and secon
    Type: Application
    Filed: July 14, 2011
    Publication date: November 3, 2011
    Applicant: PPG INDUSTRIES OHIO, INC.
    Inventors: Kevin C. Olson, Alan E. Wang
  • Publication number: 20110117387
    Abstract: A method for fabricating metal nanodots on a substrate is provided. The method includes: preparing a nanoporous polysulfone membrane; applying the nanoporous polysulfone membrane onto a substrate; depositing a metal into the pores of the polysulfone membrane thereby forming metal nanodots on the substrate; and removing the nanoporous polysulfone membrane.
    Type: Application
    Filed: November 16, 2010
    Publication date: May 19, 2011
    Inventors: Shivaraman Ramaswamy, Gopalakrishnan Chandasekaran
  • Patent number: 7887691
    Abstract: The present invention provides a method of forming coatings of at least two different coating molecules on at least two electrodes, the method comprising: (a) providing an array of at least two individually-addressable electrodes, (b) allowing a layer of a masking molecule to adsorb onto all electrodes, (c) inducing electrochemical desorption of the masking molecule from at least one but not all electrodes to expose a first set of exposed electrodes, (d) allowing a first coating molecule to adsorb onto the first set of exposed electrodes, (e) exposing all electrodes to a masking molecule to allow adsorption of the masking molecule onto all electrodes, (f) inducing electrochemical desorption of masking molecule from a second set of electrodes to expose a second set of exposed electrodes, (g) allowing a second coating molecule to adsorb onto the second set of exposed electrodes.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: February 15, 2011
    Assignee: Cambridge University Technical Services Limited
    Inventors: Alexander Giles Davies, Christoph Walti, Anton Peter Jacob Middelberg, Michael Pepper, Rene Wirtz
  • Patent number: 7820472
    Abstract: A method for forming front contacts on a silicon solar cell which includes texture etching the front surface of the solar cell, forming an antireflective layer over the face, diffusing a doping material into the face to form a heavily doped region in valleys formed during the texture-etching of the face, depositing an electrically conductive material on the heavily doped regions in the valleys and annealing the solar cell.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: October 26, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Peter Borden, John Dukovic, Li Xu
  • Patent number: 7811427
    Abstract: Permanent or temporary alignment and/or retention structures for receiving multiple components are provided. The structures are preferably formed monolithically via a plurality of deposition operations (e.g. electrodeposition operations). The structures typically include two or more positioning fixtures that control or aid in the positioning of components relative to one another, such features may include (1) positioning guides or stops that fix or at least partially limit the positioning of components in one or more orientations or directions, (2) retention elements that hold positioned components in desired orientations or locations, and/or (3) positioning and/or retention elements that receive and hold adjustment modules into which components can be fixed and which in turn can be used for fine adjustments of position and/or orientation of the components.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: October 12, 2010
    Assignee: Microfabrica Inc.
    Inventors: Adam L. Cohen, Daniel I. Feinberg, Christopher A. Bang
  • Publication number: 20100230286
    Abstract: A method for making a film having an array of cobalt selenide nanowires including: providing an aluminum substrate; anodizing the aluminum substrate to form anodized aluminum including an aluminum oxide layer having a plurality of pores therein on a surface of the aluminum substrate; preparing an electrodeposition composition including a source of cobalt ions and a source of selenite ions; contacting the anodized aluminum with the electrodeposition composition; and applying AC current to the anodized aluminum for a sufficient duration to electrodeposit cobalt selenide into the pores to form a film having an array of oriented cobalt selenide nanowires. According to a different aspect, a film has an aluminum substrate; an oxide layer having a plurality of pores therein on a surface of the aluminum substrate; and an array of cobalt selenide nanowires disposed in the pores.
    Type: Application
    Filed: March 10, 2009
    Publication date: September 16, 2010
    Applicant: RAYTHEON COMPANY
    Inventor: Alexandre D. Lifchits
  • Publication number: 20100163419
    Abstract: A method for fabricating multi-component nanowires is disclosed, which can make multi-component nanowires used to realize a nanowire-based memory device by an electroplating process using a multi-component solution. The method for fabricating multi-component nanowires in accordance with the present invention includes the steps of: (a) preparing an anodized aluminum oxide nanotemplate having a plurality of pores; (b) forming an electrode layer on one surface of the anodized aluminum oxide nanotemplate; (c) injecting the anodized aluminum oxide nanotemplate in a predetermined multi-component solution and then growing multi-component nanowires through the pores of the anodized aluminum oxide nanotemplate by an electroplating process in which the anodized aluminum oxide nanotemplate is used as a cathode; and (d) removing the anodized aluminum oxide nanotemplate.
    Type: Application
    Filed: September 24, 2009
    Publication date: July 1, 2010
    Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Young Keun Kim, Hye Min Ji, Boo Hyun An, Moon Kyu Cho, Ji Hyun Min
  • Patent number: 7718522
    Abstract: A method of plating a plurality of semiconductor devices includes: applying an electrical power source to an anode terminal and a cathode terminal; placing the plurality of semiconductor devices on a non-conductive platform in a plating solution; moving conductive parts across surfaces of the semiconductor devices to be plated, wherein the conductive parts electrically connect the surfaces of the semiconductor devices to the cathode; and wherein plating particles connected to the anode terminal move to and plate the surfaces of the semiconductor devices.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: May 18, 2010
    Assignee: UTAC Thai Limited
    Inventors: Chalermsak Sumithpibul, Somchai Nondhasitthichai, Apichart Phaowongsa
  • Patent number: 7631418
    Abstract: A manufacturing process is provided where aggressive (i.e. tight tolerance) stitching offers several advantages for magnetic write heads but at the cost of some losses during pole trimming. This problem has been overcome by replacing the alumina filler layer, that is used to protect the stitched pole during trimming, with a layer of electroplated material. Because of the superior step coverage associated with the plating method of deposition, pole trimming can then proceed without the introduction of stresses to the stitched pole while it is being trimmed.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: December 15, 2009
    Assignee: Headway Technologies, Inc.
    Inventors: Cherng-Chyi Han, Mao-Min Chen, Laurie Lauchlan, Lei Zhang
  • Publication number: 20090243584
    Abstract: This invention presents microstructures enhanced with nanopillars. The invention also provides a novel way for manufacturing nanopillar-enhanced microstructures, using conventional microfabrication techniques. In some embodiments, the invention also provides methods of use for the nanopillar-enhanced microstructures.
    Type: Application
    Filed: September 11, 2008
    Publication date: October 1, 2009
    Inventors: Guigen Zhang, Venkataramani Anandan, Yeshwanth L. Rao
  • Publication number: 20090165295
    Abstract: Various embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material. In some embodiments the dielectric material is a UV-curable photopolymer. In other embodiments, electrochemically fabricated structures are formed on dielectric substrates.
    Type: Application
    Filed: September 18, 2008
    Publication date: July 2, 2009
    Inventors: Adam L. Cohen, Gang Zhang, Fan-Gang Tseng