Coating Selected Area Patents (Class 205/118)
  • Patent number: 11142826
    Abstract: A substitution gold plating solution for performing uniform gold plating directly on copper wiring of a printed circuit board is provided and a gold plating method using the same is provided, the solution comprising a purine-based compound or a pyrimidine-based compound having a carbonyl oxygen used as a localized corrosion inhibitor, a water-soluble gold compound, an aminocarboxylic acid as a complexing agent, a dicarboxylic acid as a conductivity improving agent, an ?-hydroxycarboxylic acid and heteroaryl carboxylic acid as a base metal elution and reprecipitation preventing agent, a sulfite compound as a gold ion stabilizer, an axole compound as a surface corrosion inhibitor, other surfactants, crystal regulators, pH adjuster, and buffers. The substitution-type electroless gold plating solution according to the present invention prevents the localized corrosion of the copper surface, which is the base metal, and thus the gold plating film produced is excellent in solder mounting reliability.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: October 12, 2021
    Assignee: MK CHEM & TECH CO., LTD
    Inventors: Deok-Gon Han, Tae-Hyon Sung, Jong-Han Song, Tae-Ho Lee, Hyuk-Suk Kwon
  • Patent number: 11114406
    Abstract: A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 7, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Senaka Kanakamedala, Raghuveer S. Makala, Yao-Sheng Lee, Jian Chen
  • Patent number: 11089692
    Abstract: A catalyst for a catalytic ink includes a support particle and a metallic material supported on the support particle. The metallic material is diamminesilver hydroxide, a silver salt, a palladium salt, a gold salt, chloroauric acid, or combinations thereof. A catalytic ink obtained from the catalyst and use of the same to fabricate a conductive circuit are also disclosed.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: August 10, 2021
    Assignee: Taiwan Green Point Enterprises Co., Ltd.
    Inventors: Pen-Yi Liao, Hui-Ching Chuang, Wen-Chia Tsai, Jing-Yi Yang
  • Patent number: 10975485
    Abstract: An apparatus and method for electrochemically depositing a unitary layer structure using a reactor configured to contain an electrolyte solution with an anode array containing a plurality of independently electrically controllable anodes arranged in a two-dimensional array, a cathode, an addressing circuit for receiving a signal containing anode address data and for outputting a signal causing an anode array pattern; and, a controller. in communication with the addressing circuit and the anode array, configured to electrically control each anode in the anode array to cause an electrochemical reaction at the cathode that deposits a unitary layer structure according to the anode array pattern signal.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Fabric8Labs, Inc.
    Inventors: David Forrest Pain, David Morgan Wirth, Jeffrey William Herman
  • Patent number: 10940690
    Abstract: The present application relates to a method of manufacturing an ink-jet printhead comprising: providing a silicon substrate (10) including active ejecting elements (11); providing a hydraulic structure layer (20) for defining hydraulic circuits configured to enable a guided flow of ink; providing a silicon orifice plate (30) having a plurality of nozzles (31) for ejection of the ink; assembling the silicon substrate (10) with the hydraulic structure layer (20) and the silicon orifice plate (30); wherein providing the silicon orifice plate (30) comprises: providing a silicon wafer (40) having a planar extension delimited by a first surface (41) and a second surface (42) on opposite sides of the silicon wafer (40); performing a thinning step at the second surface (42) so as to remove from the second surface (42) a central portion (43) having a preset height (H), the silicon wafer (40) being formed, following the thinning step, by a base portion (44) having a planar extension and a peripheral portion (45) extend
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: March 9, 2021
    Assignee: SICPA HOLDING SA
    Inventors: Lucia Giovanola, Silvia Baldi, Anna Merialdo, Paolo Schina
  • Patent number: 10900135
    Abstract: Disclosed embodiments provide a method and apparatus for continuous production of micro/nanoscale particles using roll-to-roll manufacturing in combination with electroplating. The roll-to-roll process can move a mechanically flexible reel stock material along rotating elements designed to position the material for various additive, subtractive, and modification processes. In accordance with at least one embodiment, processes applied at various stations may include sputtering, electroplating, and/or etching.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: January 26, 2021
    Assignee: Weinberg Medical Physics, Inc.
    Inventors: Irving N. Weinberg, Lamar Odell Mair, Pavel Stepanov
  • Patent number: 10825621
    Abstract: A keyboard key structure includes a plurality of keycaps. Each keycap has a keycap body and an outward layer. The keycap body has an appearance with a first color. The outward layer has an appearance with a second color different from the first color. The outward layer is formed above the keycap body. The outward layer is formed with an engraving portion. The first color is exposed in the engraving portion. The present invention also provides a method of manufacturing a keycap of a keyboard key.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: November 3, 2020
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Che-Hui Tsai, Te-Wei Li, Chieh-Liang Hsiao, Jen-Chieh Huang
  • Patent number: 10775336
    Abstract: An electrical probe is disclosed for measuring an electrical response from a biological cell. The electrical probe includes a tungsten microwire having a sharpened tip section, a catalyst layer formed on the sharpened tip section of the tungsten microwire, and an array of nanotube electrodes vertically aligned on the catalyst layer. The catalyst layer includes a catalyst bilayer including a nickel layer over a gold layer, and the nanotube electrodes include a plurality of silicon nanotubes (SiNTs).
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: September 15, 2020
    Inventors: Mohammad Abdolahad, Ali Saeidi, Milad Gharooni
  • Patent number: 10714436
    Abstract: Systems and methods for achieving uniformity across a redistribution layer are described. One of the methods includes patterning a photoresist layer over a substrate. The patterning defines a region for a conductive line and a via disposed below the region for the conductive line. The method further includes depositing a conductive material in between the patterned photoresist layer, such that the conductive material fills the via and the region for the conductive line. The depositing causes an overgrowth of conductive material of the conductive line to form a bump of the conductive material over the via. The method also includes planarizing a top surface of the conductive line while maintaining the patterned photoresist layer present over the substrate. The planarizing is facilitated by exerting a horizontal shear force over the conductive line and the bump. The planarizing is performed to flatten the bump.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: July 14, 2020
    Assignee: Lam Research Corporation
    Inventors: Bryan L. Buckalew, Thomas A. Ponnuswamy, Steven T. Mayer, Stephen J. Banik, II, Justin Oberst
  • Patent number: 10631407
    Abstract: In one embodiment, an apparatus includes a plurality of layers in a circuit board, each of the layers comprising a fiber weave, two plated holes extending through the layers and connecting two or more of the layers, and a non-plated hole interposed between the plated holes. The non-plated hole passes through a potential CAF (Conductive Anodic Filament) migration path along the fiber weave to prevent CAF formation between the plated holes.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 21, 2020
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Jennifer Oliver, Ashok Kumar Singh, Musan Hu, David Senk
  • Patent number: 10557210
    Abstract: This disclosure relates generally to the discovery of improved methods of reducing corrosion on metals and metal alloys without using hexavalent chromium reagents. More particularly, the disclosure relates to preparing corrosion resistant metals using doped conducting polymers such as polyaniline (PANI) on metal alloys such as aluminum alloys.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: February 11, 2020
    Assignee: THE BOEING COMPANY
    Inventors: Patrick John Kinlen, Lawrence Michael Lawless
  • Patent number: 10508356
    Abstract: A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yuan Kao, Hung-Wen Su, Minghsing Tsai
  • Patent number: 10494731
    Abstract: Embodiments of the present technology may include an electroplating system. The electroplating system may include a vessel. The system may also include a wafer holder configured for holding a wafer in the vessel. The system may further include an anode in the vessel. In addition, the method may include a plurality of thief electrodes. For each thief electrode of the plurality of thief electrodes, a thief current channel may be defined by a channel wall. The channel wall for each thief electrode may define an aperture adjacent to the wafer holder. The thief current channel may extend from each thief electrode to the aperture. The system may include a current control system in electrical communication with the plurality of thief electrodes. The current control system may be configured such that an amount of current delivered to each thief electrode can be adjusted independently.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 3, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Paul McHugh, Gregory J. Wilson, Daniel Woodruff, Marvin Bernt
  • Patent number: 10475594
    Abstract: An electronic device includes a substrate and at least two electrodes spaced by a nanogap, wherein the at least two electrodes are bridged by at least one nanoparticle and wherein the at least one nanoparticle has an overlap area with the at least two electrodes higher than 2% of the area of the at least one nanoparticle. A method of manufacturing of the electronic device and the use of the electronic device in photodetector, transistor, phototransistor, optical modulator, electrical diode, photovoltaic cell or electroluminescent component are also described.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: November 12, 2019
    Assignees: NEXDOT, FONDS DE L'ESPCI—GEORGES CHARPAK
    Inventors: Emmanuel Lhullier, Benoit Dubertret
  • Patent number: 10468364
    Abstract: A plating method which can achieve a desired dome height is disclosed. The method includes: preparing correlation data showing a relationship between proportion of dome height to bump height and concentration of chloride ions; producing a plating solution containing chloride ions at a concentration which has been selected based on a desired proportion of dome height to bump height and on the correlation data, the selected concentration being in a range of 100 mg/dm3 to 300 mg/dm3; immersing a substrate in the plating solution; and passing an electric current between an anode and the substrate, both immersed in the plating solution, thereby plating the substrate to form bumps.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: November 5, 2019
    Assignee: EBARA CORPORATION
    Inventors: Yohei Wakuda, Yasuyuki Masuda, Masahi Shimoyama
  • Patent number: 10364505
    Abstract: The embodiments herein relate to methods and apparatus for electroplating one or more materials onto a substrate. Typically, the embodiments herein utilize a channeled plate positioned near the substrate, creating a cross flow manifold between the channeled plate and substrate, and on the sides by a flow confinement ring. A seal may be provided between the bottom surface of a substrate holder and the top surface of an element below the substrate holder (e.g., the flow confinement ring). During plating, fluid enters the cross flow manifold through channels in the channeled plate, and through a cross flow inlet, then exits at the cross flow exit, positioned opposite the cross flow inlet. The apparatus may switch between a sealed state and an unsealed state during electroplating, for example by lowering and lifting the substrate and substrate holder as appropriate to engage and disengage the seal.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: July 30, 2019
    Assignee: Lam Research Corporation
    Inventors: Kari Thorkelsson, Aaron Berke, Bryan L. Buckalew, Steven T. Mayer
  • Patent number: 10357841
    Abstract: A cap assembly for optical communications comprising a housing that includes a front side perpendicular from a bottom side, opposing parallel first and second sides perpendicular from the bottom side, and a back side disposed perpendicularly between the first side and the second side offset from respective ends of the first side and the second side opposite the front side. The back side includes an opening there-through and a three-sided ledge formed along an interior of the first side leg, an exterior of the back side, and an interior of the second side leg. The cap assembly further includes a window configured to contact the three-sided ledge of the back side, the glass panel covering the opening there-through and attached to the assembly via a solder pre-form.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: July 23, 2019
    Assignee: MATERION CORPORATION
    Inventors: Ramesh Kothandapani, Chee Kong Lee
  • Patent number: 10340143
    Abstract: A seed layer of aluminum is deposited over a wafer. A layer of photoresist material is deposited over the seed layer of aluminum. The photoresist material is patterned and developed to expose portions of the seed layer of aluminum through openings in the photoresist material. An electrochemical transformation process is performed on the wafer to electrochemically transform the portions of the seed layer of aluminum that are exposed through openings in the photoresist material into anodic aluminum oxide (AAO). The AAO includes a pattern of holes that extend through the AAO to expose areas of the top surface of the wafer beneath the seed layer of aluminum. The photoresist material is removed from the wafer. The wafer is exposed to a plasma to etch holes into the wafer at the areas of the top surface of the wafer that are exposed by the pattern of holes in the AAO.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: July 2, 2019
    Assignee: Lam Research Corporation
    Inventors: Chanyuan Liu, Shih-Ked Lee
  • Patent number: 10325850
    Abstract: An apparatus includes a laminate and a lid. The laminate generally includes a dielectric layer between a first conductive layer and a second conductive layer. The first conductive layer may include a probe configured to transfer a radio-frequency signal in a millimeter-wave band. The second conductive layer may be configured to provide a continuous ground plane parallel to the probe and separated from the probe by the dielectric layer. A plurality of channels may be (a) formed into a side of the second conductive layer opposite the dielectric layer, (b) formed to a depth less than a thickness of the second conductive layer, and (c) sized to permit gasses formed while securing the laminate to a substrate to escape from between the laminate and the substrate. The lid may be in contact with the first conductive layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 18, 2019
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Emmanuelle R. O. Convert, Ryan M. Clement, Simon J. Mahon, Leif G. M. Snygg
  • Patent number: 10236120
    Abstract: A method for manufacturing a strip of impregnated anodized aluminum, for use in a coil of an electrotechnical component, said coil including an interstitial material providing dielectric cohesion and insulation functions, said interstitial material being suitable for cross-linking, in other words for forming, by chemical reactions between the components thereof when subjected to certain physical conditions, molecular structures being organized in a lattice, the method comprising: a step of applying the precursor mixture of said interstitial material to the anodized aluminum; at least one step of cross-linking the precursor mixture in order to form said interstitial material on the strip of aluminum; wherein the anodized aluminum has not been subjected to the sealing of the pores of the alumina formed by anodization prior to the application of the precursor mixture of said interstitial material.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: March 19, 2019
    Assignee: SAFRAN ELECTRICAL & POWER
    Inventor: Mathieu Charlas
  • Patent number: 10228387
    Abstract: This disclosure provides systems and methods for a two-dimensional material-based accelerometer. In one embodiment, an accelerometer comprises a substrate; a membrane suspended over an opening in the substrate to form a suspended membrane, wherein the membrane is composed of a two-dimensional material; a mass structure coupled to the suspended membrane; and wherein the mass structure distorts the suspended membrane about a first axis in response to an applied acceleration providing a first change in a conductance of the suspended membrane so that the applied acceleration along the first axis can be detected.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: March 12, 2019
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Adam Hurst, Sunwoo Lee, James Hone
  • Patent number: 10131570
    Abstract: A method of fabricating a liquid-based masking layer for a wet etching process, is disclosed. The method comprises forming a coated solid substrate by coating a solid substrate with a coating; forming a preliminary masking layer by removing parts of the coating which are not included in a pattern; depositing a porous surface on the preliminary mask to obtain a porous preliminary mask; forming a liquid-based masking layer by filling the pores of the porous preliminary mask with a filling liquid; and applying an etchant to a surface of the solid substrate and the liquid-based masking layer, etching parts of the substrate that are not covered with the liquid-based masking layer.
    Type: Grant
    Filed: October 15, 2017
    Date of Patent: November 20, 2018
    Inventors: Behzad Haghighi, Mojtaba Karimikargar
  • Patent number: 10060799
    Abstract: A variety of nanostructures are provided having a metal nanowire having a plurality of faces extending along a length of the nanowire, and a plurality of semiconductor nanorods forming two or more nanorod arrays, wherein each of the nanorod arrays is attached to a different surface of the nanowire. For example, in some embodiments, the nanostructure is a silver nanowire having a pentagonal cross section and five faces extending along the length of the nanowire, and metal oxide nanorods forming five nanorod arrays extending along each of the five faces of the silver nanowire. The nanostructures can demonstrate high temperature coefficients of resistance, and can be used in a variety of bolometric materials. In some embodiments, bolometric materials are provided including a plurality of the nanostructures deposited onto a surface of a substrate. Methods of making the nanostructures and bolometers are also provided.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: August 28, 2018
    Assignee: Board of Regents, The University of Texas System
    Inventors: Miguel Jose Yacaman, Francisco Javier Gonzalez, J. Jesus Velazquez Salazar, John Eder Sanchez, Arturo Ponce-Pedraza, Fernando Mendoza Santoyo
  • Patent number: 9993982
    Abstract: The present invention relates to the fabrication of complicated electronic and/or mechanical structures and devices and components using homogeneous or heterogeneous 3D additive build processes. In particular the invention relates to selective metallization processes including electroless and/or electrolytic metallization.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: June 12, 2018
    Assignee: NUVOTRONICS, INC.
    Inventors: David W. Sherrer, Dara L. Cardwell
  • Patent number: 9963793
    Abstract: A cell unit includes a cell stack, two manifolds. The cell stack includes cells. Each cell has a elliptical columnar shape. The each cell includes an inner electrode layer, a solid oxide solid electrolyte layer, an outer electrode layer, a first portion, a second portion, a middle portion and a distribution hole. The solid oxide solid electrolyte layer is on the inner electrode layer. The outer electrode layer is on the solid oxide solid electrolyte layer. The first portion is at one end of the each cell in the length direction of the cells. The second portion is at the other end of the each cell in the length direction. The middle portion is located between the first portion and the second portion. The distribution hole passes through from the first portion to the second portion. A first manifold fixes the first portions. A second manifold fixes the second portions.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: May 8, 2018
    Assignee: KYOCERA Corporation
    Inventors: Takashi Ono, Shinpei Shiraishi, Naruto Takahashi
  • Patent number: 9953908
    Abstract: A barrier layer is formed over electrically conductive contact pads on a substrate such as a wafer. A photoresist layer is applied over the barrier layer, and openings in the photoresist layer are filled with solder to form solder bumps. The barrier layer may be removed from within the openings prior to filling the openings with solder. The process is applicable to fine pitch architectures and chip size packaging substrates. The photoresist layer and portions of the barrier layer outside of the openings are removed following solder fill.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Eric P. Lewandowski, Jae-Woong Nah, Peter J. Sorce
  • Patent number: 9809898
    Abstract: Disclosed herein are electroplating systems for forming a layer of metal on a wafer which include an electroplating module and a wafer edge imaging system. The electroplating module may include a cell for containing an anode and an electroplating solution during electroplating, and a wafer holder for holding the wafer in the electroplating solution and rotating the wafer during electroplating. The wafer edge imaging system may include a wafer holder for holding and rotating the wafer through different azimuthal orientations, a camera oriented for obtaining multiple azimuthally separated images of a process edge of the wafer while it is held and rotated (the process edge corresponding to the outer edge of the layer of metal formed on the wafer), and image analysis logic for determining an edge exclusion distance, wherein the edge exclusion distance is a distance between the wafer's edge and the process edge.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: November 7, 2017
    Assignee: Lam Research Corporation
    Inventors: Daniel Mark Dinneen, James E. Duncan
  • Patent number: 9767966
    Abstract: On seed metal layer of first metal, pedestal and counter electrode are formed of second metal by plating, adjacent to free space region. The free space region is filled with first sacrificial layer. By using resist pattern, second sacrificial metal layer is formed, extending from the first sacrificial layer to a portion of the pedestal, and lower structure of third metal is formed on the second sacrificial layer, by contiguous plating, exposing a portion of the pedestal not formed with the second sacrificial layer, the third metal having composition and thermal expansion coefficient equivalent to the second metal. Upper structure of fourth metal having composition and thermal expansion coefficient equivalent to the second and third metals is formed on the pedestal and the lower structure by plating. The first and second sacrificial layers are removed, leaving an electric equipment with a movable portion.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: September 19, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hiroaki Inoue, Xiaoyu Mi
  • Patent number: 9702051
    Abstract: Composite structures that have an appearance of an anodized bulk metal but that is non-capacitive and/or radio frequency (RF) transparent are disclosed. The composite structure can be part of an enclosure of an electronic device. The composite structure can give the enclosure a metallic look without interfering with the functioning of some electronic components of the electronic device, such as RF antennas, touch pads and touch screens. Some embodiments involve forming a metal oxide layer and depositing a non-capacitive layer on the metal oxide layer. Some embodiments involve forming an imitation metal oxide layer and depositing a non-capacitive layer on the imitation metal oxide layer.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: July 11, 2017
    Assignee: Apple Inc.
    Inventor: Brian P. Demers
  • Patent number: 9699905
    Abstract: To provide a wiring board ensuring adhesion strength of a connecting terminal to reduce the connecting terminal from being fallen over or peeled off under fabrication process. The wiring board according to the present invention includes a laminated body where one or more layer of each of an insulating layer and a conductor layer are laminated. The wiring board includes a plurality of connecting terminals formed separately from one another on the laminated body and a filling member filled up between the plurality of connecting terminals. The filling member is filled up to a position lower than a height of the plurality of connecting terminals. The connecting terminals has a cross section with a trapezoidal shape where a width of a first principal surface on a side contacting the laminated body is wider than a width of a second principal surface facing the first principal surface.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: July 4, 2017
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Tomohiro Nishida, Makoto Wakazono, Seiji Mori
  • Patent number: 9670588
    Abstract: An electroplating apparatus that promotes uniform electroplating on the substrates having thin seed layers includes a convex anisotropic high resistance ionic current source (AHRICS), such as an electrolyte-permeable resistive domed plate. The AHRICS is positioned in close proximity of the substrate, so that a distance from the central portion of the AHRICS to the substrate is smaller than the distance from the edge portion of the AHRICS to the substrate. The apparatus further includes a plating chamber configured to hold the electrolyte and an anode. The apparatus further includes a substrate holder configured to hold the substrate. In some embodiments, the apparatus further includes a secondary (thief) cathode configured to divert ionic current from the near-edge region of the substrate.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: June 6, 2017
    Assignee: Lam Research Corporation
    Inventor: Zhian He
  • Patent number: 9535216
    Abstract: The present invention relates to a dry film for an optical waveguide which has a carrier base material, a resin layer for an optical waveguide that can be cured by active energy ray or heat, and a protective film. The surface of the protective film that is in contact with the resin layer for an optical waveguide is a roughened surface.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: January 3, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shingo Maeda, Naoyuki Kondo, Shinji Hashimoto, Toru Nakashiba, Junko Kurizoe
  • Patent number: 9518334
    Abstract: A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: December 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yuan Kao, Hung-Wen Su, Minghsing Tsai
  • Patent number: 9515205
    Abstract: A method for creating electrically conducting or semiconducting patterns on a textured surface including plural reliefs of amplitude greater than or equal to 100 nanometers, including: preparing a substrate during which at least the textured surface of the substrate is made electrically conducting; coating during which at least one layer of an imprintable material is laid on the textured surface, made electrically conducting, of the substrate; pressing a mold including valleys or protrusions to transfer the valleys or the protrusions of the mold into the imprintable material to form patterns therein; removing the mold while leaving the imprint of the patterns in the imprintable material; exposing the textured surface, made electrically conducting, of the substrate, at a bottom of the patterns; and electrically depositing an electrically conducting or semiconducting material into the patterns to form conducting or semiconducting patterns.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: December 6, 2016
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE AUX ENERGIES ALTERNATIVES
    Inventors: Carole Pernel, Nicolas Chaix, Stefan Landis
  • Patent number: 9512532
    Abstract: Multi-layer structures are electrochemically fabricated by depositing a first material, selectively etching the first material (e.g. via a mask), depositing a second material to fill in the voids created by the etching, and then planarizing the depositions so as to bound the layer being created and thereafter adding additional layers to previously formed layers. The first and second depositions may be of the blanket or selective type. The repetition of the formation process for forming successive layers may be repeated with or without variations (e.g. variations in: patterns; numbers or existence of or parameters associated with depositions, etchings, and or planarization operations; the order of operations, or the materials deposited). Other embodiments form multi-layer structures using operations that interlace material deposited in association with some layers with material deposited in association with other layers.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: December 6, 2016
    Assignee: Microfabrica Inc.
    Inventor: Dennis R. Smalley
  • Patent number: 9493884
    Abstract: A method and composition for electroplating Cu onto a substrate in the manufacture of a microelectronic device involving and electrolytic solution containing a source of Cu ions and a quaternized pyridinium salt compound for leveling.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: November 15, 2016
    Inventors: Vincent Paneccasio, Jr., Richard Hurtubise, Xuan Lin, Paul Figura
  • Patent number: 9465003
    Abstract: A membrane electrode includes a novel sensor combining a filtering function of a membrane and a signal measuring ability of an electrode. A target material may be measured by filtration through the membrane. A small amount of target materials may be detected with high sensitivity using an amplified electrical signal by increasing electrical conductivity by reducing metal ions on the membrane, and thus the target material may be subject to quantitative analysis. In addition, only a target material selectively binding to a receptor may be filtrated by passing a sample through the membrane after a receptor material is fixed to the electrode, and thus may be used to detect an electrical signal. In addition, the sensor may measure a signal in various methods such as electrical conductivity, impedance, etc.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: October 11, 2016
    Assignee: KOREA RESEARCH INSTITUTE OF BIOSCIENCE AND BIOTECHNOLOGY
    Inventors: Min Gon Kim, Jun Hyoung Ahn, Yun Ju Sung, Yong Beom Shin, Hyo Arm Joung
  • Patent number: 9466527
    Abstract: Techniques include methods for creating contacts for microchips, solar films, etc., for electrically connecting conductive elements and/or for current spreading. Embodiments herein include using an oversized “board” or contact array positioned between a lower layer and an upper layer. This contact array is created by directed self-assembly (DSA) of block copolymers. The lower and upper layers can have conductive structures such as lines. The oversized board can be comprised of hundreds, thousands, millions (etc.) of small conductive contact cylinders, lines or other vertical structures, with each conductive structure electrically isolated from adjacent conductive structures in the array. A crossover location of a line on a lower level with a line on an upper level is connected with multiple conductive structures located at the cross over location.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: October 11, 2016
    Assignee: Tokyo Electron Limited
    Inventor: Anton J. deVilliers
  • Patent number: 9435049
    Abstract: Prior to electrodeposition, a semiconductor wafer having one or more recessed features, such as through silicon vias (TSVs), is pretreated by contacting the wafer with a pre-wetting liquid comprising a buffer (such as a borate buffer) and having a pH of between about 7 and about 13. This pre-treatment is particularly useful for wafers having acid-sensitive nickel-containing seed layers, such as NiB and NiP. The pre-wetting liquid is preferably degassed prior to contact with the wafer substrate. The pretreatment is preferably performed under subatmospheric pressure to prevent bubble formation within the recessed features. After the wafer is pretreated, a metal, such as copper, is electrodeposited from an acidic electroplating solution to fill the recessed features on the wafer. The described pretreatment minimizes corrosion of seed layer during electroplating and reduces plating defects.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: September 6, 2016
    Assignee: Lam Research Corporation
    Inventor: Matthew Thorum
  • Patent number: 9431475
    Abstract: A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: August 30, 2016
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Piyush Savalia
  • Patent number: 9427773
    Abstract: A combined scribing/filling device for scribing a desired channel, trough, trench or groove in a layer currently being fabricated and simultaneously filling the scribed channel, trough, trench or groove with a desired filling material. The combined scribing/filling device comprises (1) a scribing tool having a scribing tip which facilitates scribing of the desired channel, trough, trench or groove in the layer currently being fabricated; and a dispensing/shaping orifice for filling the scribed channel, trough, trench or groove with the filling material. The scribing tip is located coincident with respect to the dispensing/shaping orifice to facilitate simultaneously scribing and filling of the channel, trough, trench or groove. A method of fabricating a three dimensional model from a composite model formed by a plurality of layers, by simultaneously scribing and filling of the channel, trough, trench or groove is also disclosed.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: August 30, 2016
    Assignee: Solidscape, Inc.
    Inventors: Bun Chay Te, John T Wigand
  • Patent number: 9412524
    Abstract: A method for forming conductive electrode patterns of a solar cell is provided. The method includes preparing a glass substrate and forming a transparent conductive oxide film (TCO) on the glass substrate. Then, a titanium oxide (TiO2) layer and a silver (Ag) electrode are formed on the glass substrate. A nickel (Ni) layer is formed on the Ag electrode and a copper (Cu) layer is formed on the Ni layer. In addition, a tin (Sn) layer is formed on the Cu layer.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: August 9, 2016
    Assignee: Hyundai Motor Company
    Inventor: Kyoung Jin Jeong
  • Patent number: 9395830
    Abstract: Disclosed is a wired electrode of touch screen panel for transmitting a touch signal sensed by a signal sensing pattern of touch screen panel to an external driving circuit, wherein the wired electrode formed on a substrate includes at least one curved portion, and a plurality of fine protrusions are formed on an inner surface of a groove of a resin layer on the substrate. The groove is filled with a conductive material to form the wired electrode.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: July 19, 2016
    Assignee: Mirae Nano Technologies Co., Ltd.
    Inventors: Kyung Hyun Jang, Hyung Bae Choi, Sung Jin Ryu, Ki Won Park
  • Patent number: 9390969
    Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: July 12, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: David A. DeMuynck, Zhong-Xiang He, Daniel R. Miga, Matthew D. Moon, Daniel S. Vanslette, Eric J. White
  • Patent number: 9371595
    Abstract: Frost-free surfaces and methods for manufacturing such surfaces are described. The frost-free surfaces reduce ice build-up, prevent vapor condensation and reduce adhesion force between ice and a solid substrate. The surfaces can be on parts used in devices where superhydrophobic properties may be obtained post or during device manufacturing. The superhydrophobic properties are the result of aluminum oxide clusters made on such surfaces.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: June 21, 2016
    Assignee: Conopco, Inc.
    Inventor: Chunbo Ran
  • Patent number: 9366657
    Abstract: The purpose of the present invention is to grasp the state in which hydrophilic groups of an electrolyte are distributed in a reaction layer for fuel cells. Nitric acid groups are bonded to hydrophilic groups (sulfonic acid groups) contained in a reaction layer for fuel cells, and metal ions capable of forming a nitrosyl complex with the nitric acid groups, e.g., ruthenium ions, are introduced into the reaction layer to dye the nitric acid groups bonded to the hydrophilic groups contained in the reaction layer. When the hydrophilic groups have agglomerated, the nitric acid groups bonded thereto also agglomerate. When said nitric acid groups are dyed with ruthenium, the ruthenium also agglomerates to make it possible to examine said nitric acid groups with an electron microscope.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: June 14, 2016
    Assignee: KABUSHIKI KAISHA EQUOS RESEARCH
    Inventor: Taizo Yamamoto
  • Patent number: 9343524
    Abstract: Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: May 17, 2016
    Assignee: Intel Corporation
    Inventor: Ruth A. Brain
  • Patent number: 9326374
    Abstract: A flexible circuit board comprises a substrate which has a polyimide layer recessed to define at least a compartment. The compartment includes an inner wall surface having a side wall and a bottom wall. The compartment is for containing a multilayer unit, wherein the multilayer unit includes an adhesion enhancing layer formed on the wall of the compartment, a first electrically conducting layer disposed on the adhesion enhancing layer, and a second electrically conducting layer formed on the first electrically conducting layer. The adhesion enhancing layer is palladium. The first electrically conducting layer is nickel. The substrate is composed of polyimide (PI).
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: April 26, 2016
    Assignee: ICHIA TECHNOLOGIES, INC.
    Inventors: Chien-Hwa Chiu, Chih-Min Chao, Peir-Rong Kuo, Chia-Hua Chiang, Chih-Cheng Hsiao, Feng-Ping Kuan, Ying-Wei Lee, Yung-Chang Juang
  • Patent number: 9284645
    Abstract: A method of metallizing the surface of a substrate electrolessly, by spraying one or more oxidation-reduction solutions thereonto. The steps of this method include: a) physical or chemical treatment to reduce the surface tension of the substrate before metallization; b) electroless metallization of the surface of the substrate treated in step a), by spraying one or more oxidation-reduction solutions in the form of one or more aerosols thereonto; and c) formation of a top coat on the metallized surface. Compact devices for implementing this method and the products obtained are also disclosed.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: March 15, 2016
    Assignee: Jet Metal Technologies
    Inventor: Samuel Stremsdoerfer
  • Patent number: 9260793
    Abstract: Methods of electroplating metal on a substrate while controlling azimuthal uniformity, include, in one aspect, providing the substrate to the electroplating apparatus configured for rotating the substrate during electroplating, and electroplating the metal on the substrate while rotating the substrate relative to a shield such that a selected portion of the substrate at a selected azimuthal position dwells in a shielded area for a different amount of time than a second portion of the substrate having the same average arc length and the same average radial position and residing at a different angular (azimuthal) position. For example, a semiconductor wafer substrate can be rotated during electroplating slower or faster, when the selected portion of the substrate passes through the shielded area.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: February 16, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, David W. Porter, Bryan L. Buckalew, Robert Rash