Abstract: A color filter substrate and an organic light-emitting display panel are disclosed. The color filter substrate is rectangular and has an upper side, a lower side, a left side, and a right side, wherein, the lower side corresponds to a driving chip of the organic light-emitting display panel. The color filter substrate includes a light-shielding layer defined with a plurality of light-transmitting holes arranged in an array, and from the upper side to the lower side, openings of the light-transmitting holes are gradually smaller. The present disclosure allows an aperture ratio of the light-shielding layer to be gradually reduced from the upper side that is away from the driving chip to the lower side that corresponds to the driving chip. Therefore, an area of the organic light-emitting display panel having uneven chroma and brightness can be compensated, thereby improving uniformity of the chroma and brightness.

Abstract: A method for fabrication of a micromechanical part made of a one-piece synthetic carbon allotrope based material, the method including: forming a substrate with a negative cavity of the micromechanical part to be fabricated; coating the negative cavity of the substrate with a layer of the synthetic carbon allotrope based material in a smaller thickness than the depth of the negative cavity; and removing the substrate to release the one-piece micromechanical part formed in the negative cavity.

Abstract: Embodiments are related to substrates having one or more well structures each exhibiting substantially vertical sidewalls and substantially planar bottoms.

Abstract: A manufacturing method according to the present invention includes: a step of providing a first conductive metal flat plate; a step of forming a slit in a busbar assembly forming region of the flat plate; a step of coating the flat plate with a coating material containing an insulating resin such that at least the slit is filled with the insulating resin layer; a step of curing the coating material to form the insulating resin layer; and a cutting step of cutting off the insulating resin layer in the slit and busbar forming parts of the first conductive metal flat plate from the first conductive metal flat plate, wherein the busbar forming parts face each other with the slit therebetween.

Abstract: A method of manufacturing a semiconductor device includes forming a hard mask layer over a substrate and activating a surface of the hard mask layer to form a surface active layer over the hard mask layer. A resist layer is formed over the hard mask layer and a metal-containing layer is selectively formed over the surface active layer in at least one trench defined between portions of the resist layer. The resist layer is removed to define a pattern between portions of the selectively formed metal-containing layer and the hard mask layer is etched in accordance with the pattern. The etched pattern is transferred to at least a portion of the substrate and at least a portion of the hard mask layer, surface active layer, and metal-containing layer are removed.

Abstract: Embodiments are generally directed to non-planar on-package via capacitor. An embodiment of an embedded capacitor includes a first plate that is formed in a package via; a dielectric layer that is applied on the first plate; and a second plate that is formed in a cavity in the dielectric layer, wherein the first plate and the second plate are non-planar plates.

Abstract: Devices and methods for manufacturing RF circuits and systems in both passive and active forms are contemplated herein. Exemplary devices include 3D electrical and mechanical structures which are created from individual slices which may be assembled to create a final functional block such as a circuit, component or a system. The slices may fabricated by a variety of manufacturing techniques, such as micromachined layer-by-layer metal batch processing.

Abstract: The present disclosure provides a method to provide a conductive bus bar on a patterned transparent conductor, such as ITO traces used for touch screen manufacturing. The method can be a cheaper and a more convenient technique to pattern a conductive metal or metal alloy, such as copper, silver, or a copper/silver/titanium alloy, on ITO electrodes in a roll-to-roll process.

Abstract: The invention relates to a method for filling at least one cavity (5a, 5b) of a multi-layer component (1) with filling material (9). In a first step, the method comprises providing a main body (2) of the multi-layer component (1), the main body (2) having at least one cavity (5a, 5b). In a subsequent step, the method comprises placing the main body (2) in a chamber (11) and then generating a first pressure, the first pressure being a negative pressure. Then, a filling material (9) is arranged on the main body (2). Furthermore, the invention relates to a multi-layer component (1). The multi-layer component (1) has a main body (2) with at least one cavity (5a, 5b), wherein the cavity (5a, 5b) is filled with a filling material (9) which has a viscosity of between 200 mPas and 2000 mPas.

Abstract: A base material for growing a single crystal diamond that includes at least a single crystal SiC substrate, and an iridium film or a rhodium film heteroepitaxially grown on a side of the single crystal SiC substrate where the single crystal diamond is to be grown. As a result, there is provided a base material for growing a single crystal diamond and a method for producing a single crystal diamond substrate which can grow the single crystal diamond having a large area and good crystallinity and produce a high quality single crystal diamond substrate at low cost.

Abstract: A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.

Abstract: A method of forming a conductive via in a substrate includes forming a via hole covered by a dielectric layer followed by an annealing process. The dielectric layer can getter the mobile ions from the substrate. After removing the dielectric layer, a conductive material is formed in the via hole, forming a conductive via in the substrate.

Abstract: A wire grid polarizer comprising an array of parallel, elongated first rib groups disposed over a substrate. Each first rib group can comprise a central first transmissive rib and a pair of first wires including a first wire disposed along each side of the first transmissive rib. A first dielectric material can substantially fill first gaps between each rib group and an adjacent rib group. An array of parallel, elongated second wires can be disposed over the rib groups and the first dielectric material. The first wires or the second wires can be absorptive and the other of the first wires or the second wires can be reflective.

Abstract: Provided is a method for manufacturing a probe card which inspects electrical characteristics of a plurality of semiconductor devices in batch. The method includes: a step of forming a plurality of probes, which are to be brought into contact with external terminals of the semiconductor devices, on one side of a board which forms the base body of the probe card; a step of forming on the board, by photolithography and etching, a plurality of through-holes which reach the probes from the other side of the board; a step of forming, in the through-holes, through electrodes to be conductively connected with the probes, respectively; and a step of forming wiring, which is conductively connected with the through electrodes, on the other side of the board.

Abstract: A method of manufacturing touch devices comprises the steps of cutting a large-sized substrate into a plurality of even units and then performing the subsequent machining processes, providing the required materials of each structure layer, layer by layer, via sputtering or coating, and then simultaneously forming each structure layer via processes such as photolithography, developing, and etching. Therefore, the manufacturing cost is significantly reduced and the structure strength is substantially enhanced.

Abstract: A particulate matter (PM) sensor unit may include an exhaust line where exhaust gas passes, and a PM sensor that may be disposed at one side of the exhaust line and that generates a signal when particulate matter included in the exhaust gas passes the vicinity thereof, wherein the PM sensor may be an electrostatic induction type that generates an induction charge while the particulate matter having an electric charge passes the vicinity thereof

Abstract: The invention provides a process for producing a substrate with a piercing aperture, the piercing aperture being formed by conducting dry etching from the side of a second surface opposite to a first surface of a substrate to the first surface, the process comprising, in the following order, the steps of (a) forming a groove around a region where the piercing aperture is formed in the first surface of the substrate, (b) forming an etch-stop layer in the region where the piercing aperture is formed in the first surface of the substrate and in the interior of the groove, and (c) forming the piercing aperture by conducting the dry etching from the side of the second surface.

Abstract: A process of fabricating a heat dissipation substrate is provided. A metal substrate having an upper surface, a lower surface, first recesses located on the upper surface and second recesses located on the lower surface is provided. The metal substrate is divided into carrier units and connecting units connecting the carrier units. A first and a second insulating materials are respectively filled into the first and the recesses. A first conductive layer is formed on the upper surface and the first insulating material. A second conductive layer is formed on the lower surface and the second insulating material. The first and the second conductive layers are patterned to form a first and a second patterned conductive layers. The first and the second insulating materials are taken as an etching mask to etch the connecting units of the metal substrate so as to form a plurality of individual heat dissipation substrates.

Abstract: A new and novel method utilizing current nano-technological processes for fabricating a range of micro-devices with significantly expanded capabilities, unique functionalities at microscopic levels, enhanced degree of flexibilities, reduced costs and improved performance in the fields of bioscience and medicine is disclosed in the within patent application. Micro-devices fabricated using the disclosed nano-technological techniques have significant improvements in many areas over the existing, conventional methods. Such improvements include, but are not limited to reduced overall costs, early disease detection, targeted drug delivery, targeted disease treatment and reduced degree of invasiveness in treatment. Compared with existing, conventional approaches, the said inventive approach disclosed in this patent application is much more microscopic, sensitive, accurate, precise, flexible and effective.

Abstract: A substrate includes an iron-nickel alloy core or a cobalt-nickel ferrous alloy core, a chromium conversion coating on at least a portion of the core, and an insulating coating on the chromium conversion coating. A method of making a substrate includes: providing an iron-nickel alloy core or a cobalt-nickel ferrous alloy core, applying a chromium conversion coating on at least a portion of the core, and applying an insulating coating on the chromium conversion coating.

Abstract: Provided is a method of manufacturing a circuit which includes: (a) providing a substrate made of a conductive material; (b) etching a first surface of the substrate excluding a region in which at least one via is to be formed; (c) etching a region of the etched first surface of the substrate in which an insulated portion of a first circuit is to be formed; (d) stacking a first insulation layer in spaces formed by the etching performed in operations (b) and (c); and (e) grinding a second surface of the substrate to expose the first insulation layer outward along with the first circuit, thereby forming a circuit board.

Abstract: An electrostatic chuck of a stack structure includes a metal layer interposed between insulating layers and a groove formed at a peripheral portion of the electrostatic chuck to have a thickness gradually increasing toward an outside, the groove being covered with a thermally sprayed insulating film. The thermally sprayed film covers at least a portion of the metal layer exposed at an inside of the groove such that the thermally sprayed film does not protrude from the groove.

Abstract: An ultrasound transducer for use in intra-vascular ultrasound (IVUS) imaging systems including a single crystal composite (SCC) layer is provided. The transducer has a front electrode on a side of the SCC layer; and a back electrode on the opposite side of the SCC layer. The SCC layer may have a dish shape including pillars made of a single crystal piezo-electric material embedded in a polymer matrix. Also provided is an ultrasound transducer as above, with the back electrode split into two electrodes electrically decoupled from one another. A method of forming an ultrasound transducer as above is also provided. An IVUS imaging system is provided, including an ultrasound transducer rotationally disposed within an elongate member; an actuator; and a control system controlling activation of the ultrasound transducer to facilitate imaging.

Abstract: A method of manufacturing a magnetic sensor having a hard bias structure located at a back edge of the sensor. The method forms an electrical lapping guide that is compatible for use with such a sensor having a back edge hard bias structure and which can accurately determine a termination point for a lapping operation that forms an air bearing surface of the slider and determines the sensor stripe height.

Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 25 at % carbon. Another capacitor forming method includes forming a support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 20 at % carbon. The support material has a thickness and the opening has an aspect ratio 20:1 or greater within the thickness of the support material.

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

Abstract: Disclosed herein is a method of manufacturing a printed circuit board, including the steps of providing a substrate including a first metal layer formed thereon, and forming a patterned first insulation layer on the first metal layer. The method further includes patterning the first metal layer to allow the first metal layer to have a pattern corresponding to that of the first insulation layer, thus forming a first circuit layer, and forming a second insulation layer on the substrate such that the second insulation layer surrounds the first circuit layer and the first insulation layer formed on the first circuit layer. The printed circuit board is advantageous in that process time and process cost can be reduced because a first insulation layer is used as an etching resist and is included as a part of a printed circuit board even after etching.

Abstract: Embodiments of the present disclosure provide semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board. The substrate is formed using several techniques that minimize the amount of mask levels used to form the substrate. For example, a metal substrate is patterned to form a three dimensional pattern on the surface. A dielectric material is deposited on the three dimensional pattern. Using several patterning and polishing embodiments described herein, the metal/dielectric substrate is patterned and polished to form a substantially flush surface that is bonded to the semiconductor device. In one embodiment, the top surface of the metal/dielectric substrate is patterned to expose the underlying metal substrate and the bottom surface of the metal substrate is polished to be substantially flush with the dielectric material.

Abstract: A printed circuit board includes a first insulating layer, a second insulating layer on the first insulating layer, and at least one via formed through the first and second insulating layers in a layered structure. The via includes a first via layer formed through the first insulating layer, a second via layer formed on the first via layer while passing through the second insulating layer, and an adhesive layer between the first and second via layers. The first via layer has a section different from a section of the second via layer. The adhesive property between the copper layer and the insulating layer is improved. The vias used to connect interlayer circuits to each other are formed between a plurality of insulating layers through an etching process instead of a laser process or a polishing process, thereby improving the process ability and reducing the manufacturing cost.

Abstract: Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer. The via includes a first part, a second part below the first part, and a third part between the first and second parts, and the third part includes a metal different from a metal of the first and second parts. The inner circuit layer and the via are simultaneously formed so that the process steps are reduced. Since odd circuit layers are provided, the printed circuit board has a light and slim structure.

Abstract: Methods for fabricating arrays of nanoscaled alternating lamellae or cylinders in a polymer matrix having improved long range order utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.

Abstract: A circuit board includes an insulating layer with a surface on which a semiconductor element is to be mounted and wiring portions that are located on the insulating layer. The wiring portions includes upper wiring portions, lower wiring portions, and interlayer wiring portions. The upper wiring portions, the lower wiring portions, and the interlayer wiring portions are integrally defined by a single copper sheet. With this configuration, a circuit board capable of withstanding a large current and a method of manufacturing the circuit board are provided.

Abstract: A method of fabricating electrical feedthroughs selectively removes substrate material from a first side of an electrically conductive substrate (e.g. a bio-compatible metal) to form an array :of electrically conductive posts in a substrate cavity. An electrically insulating material (e.g. a bio-compatible sealing glass) is then flowed to fill the substrate cavity and surround each post, and solidified. The solidified insulating material is then exposed from an opposite second side of the substrate so that each post is electrically isolated from each other as well as the bulk substrate. In this manner a hermetic electrically conductive feedthrough construction is formed having an array of electrical feedthroughs extending between the first and second sides of the substrate from which it was formed.

Abstract: An electrostatic chuck of a stack structure includes a metal layer interposed between insulating layers and a groove formed at a peripheral portion of the electrostatic chuck to have a thickness gradually increasing toward an outside, the groove being covered with a thermally sprayed insulating film. The thermally sprayed film covers at least a portion of the metal layer exposed at an inside of the groove such that the thermally sprayed film does not protrude from the groove.

Abstract: A magnetic resonance coil for transmitting and/or receiving magnetic resonance signals is provided. The magnetic resonance coil includes at least two overlapping coil elements. Coil conductors of the at least two overlapping coil elements intersect in intersection regions and are arranged on a support. Mutually overlapping coil elements of the at least two overlapping coil elements are arranged on different sides of the support. The support is formed from at least three layers of a support material. A cavity that is filled with air or a filler material, the dielectric constant of the filler material being lower than the dielectric constant of the support material, is provided in the intersection regions in a middle layer of the at least three layers.

Abstract: In order to provide a method of manufacturing a multilayer wiring substrate, a base member having a copper foil separably laminated thereon is prepared, and a solder resist layer is formed on the copper foil. Openings are formed in the solder resist layer, and a metal conductor portion is formed in each of the openings. By means of sputtering, a dissimilar metal layer is formed over the surface of the metal conductor portion and the entire surface of the solder resist layer. Copper electroplating is performed so as to form connection terminals and a conductor layer on the dissimilar metal layer. After a build-up step, the base material is removed, whereby the copper foil is exposed, and the exposed copper foil and the metal conductor portion are removed through etching, whereby the surfaces of the external connection terminals are exposed from the openings.

Abstract: A technique for embedding a nanotube in a nanopore is provided. A membrane separates a reservoir into a first reservoir part and a second reservoir part, and the nanopore is formed through the membrane for connecting the first and second reservoir parts. An ionic fluid fills the nanopore, the first reservoir part, and the second reservoir part. A first electrode is dipped in the first reservoir part, and a second electrode is dipped in the second reservoir part. Driving the nanotube into the nanopore causes an inner surface of the nanopore to form a covalent bond to an outer surface of the nanotube via an organic coating so that the inner surface of the nanotube will be the new nanopore with a super smooth surface for studying bio-molecules while they translocate through the nanotube.

Abstract: A toughening agent composition for increasing the hydrophobicity of an organosilicate glass dielectric film when applied to said film. It includes a component capable of alkylating or arylating silanol moieties of the organosilicate glass dielectric film via silylation, and an activating agent selected from the group consisting of an amine, an onium compound and an alkali metal hydroxide.

Abstract: Fundamental interconnect systems for connecting high-speed electronics elements are provided. The interconnect systems consists of signal line, dielectric system with open trench or slot filled up with air or lower dielectric loss material, and the ground plane. The signal line could be for example, microstripline, strip line, coplanar line, single line or differential pairs. The interconnect system can be used for on-chip interconnects or can also be used for off-chip interconnects. The fundamental techniques provided in this invention can also be used for high-speed connectors and high-speed cables.

Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 25 at % carbon. Another capacitor forming method includes forming a support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 20 at % carbon. The support material has a thickness and the opening has an aspect ratio 20:1 or greater within the thickness of the support material.

Abstract: In a method for transferring nanostructures into a substrate, the following order of steps is used: decorating a substrate with nanomaterials (13), etching the substrate (10), applying a coating (15), removing the nanomaterials (13), and etching the substrate (10).

Abstract: A method for manufacturing a wiring structure of a wiring board is provided. In the method, a substrate including an insulation layer and a film disposed on the insulation layer is provided. Next, a barrier layer completely covering the film is formed. Next, an intaglio pattern partially exposing the insulation layer is formed on an outer surface of the barrier layer. Next, an activated layer is formed on the outer surface and in the intaglio pattern. Then, the activated layer on the outer surface is removed, and the activated layer in the intaglio pattern is remained. After the activated layer on the outer surface is removed, a conductive material is formed in the intaglio pattern by using a chemical deposition method. After forming the conductive material, the barrier layer and the film are removed.

Abstract: A sensor device includes a substrate, an IC chip, a sensor element, bonding wires, and a lid. The substrate includes a plurality of metal posts which are disposed so as to be electrically independent of each other and an insulator which is filled in a gap between faces different from first faces and second faces of the plurality of metal posts and integrally fixes the plurality of metal posts. The IC chip has electrode pads on an active face and is fixed to a first metal post. The sensor element has vibrating portions and is supported by the IC chip by bonding a supporting portion to the active face of the IC chip. The bonding wires electrically connect the electrode pads with second metal posts. The lid is disposed so as to cover the IC chip and the sensor element.

Abstract: Methods of forming a capacitor including forming at least one aperture in a support material, forming a titanium nitride material within the at least one aperture, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The support material may then be removed and the titanium nitride material may be oxidized to form a titanium dioxide material. A second conductive material may then be formed over an outer surface of the titanium dioxide material. Capacitors, semiconductor devices and methods of forming a semiconductor device including the capacitors are also disclosed.

Abstract: In a method for fabricating a molecule characterization device, there is formed an aperture in a support structure, and electrical contact pads are formed on a selected surface of the support structure for connection to molecular analysis circuitry. Then at the aperture is provided at least one carbon nanotube. An electrically insulating layer is deposited on walls of the aperture to reduce an extent of the aperture and form a smaller aperture, while depositing substantially no insulating layer on a region of the nanotube that is at the aperture.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

Abstract: Disclosed is an article comprising a layer of nonconductive polymeric material comprising a plurality of integral polymer conduit channels containing a substantially transparent conductive material.

Abstract: The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.

Abstract: Disclosed herein is a heat-radiating substrate. The heat-radiating substrate includes: a metal core layer; a first insulating layer that is formed on one side or both sides of the metal core layer, includes a bather layer contacting with the metal core layer, first and second pores having different diameters, and a porous layer connected with the bather layer; a first circuit layer that is embedded in the first insulating layer, filled in the second pores of the porous layer, and connected to the sides of the second pores; and a second insulating layer that is formed on the porous layer of the first insulating layer. Further, in the heat-radiating substrate of the present embodiment, the first circuit layer is partially filled in the second pores and the second insulating layer is filled in the second pores to make a plane the first insulating layer. In addition, disclosed is a method of manufacturing the heat-radiating substrate.

Abstract: A multilayer printed wiring board manufacturing method including forming conductor posts, which are of substantially uniform thickness and with which the top surfaces are protected by a resist, on a conductor pattern disposed on an upper surface of a build-up layer formed on a core substrate, shaping the conductor posts to have a constriction by adjusting the time of immersion in an etching solution that etches the conductor posts, forming a low elastic modulus layer of substantially the same height as the conductor posts after removing the resist at the top surfaces, and forming mounting electrodes on upper surfaces of the conductor posts.