Abstract: The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound with nanotube particles. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The nanotube particles are dispersed throughout a bottom portion of the first mold compound, and have a higher thermal conductivity than the first mold compound alone. The bottom portion of the first mold compound resides over the active layer and top surfaces of the isolation sections. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.

Abstract: A method of forming an electrical metal contact within a semiconductor layer stack of a vertical cavity surface emitting laser includes forming a contact hole into the semiconductor layer stack. The contact hole has a bottom and a side wall extending from the bottom. The method further includes providing a photoresist mask inside the contact hole. The photoresist mask covers the side wall of the contact hole and has an opening extending to the bottom of the contact hole. The method additionally includes wet-chemical isotropic etching the bottom of the contact hole, depositing a metal on the bottom of the contact hole, and removing the photoresist mask so that the metal on the bottom of the contact hole is left as the electrical metal contact.

Abstract: The present invention discloses a silicon plate, a method for producing a silicon plate, an application of silicon to a fuel cell, a fuel cell stack structure, a fuel cell, and an application of a fuel cell. The silicon plate is made of a doped conductive crystalline silicon material, and has an internal cooling medium flow channel, a front reducing agent flow channel, and/or a back oxidizing agent flow channel, and each of the internal cooling medium flow channel, the front reducing agent flow channel, and/or the back oxidizing agent flow channel is provided with a silicon plate inlet-outlet combination connected to thereof. Compared with a metal plate, a graphite plate, or a composite material plate in the existing technologies, the silicon plate provided in the present invention are more advantageous in service life, costs, efficiency, and power density, and therefore significantly drives mass industrialization of fuel cells.

Abstract: Provided is a method of measuring eccentricity of a blind via hole formed in a printed circuit board including an inner-layer board and an outer-layer board that are bonded by thermocompression bonding. The method includes acquiring, by a microscope camera, an image by photographing a marker which is formed on a surface of the outer-layer board and a blind via hole which is exposed upward through a marker hole formed in a center of the marker with a microscope camera, and measuring, by computing equipment connected to the microscope camera, eccentricity indicating a separation distance and a separation direction from central coordinates of the marker hole to central coordinates of the blind via hole using a distance between an end point of the marker hole and an end point of the blind via hole which are included in the image.

Abstract: The disclosed plasma processing apparatus includes a plasma processing chamber, a substrate support, a bias power source, and a radio frequency power source. The substrate support is disposed in the plasma processing chamber and includes an electrode. The bias power source is coupled to the electrode and configured to generate a bias power having a first frequency. The radio frequency power source is coupled to the plasma processing chamber and configured to generate a radio frequency power having a second frequency higher than the first frequency. The radio frequency power has a first power level in a first period within one cycle of the bias power and has a second power level lower than the first power level in a second period within one cycle of the bias power.

Abstract: The present invention discloses an electrophoretic chip comprising: (a) a non-conductive substrate designed to support elements of said electrophoretic chip; (b) an electrode structure for conducting current through said electrophoretic chip, printed on said non-conductive substrate and comprising a counter electrode and at least one working electrode, each electrode comprising a conductive low-resistance ink layer printed on the non-conductive substrate, and a carbon ink layer printed on top of and fully or partially covering said conductive low-resistance ink layer; (c) a dielectric ink insulator layer placed on top of, and covering, said electrode structure, said dielectric ink insulator layer having at least one opening above the counter electrode and at least one opening above said at least one working electrode, thereby forming at least one addressable location; and (d) a molecule capturing matrix spotted on and covering said at least one addressable location, thereby creating at least one microgel regi

Abstract: A method of processing a substrate is provided. The substrate includes an etching target region and a patterned region. The patterned region is provided on the etching target region. In the method, an organic film is formed on a surface of the substrate. Subsequently, the etching target region is etched by plasma generated from a processing gas. The organic film is formed in a state that the substrate is placed in a processing space within a chamber. When the organic film is formed, a first gas containing a first organic compound is supplied toward the substrate, and then, a second gas containing a second organic compound is supplied toward the substrate. An organic compound constituting the organic film is generated by polymerization of the first organic compound and the second organic compound.

Abstract: The present invention provides a display substrate polyimide film having: remarkably improved insulation characteristics; inner pores, included in the polyimide film, of which the maximum size is 10 nm or less; and a high maximum dielectric breakdown voltage of 350 V/?m or more. The polyimide film according to the present invention has improved insulation characteristics so as to be capable of suppressing the generation of a current fluctuation of TFTs according to the long-term driving of a TFT device in a display such as an OLED, thereby enabling the deterioration of the contrast of a display to be reduced.

Abstract: A printed circuit board is provided with multiple electrically conductive layers which are separated from each other by electrically non-conductive layers. At least one electrically conductive outer layer and multiple electrically conductive intermediate layers are provided. At least one electrically conductive through-connection is provided between an electrically conductive outer layer and an electrically conductive intermediate layer. The printed circuit board consists of at least one first multilayer PCB and one second multilayer PCB. The first multilayer PCB is formed from multiple electrically conductive layers and multiple electrically non-conductive layers, and the second multilayer PCB has at least one electrically conductive layer and at least one electrically non-conductive layer. The multilayer PCBs are connected to each other.

Abstract: A composite article includes a conductive layer with nanowires on at least a portion of a flexible substrate, wherein the conductive layer has a conductive surface. A patterned layer of a low surface energy material is on a first region of the conductive surface. An overcoat layer free of conductive particulates is on a first portion of a second region of the conductive surface unoccupied by the patterned layer. A via is in a second portion of the second region of the conductive surface between an edge of the patterned layer of the low surface energy material and the overcoat layer. A conductive material is in the via to provide an electrical connection to the conductive surface.

Abstract: The disclosure generally relates to a method of creating patterned metallic circuits (e.g., silver circuits) on a substrate (e.g., a ceramic substrate). A porous metal interlayer (e.g., porous nickel) is applied to the substrate to improve wetting and adhesion of the patterned metal circuit material to the substrate. The substrate is heated to a temperature sufficient to melt the patterned metal circuit material but not the porous metal interlayer. Spreading of molten metal circuit material on the substrate is controlled by the porous metal interlayer, which can itself be patterned, such as having a defined circuit pattern. Thick-film silver or other metal circuits can be custom designed in complicated shapes for high temperature/high power applications. The materials designated for the circuit design allows for a low-cost method of generating silver circuits other metal circuits on a ceramic substrate.

Abstract: A method for manufacturing a semiconductor device in which a semiconductor substrate is provided, including a SOI-wafer having a carrier layer defining a rear side, a functional layer defining a front side. An insulation layer is situated between the carrier layer and functional layer. The functional layer includes a functional area having functional structures. The front side is masked, a first mask opening defines an interior area containing the functional area. The functional layer is removed by etching the front side. The rear side is masked, a second mask opening being configured, and a circumferential edge of the second mask opening is spaced outwardly relative to an outer circumferential edge of the interior area. The carrier layer and the insulation layer are removed at least in the area of the second-mask opening by etching to expose the interior area.

Abstract: A novel pretreating liquid for electroless plating which is used simultaneously with reduction treatment after roughening treatment of a filler-containing insulating resin substrate. A pretreating liquid for electroless plating is used simultaneously with reduction treatment when an insulating resin substrate containing a filler is roughened and residues generated on the insulating resin substrate are reduced. The pretreating liquid comprises: a reducing agent; and at least one selected from the group consisting of ethylene-based glycol ether represented by CmH(2m+1)-(OC2H4)n-OH (m=an integer of 1 to 4, n=an integer of 1 to 4) and propylene-based glycol ether represented by CxH(2x+1)-(OC3H6)y-OH (x=an integer of 1 to 4, y= an integer of 1 to 3).

Abstract: A gyroscope and method for navigating using the gyroscope can include a substrate that can define a cavity. The cavity can be placed under a vacuum, and a birefringent microrotor can be located in the cavity. A light source can direct light through the substrate and into the cavity to establish an optical spring effect, which act on the microrotor to establish an initial reference position, as well as to establish rotational and translational motion of said microrotor. A receiver can detect light that has passed through said cavity. Changes in light patterns that can be detected at the receiver can be indicative of a change in position of the microrotor. The change and rate of change in position of the microrotor can be used for inertial navigation.

Abstract: A technique for repairing a dual walled component comprising a spar comprising a plurality of pedestals and a coversheet attached to the plurality of pedestals may include removing a damaged portion of the coversheet from the dual walled component to expose a plurality of exposed pedestals and define a repair location and an adjacent coversheet portion. The technique also may include filling space between the plurality of exposed pedestals with a stop material. The stop material may define a surface substantially aligned with a pedestal-contacting surface of the adjacent coversheet portion. In some examples, the method additionally includes positioning a braze material on the surface of the stop material and attaching the braze material to the plurality of exposed pedestals and adjacent coversheet portion to form a repaired coversheet portion.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a first contact plug and a first via plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The first contact plug is positioned over the source/drain structure. The first via plug is positioned over the first contact plug. The first via plug includes a first group IV element.

Abstract: To overcome the problem of the fiber weave effect desynchronizing differential signals in a pair of traces of approximately the same length in a printed circuit board, the pair of traces can be routed to traverse largely parallel paths that are above one another in the printed circuit board. The material between the paths can include weaved fiber bundles. The material on opposite sides of the paths, surrounding the pair of traces and the weaved fiber bundles, can include resin-rich material. As a result, the pair of traces are directly adjacent to the same materials, which can allow signals in the traces to propagate at the same speed, and prevent desynchronization of differential signals traversing the paths. The path length difference associated with traversing to different depths can be compensated with a relatively small in-plane diagonal jog of one of the traces.

Abstract: Disclosed herein are techniques to incorporate a light bar for a backlit liquid crystal display (LCD) onto a display carrier for the display. In particular, a display carrier for a display stack may have traces formed thereon and light emitting diodes (LEDs) disposed on the display carrier operably coupled to the traces. The LEDs to provide light to illuminate pixels in the display.

Abstract: A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.

Abstract: A perforated substrate having a first surface, a second (opposite) surface, a plurality of through holes running through the substrate from the first surface to the second surface and an etching object arranged on the first surface, is processed by forming a coating layer containing a resin material on the etching object, then allowing part of the resin material to drop into each of the through holes so as to close each of the through holes at least partly with the dropped resin material, then patterning the coating layer such that the coating layer is left on each of the through holes as mask while at least part of the coating layer covering the etching object is removed to expose the etching object; and etching the exposed etching object under a condition where each of the through holes is closed at least partly with the resin material.

Abstract: Methods for gapfill of high aspect ratio features are described. A first film is deposited on the bottom and upper sidewalls of a feature. The first film is etched from the sidewalls of the feature and the first film in the bottom of the feature is treated to form a second film. The deposition, etch and treat processes are repeated to fill the feature.

Abstract: A method for forming cavity of bulk acoustic wave resonator comprising following steps of: forming a sacrificial epitaxial structure mesa on a compound semiconductor substrate; forming an insulating layer on the sacrificial epitaxial structure mesa and the compound semiconductor substrate; polishing the insulating layer by a chemical-mechanical planarization process to form a polished surface; forming a bulk acoustic wave resonance structure on the polished surface, which comprises following steps of: forming a bottom electrode layer on the polished surface; forming a piezoelectric layer on the bottom electrode layer; and forming a top electrode layer on the piezoelectric layer, wherein the bulk acoustic wave resonance structure is located above the sacrificial epitaxial structure mesa; and etching the sacrificial epitaxial structure mesa to form a cavity, wherein the cavity is located under the bulk acoustic wave resonance structure.

Abstract: The present disclosure provides an MEMS microphone, including a substrate having a back cavity and a capacitor system fixedly disposed on the substrate, where the capacitor system includes a backplane and a vibrating diaphragm that are spaced apart from each other, the backplane includes a backplane insulation layer and a backplane conducting layer disposed on the backplane insulation layer, an outer edge of the backplane conducting layer is provided with a notch, the backplane insulation layer is provided with a first through hole, the first through hole includes a first sound hole disposed in a location corresponding to the notch, and the notch is in communication with the first sound hole. The present disclosure reduces stress concentration of the backplane and reducing a risk of structural failure such as breaking of the backplane.

Abstract: A method of fabricating a wire grid polarizer includes sequentially depositing a conductive wire pattern layer, and a plurality of guide patterns which forms one or more trenches therebetween on the conductive wire pattern layer, hydrophobically treating surfaces of the conductive wire pattern layer exposed in the trenches, and the guide patterns, coating the hydrophobically treated conductive wire pattern layer in the trenches with a neutral layer to partially fill the trenches, filling a remainder of the trenches with a block copolymer of two monomers with different etching rates, aligning the block copolymer filled in the trenches, selectively removing blocks of one monomer among the two monomers from the aligned block copolymer, and patterning the conductive wire pattern layer by using blocks of the other monomer among the two monomers remaining in the trenches and the guide patterns as a mask.

Abstract: Methods of fabricating semiconductor devices may include forming a hardmask layer including a photosensitive hardmask material on lower structures. The hardmask layer may include a lower portion and an upper portion thereon. An exposing and developing process may be performed on the hardmask layer to remove the upper portion of the hardmask layer and thereby form a hardmask structure with a substantially flat top surface.

Abstract: A method for dividing a wafer having a wiring layer including Cu on the front side, the front side of the wafer being partitioned by a plurality of crossing division lines to define a plurality of separate regions where a plurality of devices are formed. The method includes a laser processed groove forming step of applying a laser beam to the wiring layer along each division line to thereby remove the wiring layer along each division line and form a laser processed groove along each division line, a cutting step of using a cutting blade having a thickness smaller than the width of each laser processed groove to fully cut the wafer along each laser processed groove after performing the laser processed groove forming step, and a dry etching step of dry-etching at least each laser processed groove after performing the laser processed groove forming step.

Abstract: Various embodiments of the present disclosure are directed to structures comprising a nanostructure layer that includes a plurality of transparent conductors and coating layer formed on a surface thereof. In some embodiments, the coating layer includes one or more conductive plugs having outer and inner surfaces. The inner surface the plug is placed in electrical communication with the nanostructure layer and the outer surface forms conductive surface contacts proximate an outer surface of the coating layer. In some embodiments, the structure includes a polarizer and is used as a shielding layer in flat panel electrochromic displays, such as liquid crystal displays, touch panels, and the like.

Abstract: A method for forming metal on a dielectric includes forming a seed layer on a surface including a reactant element. A first metal layer is formed on the seed layer wherein the first metal layer wets the seed layer. A second metal layer is formed on the first metal layer wherein the second metal layer wets the first metal layer. Diffuse the reactant element of the seed layer into the first metal layer by annealing to convert the first metal layer to a dielectric layer.

Abstract: A method of filling a germanium film in a recess on a substrate to be processed having an insulating film on which the recess is formed on a surface of the substrate, includes forming a first germanium film so as to fill the recess by supplying a germanium raw material gas to the substrate, etching the first germanium film with an etching gas containing an excited H2 gas or NH3 gas, and forming a second germanium film on the first germanium film so as to fill the recess by supplying a germanium raw material gas.

Abstract: A directed vapor deposition (DVD) method and system for applying at least one bond coating on at least one substrate for thermal barrier coating systems. To overcome the limitations incurred by conventional methods, the DVD system uses an electron beam directed vapor deposition (DVD) technique to evaporate and deposit compositionally and morphologically controlled bond coats at high rate. The present DVD system uses the combination of an electron beam and a combined inert gas/reactive gas carrier jet of controlled composition to create engineering films. In this system, the vaporized material can be entrained in the carrier gas jet and deposited onto the substrate at a high rate and with high materials utilization efficiency. The velocity and flux of the gas atoms entering the chamber, the nozzle parameters, and the operating chamber pressure can all be significantly varied, facilitating wide processing condition variation and allowing for improved control over the properties of the deposited layer.

Abstract: A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer over the source/drain, and forming an inter-level dielectric (ILD) layer over the sacrificial layer. The method further includes forming trenches that extend partially into the sacrificial layer, removing the sacrificial layer to expose an upper surface of the source/drain, and filling the trenches with at least one conducting material. The sacrificial layer is germanium (Ge) and the at least one conducting material includes three conducting materials.

Abstract: The electronically switchable MEMS valve includes a housing formed from soft magnetic material and defining a fluid flow path therethrough. A magnetic field generating member is mounted within the housing and connected to a source of electrical power. A MEMS valve portion is mounted within the magnetic field generating member, has a valve closing member movably mounted therein, and defines a portion of the fluid flow path therethrough. The valve closing element is movable between a closed position wherein the fluid flow path is blocked, and an open position wherein the fluid flow path is not blocked. When an electric current is removed from the magnetic field generating member, the valve closing element is configured to move to and remain in the one of the closed position and the open position to which the valve closing element is the closest when the electric current is removed.

Abstract: The present disclosure relates to a method for pattern formation on a substrate. An example embodiment includes a method for pattern formation. The method includes providing a photoresist layer on a composite substrate. The method also includes patterning the photoresist layer by lithography to define a plurality of parallel stripe photoresist structures. The method further includes providing a block copolymer on and along the composite substrate, in between the parallel stripe photoresist structures. The block copolymer includes a first component and a second component. The method additionally includes subjecting the block copolymer to predetermined conditions to cause phase separation of the first component and the second component. In addition, the method includes performing a sequential infiltration synthesis process. Still further, the method includes selectively removing the parallel stripe photoresist structures. Additionally, the method includes defining a core stripe structure.

Abstract: A method includes providing a substrate; forming mandrel patterns over the substrate; and forming spacers on sidewalls of the mandrel patterns. The method further includes removing the mandrel patterns, thereby forming trenches that are at least partially surrounded by the spacers. The method further includes depositing a copolymer material in the trenches, wherein the copolymer material is directed self-assembling; and inducing microphase separation within the copolymer material, thereby defining a first constituent polymer surrounded by a second constituent polymer. The mandrel patterns have restricted sizes and a restricted configuration. The first constituent polymer includes cylinders arranged in a rectangular or square array.

Abstract: A method including spanning a relatively larger opening (50) with a support structure (72) to divide the larger opening into a plurality of relatively smaller openings (78); placing superalloy powder across the smaller openings and in contact with the support structure; and melting the superalloy powder to form a cladding layer (104) that spans the opening and is metallurgically bonded to the support structure.

Abstract: Disclosed herein is a mechanism for forming an interconnect comprising forming a connector on an interconnect disposed on a first surface of a first substrate and applying a nonconductive material in a non-liquid form over the interconnect after forming the connector. The nonconductive material covers at least a lower portion of the interconnect, and at least a portion of the interconnect is exposed. The nonconductive material is formed around the connector by pressing the nonconductive material over the connector with a roller. An angle between a top surface of the nonconductive material and a connector sidewall between about 65 degrees and about 135 degrees. The nonconductive material may be formed to extend under the connector.

Abstract: A method is for making an electronic device including forming a multilayer circuit board having a non-planar three-dimensional shape defining a membrane switch recess therein, the multilayer circuit board including at least one liquid crystal polymer (LCP) layer, and at least one electrically conductive pattern layer thereon defining at least one membrane switch electrode adjacent the membrane switch recess to define a membrane switch. The method also includes filling the membrane switch recess with a compressible dielectric material, and positioning at least one biasing member in the membrane switch recess.

Abstract: A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.

Abstract: A method of forming a skip-via, including, forming a first dielectric layer on a first metallization layer, forming a second metallization layer on the first dielectric layer and a second dielectric layer on the second metallization layer, removing a section of the second dielectric layer to form a via to the second metallization layer, removing a portion of the second metallization layer to form an aperture, and removing an additional portion of the second metallization layer to form an exclusion zone.

Abstract: A method of fabricating a wire grid polarizer includes sequentially depositing a conductive wire pattern layer, and a plurality of guide patterns which forms one or more trenches therebetween on the conductive wire pattern layer, hydrophobically treating surfaces of the conductive wire pattern layer exposed in the trenches, and the guide patterns, coating the hydrophobically treated conductive wire pattern layer in the trenches with a neutral layer to partially fill the trenches, filling a remainder of the trenches with a block copolymer of two monomers with different etching rates, aligning the block copolymer filled in the trenches, selectively removing blocks of one monomer among the two monomers from the aligned block copolymer, and patterning the conductive wire pattern layer by using blocks of the other monomer among the two monomers remaining in the trenches and the guide patterns as a mask.

Abstract: A printed circuit board with high-capacity copper circuit includes a conductive trace, a first protecting layer, and a second protecting layer formed on opposite sides of the conductive trace. The conductive trace includes a base conductive trace pattern, a first conductive trace pattern, and a second conductive trace pattern. The first and second conductive trace patterns are directly formed on opposite surfaces of the base copper conductive trace pattern. A trace width of the first conductive trace pattern is the same as a line width of the second conductive trace pattern.

Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

Abstract: The present invention is a sacrificial-film removal method of removing a sacrificial film from a surface of a substrate provided with a plurality of struts and the sacrificial film embedded between the plurality of struts, including: a wet etching step where the sacrificial film is removed to its halfway depth by supplying an etchant to the surface of the substrate; a rinse step where a residue adhering to the surface of the substrate is washed out by supplying a rinsing liquid to the surface of the substrate after the wet etching step; a drying step where a liquid component on the surface of the substrate is removed after the rinse step; and a dry etching step where the sacrificial film remaining on the surface of the substrate is removed by supplying an etching gas to the surface of the substrate after the drying step.

Abstract: Method of manufacturing a semiconductor device is described that uses sidewall protection of a recessed feature to prevent loss of critical dimension during a cleaning process to remove etch residue. According to one embodiment, the method includes providing a substrate containing a film thereon having a recessed feature with a sidewall and a bottom portion, depositing a conformal film on the sidewall and on the bottom portion, removing the conformal film from the bottom portion in an anisotropic etching process, where the remaining conformal film forms a protection film on the sidewall, and performing a cleaning process that removes etch residue from the recessed feature without etching the protection film or the sidewall.

Abstract: A method for making patterns includes forming on a substrate surface a first mask delimiting at least two areas to be metallised; forming an assembly guide above the first mask, the assembly guide delimiting a surface covering two contact areas belonging respectively to the two areas to be metallised; depositing on the surface a block copolymer layer; reorganising the block copolymer layer; eliminating one of the phases of the reorganised block copolymer layer, resulting in a plurality of holes extending into the block copolymer layer above the two contact areas and a portion of the first mask arranged between the two contact areas; widening the holes of the block copolymer layer until a continuous trench is formed above the two contact areas and the portion of the first mask; transferring, through the first mask, the continuous trench onto the surface of the substrate to form patterns corresponding to the contact areas.

Abstract: Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the at least one soluble block laterally aligned with the trench and positioned within a matrix of the at least one insoluble block. The self-assembled pattern may be exposed to a metal oxide precursor that impregnates the at least one soluble block. The metal oxide precursor may be oxidized to form a metal oxide. The self-assembled pattern may be removed to form a pattern of metal oxide lines on the substrate surface. Semiconductor device structures are also described.

Abstract: A method of manufacturing an optical waveguide with a vertical slot including the steps of a) providing a substrate successively including an electric insulator layer and a crystalline semiconductor layer, b) forming a trench on the semiconductor layer to expose the electric insulator layer and defining first and second semiconductor areas on either side, step b) being executed so that the first semiconductor area has a lateral edge extending across the entire thickness of the semiconductor layer, c) forming the dielectric layer having the predetermined width across the entire thickness of the lateral edge, the method being remarkable in that the trench formed at step b) is configured so that the second semiconductor area forms a seed layer.

Abstract: A microvalve device and fluid flow control method, the microvalve device comprising: a microvalve body, the microvalve body being composed of multiple layers and comprising a first layer (1) and a second layer (2) bonded with the first layer (1), the second layer (2) having a plurality of fluid ports (7, 8, 9); a cavity (6) disposed between the first layer and the second layer; a plurality of actuators (3, 4, 5) respectively disposed corresponding to each fluid port, the plurality of actuators (3, 4, 5) controlling the opening and closing of the plurality of fluid ports (7, 8, 9). The fluid flow control method comprising: respectively employing a plurality of actuators to independently control the opening and closing of a plurality of fluid ports.

Abstract: A patterning method includes forming an etch-target layer on a substrate, forming mask patterns on the etch-target layer, and etching the etch-target layer using the mask patterns as an etch mask to form patterns spaced apart from each other. The etching process of the etch-target layer includes irradiating the etch-target layer with an ion beam, whose incident energy ranges from 600 eV to 10 keV. A recess region is formed in the etch-target layer between the mask patterns, and the ion beam is incident onto a bottom surface of the recess region at a first angle with respect to a top surface of the substrate and is incident onto an inner side surface of the recess region at a second angle with respect to the inner side surface of the recess region. The first angle ranges from 50° to 90° and the second angle ranges from 0° to 40°.