Forming Or Treating Of Groove Or Through Hole Patents (Class 216/17)
  • Patent number: 10950455
    Abstract: A method for manufacturing a semiconductor device in which a semiconductor substrate is provided, including a SOI-wafer having a carrier layer defining a rear side, a functional layer defining a front side. An insulation layer is situated between the carrier layer and functional layer. The functional layer includes a functional area having functional structures. The front side is masked, a first mask opening defines an interior area containing the functional area. The functional layer is removed by etching the front side. The rear side is masked, a second mask opening being configured, and a circumferential edge of the second mask opening is spaced outwardly relative to an outer circumferential edge of the interior area. The carrier layer and the insulation layer are removed at least in the area of the second-mask opening by etching to expose the interior area.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 16, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Zhenyu Wu, Jens Schindele, Torsten Kramer
  • Patent number: 10927463
    Abstract: A novel pretreating liquid for electroless plating which is used simultaneously with reduction treatment after roughening treatment of a filler-containing insulating resin substrate. A pretreating liquid for electroless plating is used simultaneously with reduction treatment when an insulating resin substrate containing a filler is roughened and residues generated on the insulating resin substrate are reduced. The pretreating liquid comprises: a reducing agent; and at least one selected from the group consisting of ethylene-based glycol ether represented by CmH(2m+1)-(OC2H4)n-OH (m=an integer of 1 to 4, n=an integer of 1 to 4) and propylene-based glycol ether represented by CxH(2x+1)-(OC3H6)y-OH (x=an integer of 1 to 4, y= an integer of 1 to 3).
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: February 23, 2021
    Assignee: C. UYEMURA & CO., LTD.
    Inventors: Yoshikazu Saijo, Hisamitsu Yamamoto, Nobuhiko Naka
  • Patent number: 10866099
    Abstract: A gyroscope and method for navigating using the gyroscope can include a substrate that can define a cavity. The cavity can be placed under a vacuum, and a birefringent microrotor can be located in the cavity. A light source can direct light through the substrate and into the cavity to establish an optical spring effect, which act on the microrotor to establish an initial reference position, as well as to establish rotational and translational motion of said microrotor. A receiver can detect light that has passed through said cavity. Changes in light patterns that can be detected at the receiver can be indicative of a change in position of the microrotor. The change and rate of change in position of the microrotor can be used for inertial navigation.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: December 15, 2020
    Assignee: United States of America as represented by the Secretary of the Navy
    Inventors: Michael Mazilu, Joanna Ptasinski, Alexandru Hening
  • Patent number: 10766105
    Abstract: A technique for repairing a dual walled component comprising a spar comprising a plurality of pedestals and a coversheet attached to the plurality of pedestals may include removing a damaged portion of the coversheet from the dual walled component to expose a plurality of exposed pedestals and define a repair location and an adjacent coversheet portion. The technique also may include filling space between the plurality of exposed pedestals with a stop material. The stop material may define a surface substantially aligned with a pedestal-contacting surface of the adjacent coversheet portion. In some examples, the method additionally includes positioning a braze material on the surface of the stop material and attaching the braze material to the plurality of exposed pedestals and adjacent coversheet portion to form a repaired coversheet portion.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: September 8, 2020
    Assignee: Rolls-Royce Corporation
    Inventors: Joseph Peter Henderkott, Raymond Ruiwen Xu
  • Patent number: 10763168
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a first contact plug and a first via plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The first contact plug is positioned over the source/drain structure. The first via plug is positioned over the first contact plug. The first via plug includes a first group IV element.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Po Hsieh, Su-Hao Liu, Hong-Chih Liu, Jing-Huei Huang, Jie-Huang Huang, Lun-Kuang Tan, Huicheng Chang, Liang-Yin Chen, Kuo-Ju Chen
  • Patent number: 10716209
    Abstract: To overcome the problem of the fiber weave effect desynchronizing differential signals in a pair of traces of approximately the same length in a printed circuit board, the pair of traces can be routed to traverse largely parallel paths that are above one another in the printed circuit board. The material between the paths can include weaved fiber bundles. The material on opposite sides of the paths, surrounding the pair of traces and the weaved fiber bundles, can include resin-rich material. As a result, the pair of traces are directly adjacent to the same materials, which can allow signals in the traces to propagate at the same speed, and prevent desynchronization of differential signals traversing the paths. The path length difference associated with traversing to different depths can be compensated with a relatively small in-plane diagonal jog of one of the traces.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Eng Huat Goh, Jackson Chung Peng Kong, Khang Choong Yong, Min Suet Lim
  • Patent number: 10690836
    Abstract: Disclosed herein are techniques to incorporate a light bar for a backlit liquid crystal display (LCD) onto a display carrier for the display. In particular, a display carrier for a display stack may have traces formed thereon and light emitting diodes (LEDs) disposed on the display carrier operably coupled to the traces. The LEDs to provide light to illuminate pixels in the display.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: June 23, 2020
    Assignee: INTEL CORPORATION
    Inventor: Arvind Sundaram
  • Patent number: 10685931
    Abstract: A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: June 16, 2020
    Assignee: CATLAM LLC
    Inventors: Kenneth S. Bahl, Konstantine Karavakis
  • Patent number: 10632754
    Abstract: A perforated substrate having a first surface, a second (opposite) surface, a plurality of through holes running through the substrate from the first surface to the second surface and an etching object arranged on the first surface, is processed by forming a coating layer containing a resin material on the etching object, then allowing part of the resin material to drop into each of the through holes so as to close each of the through holes at least partly with the dropped resin material, then patterning the coating layer such that the coating layer is left on each of the through holes as mask while at least part of the coating layer covering the etching object is removed to expose the etching object; and etching the exposed etching object under a condition where each of the through holes is closed at least partly with the resin material.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: April 28, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Masaya Uyama, Tadanobu Nagami
  • Patent number: 10626495
    Abstract: Methods for gapfill of high aspect ratio features are described. A first film is deposited on the bottom and upper sidewalls of a feature. The first film is etched from the sidewalls of the feature and the first film in the bottom of the feature is treated to form a second film. The deposition, etch and treat processes are repeated to fill the feature.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: April 21, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Rui Cheng, Abhijit Basu Mallick, Pramit Manna
  • Patent number: 10594286
    Abstract: A method for forming cavity of bulk acoustic wave resonator comprising following steps of: forming a sacrificial epitaxial structure mesa on a compound semiconductor substrate; forming an insulating layer on the sacrificial epitaxial structure mesa and the compound semiconductor substrate; polishing the insulating layer by a chemical-mechanical planarization process to form a polished surface; forming a bulk acoustic wave resonance structure on the polished surface, which comprises following steps of: forming a bottom electrode layer on the polished surface; forming a piezoelectric layer on the bottom electrode layer; and forming a top electrode layer on the piezoelectric layer, wherein the bulk acoustic wave resonance structure is located above the sacrificial epitaxial structure mesa; and etching the sacrificial epitaxial structure mesa to form a cavity, wherein the cavity is located under the bulk acoustic wave resonance structure.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: March 17, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chia-Ta Chang, Chun-Ju Wei, Kuo-Lung Weng
  • Patent number: 10582307
    Abstract: The present disclosure provides an MEMS microphone, including a substrate having a back cavity and a capacitor system fixedly disposed on the substrate, where the capacitor system includes a backplane and a vibrating diaphragm that are spaced apart from each other, the backplane includes a backplane insulation layer and a backplane conducting layer disposed on the backplane insulation layer, an outer edge of the backplane conducting layer is provided with a notch, the backplane insulation layer is provided with a first through hole, the first through hole includes a first sound hole disposed in a location corresponding to the notch, and the notch is in communication with the first sound hole. The present disclosure reduces stress concentration of the backplane and reducing a risk of structural failure such as breaking of the backplane.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: March 3, 2020
    Assignee: AAC Technologies Pte. Ltd.
    Inventors: Yang Bai, Rui Zhang
  • Patent number: 10509150
    Abstract: A method of fabricating a wire grid polarizer includes sequentially depositing a conductive wire pattern layer, and a plurality of guide patterns which forms one or more trenches therebetween on the conductive wire pattern layer, hydrophobically treating surfaces of the conductive wire pattern layer exposed in the trenches, and the guide patterns, coating the hydrophobically treated conductive wire pattern layer in the trenches with a neutral layer to partially fill the trenches, filling a remainder of the trenches with a block copolymer of two monomers with different etching rates, aligning the block copolymer filled in the trenches, selectively removing blocks of one monomer among the two monomers from the aligned block copolymer, and patterning the conductive wire pattern layer by using blocks of the other monomer among the two monomers remaining in the trenches and the guide patterns as a mask.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: December 17, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Eun Ae Kwak, Min Hyuck Kang, Moon Gyu Lee
  • Patent number: 10503072
    Abstract: Methods of fabricating semiconductor devices may include forming a hardmask layer including a photosensitive hardmask material on lower structures. The hardmask layer may include a lower portion and an upper portion thereon. An exposing and developing process may be performed on the hardmask layer to remove the upper portion of the hardmask layer and thereby form a hardmask structure with a substantially flat top surface.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: December 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: DoYoung Kim, Kyoungsil Park
  • Patent number: 10354919
    Abstract: A method for dividing a wafer having a wiring layer including Cu on the front side, the front side of the wafer being partitioned by a plurality of crossing division lines to define a plurality of separate regions where a plurality of devices are formed. The method includes a laser processed groove forming step of applying a laser beam to the wiring layer along each division line to thereby remove the wiring layer along each division line and form a laser processed groove along each division line, a cutting step of using a cutting blade having a thickness smaller than the width of each laser processed groove to fully cut the wafer along each laser processed groove after performing the laser processed groove forming step, and a dry etching step of dry-etching at least each laser processed groove after performing the laser processed groove forming step.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: July 16, 2019
    Assignee: DISCO CORPORATION
    Inventors: Tomotaka Tabuchi, Kentaro Odanaka, Satoshi Kumazawa, Senichi Ryo, Yuki Ogawa
  • Patent number: 10324352
    Abstract: Various embodiments of the present disclosure are directed to structures comprising a nanostructure layer that includes a plurality of transparent conductors and coating layer formed on a surface thereof. In some embodiments, the coating layer includes one or more conductive plugs having outer and inner surfaces. The inner surface the plug is placed in electrical communication with the nanostructure layer and the outer surface forms conductive surface contacts proximate an outer surface of the coating layer. In some embodiments, the structure includes a polarizer and is used as a shielding layer in flat panel electrochromic displays, such as liquid crystal displays, touch panels, and the like.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: June 18, 2019
    Assignee: Cambrios Film Solutions Corporation
    Inventors: Paul Mansky, Kalpesh Biyani
  • Patent number: 10294561
    Abstract: A method for forming metal on a dielectric includes forming a seed layer on a surface including a reactant element. A first metal layer is formed on the seed layer wherein the first metal layer wets the seed layer. A second metal layer is formed on the first metal layer wherein the second metal layer wets the first metal layer. Diffuse the reactant element of the seed layer into the first metal layer by annealing to convert the first metal layer to a dielectric layer.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Guohan Hu, Daniel C. Worledge
  • Patent number: 10269561
    Abstract: A method of filling a germanium film in a recess on a substrate to be processed having an insulating film on which the recess is formed on a surface of the substrate, includes forming a first germanium film so as to fill the recess by supplying a germanium raw material gas to the substrate, etching the first germanium film with an etching gas containing an excited H2 gas or NH3 gas, and forming a second germanium film on the first germanium film so as to fill the recess by supplying a germanium raw material gas.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: April 23, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroki Murakami
  • Patent number: 10260143
    Abstract: A directed vapor deposition (DVD) method and system for applying at least one bond coating on at least one substrate for thermal barrier coating systems. To overcome the limitations incurred by conventional methods, the DVD system uses an electron beam directed vapor deposition (DVD) technique to evaporate and deposit compositionally and morphologically controlled bond coats at high rate. The present DVD system uses the combination of an electron beam and a combined inert gas/reactive gas carrier jet of controlled composition to create engineering films. In this system, the vaporized material can be entrained in the carrier gas jet and deposited onto the substrate at a high rate and with high materials utilization efficiency. The velocity and flux of the gas atoms entering the chamber, the nozzle parameters, and the operating chamber pressure can all be significantly varied, facilitating wide processing condition variation and allowing for improved control over the properties of the deposited layer.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: April 16, 2019
    Assignee: University of Virginia Patent Foundation
    Inventors: Derek D. Hass, Haydn N. G. Wadley, Kumar P. Dharmasena, Yosef Marciano
  • Patent number: 10217707
    Abstract: A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer over the source/drain, and forming an inter-level dielectric (ILD) layer over the sacrificial layer. The method further includes forming trenches that extend partially into the sacrificial layer, removing the sacrificial layer to expose an upper surface of the source/drain, and filling the trenches with at least one conducting material. The sacrificial layer is germanium (Ge) and the at least one conducting material includes three conducting materials.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10190702
    Abstract: The electronically switchable MEMS valve includes a housing formed from soft magnetic material and defining a fluid flow path therethrough. A magnetic field generating member is mounted within the housing and connected to a source of electrical power. A MEMS valve portion is mounted within the magnetic field generating member, has a valve closing member movably mounted therein, and defines a portion of the fluid flow path therethrough. The valve closing element is movable between a closed position wherein the fluid flow path is blocked, and an open position wherein the fluid flow path is not blocked. When an electric current is removed from the magnetic field generating member, the valve closing element is configured to move to and remain in the one of the closed position and the open position to which the valve closing element is the closest when the electric current is removed.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: January 29, 2019
    Assignee: DunAn Microstaq, Inc.
    Inventors: E. Nelson Fuller, Parthiban Arunasalam, Joe A. Ojeda, Chen Yang
  • Patent number: 10079145
    Abstract: The present disclosure relates to a method for pattern formation on a substrate. An example embodiment includes a method for pattern formation. The method includes providing a photoresist layer on a composite substrate. The method also includes patterning the photoresist layer by lithography to define a plurality of parallel stripe photoresist structures. The method further includes providing a block copolymer on and along the composite substrate, in between the parallel stripe photoresist structures. The block copolymer includes a first component and a second component. The method additionally includes subjecting the block copolymer to predetermined conditions to cause phase separation of the first component and the second component. In addition, the method includes performing a sequential infiltration synthesis process. Still further, the method includes selectively removing the parallel stripe photoresist structures. Additionally, the method includes defining a core stripe structure.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: September 18, 2018
    Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D
    Inventors: Boon Teik Chan, Arjun Singh
  • Patent number: 10056265
    Abstract: A method includes providing a substrate; forming mandrel patterns over the substrate; and forming spacers on sidewalls of the mandrel patterns. The method further includes removing the mandrel patterns, thereby forming trenches that are at least partially surrounded by the spacers. The method further includes depositing a copolymer material in the trenches, wherein the copolymer material is directed self-assembling; and inducing microphase separation within the copolymer material, thereby defining a first constituent polymer surrounded by a second constituent polymer. The mandrel patterns have restricted sizes and a restricted configuration. The first constituent polymer includes cylinders arranged in a rectangular or square array.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Huei Weng, Kuan-Hsin Lo, Wei-Liang Lin, Chi-Cheng Hung
  • Patent number: 10046416
    Abstract: A method including spanning a relatively larger opening (50) with a support structure (72) to divide the larger opening into a plurality of relatively smaller openings (78); placing superalloy powder across the smaller openings and in contact with the support structure; and melting the superalloy powder to form a cladding layer (104) that spans the opening and is metallurgically bonded to the support structure.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: August 14, 2018
    Assignee: SIEMENS ENERGY, INC.
    Inventors: Gerald J. Bruck, Ahmed Kamel
  • Patent number: 10015888
    Abstract: Disclosed herein is a mechanism for forming an interconnect comprising forming a connector on an interconnect disposed on a first surface of a first substrate and applying a nonconductive material in a non-liquid form over the interconnect after forming the connector. The nonconductive material covers at least a lower portion of the interconnect, and at least a portion of the interconnect is exposed. The nonconductive material is formed around the connector by pressing the nonconductive material over the connector with a roller. An angle between a top surface of the nonconductive material and a connector sidewall between about 65 degrees and about 135 degrees. The nonconductive material may be formed to extend under the connector.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: July 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ting Chen, Hsuan-Ting Kuo, Hsien-Wei Chen, Wen-Hsiung Lu, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9922783
    Abstract: A method is for making an electronic device including forming a multilayer circuit board having a non-planar three-dimensional shape defining a membrane switch recess therein, the multilayer circuit board including at least one liquid crystal polymer (LCP) layer, and at least one electrically conductive pattern layer thereon defining at least one membrane switch electrode adjacent the membrane switch recess to define a membrane switch. The method also includes filling the membrane switch recess with a compressible dielectric material, and positioning at least one biasing member in the membrane switch recess.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: March 20, 2018
    Assignee: HARRIS CORPORATION
    Inventors: Louis Joseph Rendek, Jr., Lawrence Wayne Shacklette, Paul Brian Jaynes, Philip Anthony Marvin
  • Patent number: 9922951
    Abstract: A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.
    Type: Grant
    Filed: November 12, 2016
    Date of Patent: March 20, 2018
    Assignee: Sierra Circuits, Inc.
    Inventors: Kenneth S. Bahl, Konstantine Karavakis
  • Patent number: 9911651
    Abstract: A method of forming a skip-via, including, forming a first dielectric layer on a first metallization layer, forming a second metallization layer on the first dielectric layer and a second dielectric layer on the second metallization layer, removing a section of the second dielectric layer to form a via to the second metallization layer, removing a portion of the second metallization layer to form an aperture, and removing an additional portion of the second metallization layer to form an exclusion zone.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Patent number: 9907167
    Abstract: A printed circuit board with high-capacity copper circuit includes a conductive trace, a first protecting layer, and a second protecting layer formed on opposite sides of the conductive trace. The conductive trace includes a base conductive trace pattern, a first conductive trace pattern, and a second conductive trace pattern. The first and second conductive trace patterns are directly formed on opposite surfaces of the base copper conductive trace pattern. A trace width of the first conductive trace pattern is the same as a line width of the second conductive trace pattern.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 27, 2018
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventors: Fang-Bo Xu, Peng Wu, Jian-Quan Shen, Ke-Jian Wu
  • Patent number: 9903991
    Abstract: A method of fabricating a wire grid polarizer includes sequentially depositing a conductive wire pattern layer, and a plurality of guide patterns which forms one or more trenches therebetween on the conductive wire pattern layer, hydrophobically treating surfaces of the conductive wire pattern layer exposed in the trenches, and the guide patterns, coating the hydrophobically treated conductive wire pattern layer in the trenches with a neutral layer to partially fill the trenches, filling a remainder of the trenches with a block copolymer of two monomers with different etching rates, aligning the block copolymer filled in the trenches, selectively removing blocks of one monomer among the two monomers from the aligned block copolymer, and patterning the conductive wire pattern layer by using blocks of the other monomer among the two monomers remaining in the trenches and the guide patterns as a mask.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: February 27, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Eun Ae Kwak, Min Hyuck Kang, Moon Gyu Lee
  • Patent number: 9865812
    Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: January 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Scott E. Sills, Whitney L. West, Rob B. Goodwin, Nishant Sinha
  • Patent number: 9865472
    Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: January 9, 2018
    Assignee: Lam Research Corporation
    Inventors: Robert Chebi, Frank Lin, Jaroslaw W. Winniczek, Wan-Lin Chen, Erin Moore, Lily Zheng, Stephan Lassig, Jeff Bogart, Camelia Rusu
  • Patent number: 9852914
    Abstract: The present invention is a sacrificial-film removal method of removing a sacrificial film from a surface of a substrate provided with a plurality of struts and the sacrificial film embedded between the plurality of struts, including: a wet etching step where the sacrificial film is removed to its halfway depth by supplying an etchant to the surface of the substrate; a rinse step where a residue adhering to the surface of the substrate is washed out by supplying a rinsing liquid to the surface of the substrate after the wet etching step; a drying step where a liquid component on the surface of the substrate is removed after the rinse step; and a dry etching step where the sacrificial film remaining on the surface of the substrate is removed by supplying an etching gas to the surface of the substrate after the drying step.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: December 26, 2017
    Assignees: SCREEN Holdings Co., Ltd., CENTRAL GLASS COMPANY, LIMITED
    Inventors: Manabu Okutani, Tomonori Umezaki, Akiou Kikuchi
  • Patent number: 9837304
    Abstract: Method of manufacturing a semiconductor device is described that uses sidewall protection of a recessed feature to prevent loss of critical dimension during a cleaning process to remove etch residue. According to one embodiment, the method includes providing a substrate containing a film thereon having a recessed feature with a sidewall and a bottom portion, depositing a conformal film on the sidewall and on the bottom portion, removing the conformal film from the bottom portion in an anisotropic etching process, where the remaining conformal film forms a protection film on the sidewall, and performing a cleaning process that removes etch residue from the recessed feature without etching the protection film or the sidewall.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: December 5, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Robert D. Clark, Kandabara N. Tapily
  • Patent number: 9779985
    Abstract: A method for making patterns includes forming on a substrate surface a first mask delimiting at least two areas to be metallised; forming an assembly guide above the first mask, the assembly guide delimiting a surface covering two contact areas belonging respectively to the two areas to be metallised; depositing on the surface a block copolymer layer; reorganising the block copolymer layer; eliminating one of the phases of the reorganised block copolymer layer, resulting in a plurality of holes extending into the block copolymer layer above the two contact areas and a portion of the first mask arranged between the two contact areas; widening the holes of the block copolymer layer until a continuous trench is formed above the two contact areas and the portion of the first mask; transferring, through the first mask, the continuous trench onto the surface of the substrate to form patterns corresponding to the contact areas.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: October 3, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jérôme Belledent, Patricia Pimenta Barros
  • Patent number: 9768021
    Abstract: Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the at least one soluble block laterally aligned with the trench and positioned within a matrix of the at least one insoluble block. The self-assembled pattern may be exposed to a metal oxide precursor that impregnates the at least one soluble block. The metal oxide precursor may be oxidized to form a metal oxide. The self-assembled pattern may be removed to form a pattern of metal oxide lines on the substrate surface. Semiconductor device structures are also described.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Timothy A. Quick, J. Neil Greeley
  • Patent number: 9733430
    Abstract: A method of manufacturing an optical waveguide with a vertical slot including the steps of a) providing a substrate successively including an electric insulator layer and a crystalline semiconductor layer, b) forming a trench on the semiconductor layer to expose the electric insulator layer and defining first and second semiconductor areas on either side, step b) being executed so that the first semiconductor area has a lateral edge extending across the entire thickness of the semiconductor layer, c) forming the dielectric layer having the predetermined width across the entire thickness of the lateral edge, the method being remarkable in that the trench formed at step b) is configured so that the second semiconductor area forms a seed layer.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: August 15, 2017
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Marc Fedeli, Alexis Abraham, Ségoléne Olivier, Yann Bogumilowicz, Thomas Magis, Pierre Brianceau
  • Patent number: 9689508
    Abstract: A microvalve device and fluid flow control method, the microvalve device comprising: a microvalve body, the microvalve body being composed of multiple layers and comprising a first layer (1) and a second layer (2) bonded with the first layer (1), the second layer (2) having a plurality of fluid ports (7, 8, 9); a cavity (6) disposed between the first layer and the second layer; a plurality of actuators (3, 4, 5) respectively disposed corresponding to each fluid port, the plurality of actuators (3, 4, 5) controlling the opening and closing of the plurality of fluid ports (7, 8, 9). The fluid flow control method comprising: respectively employing a plurality of actuators to independently control the opening and closing of a plurality of fluid ports.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: June 27, 2017
    Assignees: ZHEJIANG DUNAN ARTIFICIAL ENVIRONMENT CO., LTD., TSINGHUA UNIVERSITY
    Inventors: Ning Deng, Zheyao Wang, Peiyi Chen, Shengchang Zhang, Tinghou Jiang
  • Patent number: 9685606
    Abstract: A patterning method includes forming an etch-target layer on a substrate, forming mask patterns on the etch-target layer, and etching the etch-target layer using the mask patterns as an etch mask to form patterns spaced apart from each other. The etching process of the etch-target layer includes irradiating the etch-target layer with an ion beam, whose incident energy ranges from 600 eV to 10 keV. A recess region is formed in the etch-target layer between the mask patterns, and the ion beam is incident onto a bottom surface of the recess region at a first angle with respect to a top surface of the substrate and is incident onto an inner side surface of the recess region at a second angle with respect to the inner side surface of the recess region. The first angle ranges from 50° to 90° and the second angle ranges from 0° to 40°.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: June 20, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongchul Park, Hyungjoon Kwon, Inho Kim, Jongsoon Park
  • Patent number: 9669628
    Abstract: The wall of each supply path formed in a silicon substrate has such a shape that a plurality of regions distinguished from each other due to different inclinations to a first surface of the silicon substrate are connected to each other between the first surface and a second surface of the silicon substrate and the width of the supply path is maintained or expands from the first surface to second surface of the silicon substrate. An internal opening is formed by one of the regions that is most steeply inclined to the first surface of the silicon substrate. A region reducing the squeezing of an adhesive into the internal opening is placed between the internal opening and the second surface of the silicon substrate.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: June 6, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keisuke Kishimoto, Taichi Yonemoto
  • Patent number: 9625329
    Abstract: An example system comprises a microelectromechanical system (MEMS) sensor, a strain gauge, and a strain compensation circuit. The MEMS sensor is operable to generate a sensor output signal that corresponds to a sensed condition (e.g., acceleration, orientation, and/or pressure). The strain gauge is operable to generate a strain measurement signal indicative of a strain on the MEMS sensor. The strain compensation circuit is operable to modify the sensor output signal to compensate for the strain based on the strain measurement signal. The strain compensation circuit stores sensor-strain relationship data indicative of a relationship between the sensor output signal and the strain measurement signal. The strain compensation circuit is operable to use the sensor-strain relationship data for the modifying of the sensor output signal. The modification of the sensor output signal comprises one or both of: removal of an offset from the sensor signal, and application of a gain to the sensor signal.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: April 18, 2017
    Assignee: INVENSENSE, INC.
    Inventors: Ilya Gurin, Joe Seeger
  • Patent number: 9620379
    Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a multi-layered mask comprising a laser energy absorbing, non-photodefinable topcoat disposed over a water-soluble base layer disposed over the semiconductor substrate. Because the laser light absorbing material layer is non-photodefinable, material costs associated with conventional photo resist formulations may be avoided. The mask is direct-write patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. Absorption of the mask layer within the laser emission band (e.g., UV band and/or green band) promotes good scribe line quality. The substrate may then be plasma etched through the gaps in the patterned mask to singulate the IC with the mask protecting the ICs during the plasma etch. The soluble base layer of the mask may then be dissolved subsequent to singulation, facilitating removal of the layer.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: April 11, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Mohammad Kamruzzaman Chowdhury, Todd Egan, Brad Eaton, Madhava Rao Yalamanchili, Ajay Kumar
  • Patent number: 9538647
    Abstract: A substrate structure is provided. The substrate structure includes a substrate and a carrier. The substrate includes a first through hole, a first surface and a second surface opposite to the first surface. The first through hole penetrates the substrate for connecting the first surface and the second surface. The carrier includes a second through hole, a release layer, an insulating paste layer and a metal layer. The insulating paste layer is disposed between the release layer and the metal layer. The carrier is attached to the second surface with the release layer thereof. The second through hole corresponds to the first through hole and penetrates the carrier for exposing the first through hole.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: January 3, 2017
    Assignee: SUBTRON TECHNOLOGY CO., LTD.
    Inventor: Chao-Min Wang
  • Patent number: 9531209
    Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: December 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Patent number: 9526176
    Abstract: A component-embedded resin substrate includes a resin structure including a plurality of laminated resin layers and having an end surface surrounding an outer periphery of the resin layers and a plurality of embedded components arranged as embedded in the resin structure. The plurality of embedded components include a first embedded component and a second embedded component. When viewed in a planar view, the first embedded component has a first outer side extending along a portion of an end surface 5 closest to the first embedded component. When viewed in a planar view, the second embedded component has a second outer side extending along a portion of the end surface closest to the second embedded component. When viewed in a planar view, the outer side is oblique to the second outer side.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: December 20, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Norio Sakai, Yoshihito Otsubo
  • Patent number: 9442371
    Abstract: A method of producing a structure containing a phase-separated structure, including a step in which a layer including an Si-containing block copolymer having a plurality of blocks bonded is formed between guide patterns on a substrate; a step in which a solution of a top coat material is applied to the layer and the guide patterns so as to form a top coat film; and a step in which the layer including the Si-containing block copolymer and having the top coat film formed thereon is subjected to annealing treatment so as to conduct a phase separation of the layer; in which a solvent of the solution of the top coat material contains no basic substance.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: September 13, 2016
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Takehiro Seshimo, Takaya Maehashi, Takahiro Dazai, Yoshiyuki Utsumi, Tasuku Matsumiya, Ken Miyagi, Daiju Shiono, Tsuyoshi Kurosawa
  • Patent number: 9412611
    Abstract: A method for forming a patterned topography on a substrate is provided. The substrate is initially provided with an exposed plurality of lines formed atop. An embodiment of the method includes aligning and preparing a first directed self-assembly pattern (DSA) pattern immediately overlying the plurality of lines, and transferring the first DSA pattern to form a first set of cuts in the plurality of lines. The embodiment further includes aligning and preparing a second DSA pattern immediately overlying the plurality of lines having the first set of cuts formed therein, and transferring the second DSA pattern to form a second set of cuts in the plurality of lines. The first and second DSA patterns each comprise a block copolymer having a hexagonal close-packed (HCP) morphology and a characteristic dimension Lo that is between 0.9 and 1.1 times the spacing between individual lines of the plurality of lines.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: August 9, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Mark H. Somervell, Benjamen M. Rathsack
  • Patent number: 9402307
    Abstract: A rigid-flexible substrate includes a plurality of rigid portions, and a flexible portion connecting the plurality of rigid portions and including a portion of a first resin sheet including at least one layer of a thermoplastic resin sheet, the rigid portions including a portion of the first resin sheet other than the flexible portion, and a second resin sheet including a plurality of thermoplastic resin sheets laminated on one surface or both surfaces of the portion of the first resin sheet other than the flexible portion, and a tapered portion is provided at an end edge of the second resin sheet on a side close to the flexible portion, and a thickness of the tapered portion in a direction in which the second resin sheet is laminated decreases toward the flexible portion and is substantially 0 at a position in contact with the flexible portion.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: July 26, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshihito Otsubo, Takayoshi Yoshikawa, Akinori Takezawa
  • Patent number: 9398703
    Abstract: A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material that has been covered with catalytic adhesive material on both faces of the dielectric laminate material. The layer of catalytic adhesive coats a portion of the dielectric laminate material around the hole. The patterned metal layer is placed over the catalytic adhesive material on both faces of the dielectric laminate material and within the hole.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: July 19, 2016
    Assignee: Sierra Circuits, Inc.
    Inventors: Konstantine Karavakis, Kenneth S. Bahl
  • Patent number: 9377684
    Abstract: A material (M) includes a substrate one of the surfaces of which is covered with a layer based on a block copolymer having a block (B) consisting of a polysaccharide and to its uses for electronics, in order to prepare organic electroluminescent diodes (OLEDs) or organic photovoltaic cells (OPV) or for designing detection devices (nanobiosensors, biochips).
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: June 28, 2016
    Assignee: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (C.N.R.S)
    Inventors: Karim Aissou, Sami Halila, Sebastien Fort, Redouane Borsali, Thierry Baron