Forming Or Treating Electrical Conductor Article (e.g., Circuit, Etc.) Patents (Class 216/13)
  • Patent number: 10269591
    Abstract: A method of selectively removing silicon nitride is provided. The method includes: providing a wafer having silicon nitride on a surface of the wafer; providing a mixture of phosphoric acid and a silicon-containing material; and delivering the mixture to the surface of the wafer to remove the silicon nitride. Single wafer etching apparatuses of selectively removing silicon nitride are also provided.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Hsueh Changchien, Yu-Ming Lee, Chi-Ming Yang
  • Patent number: 10269841
    Abstract: A sensor package includes a sensor, an encapsulation layer, a redistribution layer, a photo-imageable dielectric (PID) layer and via plugs. The encapsulation layer exposes the active surface of the sensor, and the top surface of the encapsulation layer is coplanar with the active surface of the sensor. The redistribution layer covers the top surface of the encapsulation layer and the active surface of the sensor. The PID layer covers the redistribution layer, the encapsulation layer and the active surface of the sensor. The via plugs are disposed around the sensor and through the encapsulation layer. The via plugs are electrically connected to the redistribution layer and the active surface of the sensor. The cross section of the via plug at the top surface of the encapsulation layer has a first hole diameter, and the cross section of the via plug at the bottom surface of the encapsulation layer has a second hole diameter. The first hole diameter is less than the second hole diameter.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: April 23, 2019
    Assignee: PHOENIX & CORPORATION
    Inventors: Che-Wei Hsu, Shih-Ping Hsu
  • Patent number: 10263221
    Abstract: A method for exposing an electrode terminal covered with an organic film in a light-emitting device without damaging the electrode terminal is provided. In a region of the electrode terminal to which electric power from an external power supply or an external signal is input, an island-shaped organic compound-containing layer is formed and the organic film is formed thereover. The organic film is removed by utilizing low adhesion of an interface between the organic compound-containing layer and the electrode terminal, whereby the electrode terminal can be exposed without damage to the electrode terminal.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: April 16, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Chida, Kaoru Hatano, Tomoya Aoyama, Ryu Komatsu, Masatoshi Kataniwa
  • Patent number: 10199215
    Abstract: Methods and apparatus for processing a substrate are described herein. Methods for passivating dielectric materials include forming alkyl silyl moieties on exposed surfaces of the dielectric materials. Suitable precursors for forming the alkyl silyl moieties include (trimethylsilyl)pyrrolidine, aminosilanes, and dichlorodimethylsilane, among others. A capping layer may be selectively deposited on source/drain materials after passivation of the dielectric materials. Apparatus for performing the methods described herein include a platform comprising a transfer chamber, a pre-clean chamber, an epitaxial deposition chamber, a passivation chamber, and an atomic layer deposition chamber.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: February 5, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Abhishek Dube, Schubert S. Chu, Jessica S. Kachian, David Thompson, Jeffrey Anthis
  • Patent number: 10191380
    Abstract: [Problem] To provide a composition capable of improving surface roughness of resist patterns, and also to provide a pattern formation method employing the composition. [Solution] The present invention provides a composition containing a particular nitrogen-containing compound, an anionic surfactant having a sulfo group, and water; and also provides a pattern formation method containing a step of applying the composition to a resist pattern beforehand developed and dried.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: January 29, 2019
    Assignee: AZ Electronic Materials (Luxembourg) S.a.r.l.
    Inventors: Kazuma Yamamoto, Tatsuro Nagahara
  • Patent number: 10181381
    Abstract: A variable capacitor device that includes a dielectric layer comprising a shape-memory polymer, a first metal plate and a second metal plate, wherein the dielectric layer is sandwiched between the first and the second metal plates. The shape-memory polymer has a first thickness at a first temperature under a first external compressive load, a second thickness at a second temperature under a second external compressive load, wherein the first thickness is greater than the second thickness, the second temperature is greater than the first temperature, and the second external compressive load is greater than the first external compressive load. The shape memory polymer having the second thickness is configured to convert to the shape-memory polymer having the first thickness when sequentially subjected to the first external compressive load and the second temperature.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: January 15, 2019
    Assignee: King Abdulaziz University
    Inventors: Faten Ebrahim S. Al-Hazmi, Fahrettin Yakuphanoglu, Ahmed A. Al-Ghamdi, Yusuf Al-Turki
  • Patent number: 10156713
    Abstract: A wavelength variable interference filter includes a fixed reflection film, a movable reflection film, and an actuator that changes a gap between the films. A wavelength of output light is first wavelength ??. A center wavelength in a target wavelength region is measurement center wavelength ?0. A peak center wavelength in reflection characteristics of the movable reflection film is first center wavelength ?1. A peak center wavelength in reflection characteristics of the fixed reflection film is second center wavelength ?2. The gap between the films when light of the first wavelength ?? is transmitted is d?(?1 , ?2). When a pair of optical films face each other, a center wavelength in reflection characteristics of the pair is the measurement center wavelength ?0, and the light of the first wavelength ?? is outputted, the gap between the pair of optical films is d?(?0, ?0). Further, d?(?1, ?2)<d?(?0, ?0).
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: December 18, 2018
    Assignee: Seiko Epson Corporation
    Inventor: Tomonori Matsushita
  • Patent number: 10155371
    Abstract: An automated bonding sequence system and method for customizing a bonding sequence is provided. The method includes the steps of detecting that a first substrate is in close proximity with the a second substrate, during an optical bonding operation, wherein at least the first substrate includes an amount of adhesive for optically bonding to the second substrate, stopping an automated process of optically bonding of the optical bonding operation, in response to the detecting, recording operator feedback control signals, the operator feedback control signals being received from a controller being operated by an operator to contact the first substrate and the second substrate, analyzing the operator feedback control signals to determine a bonding sequence for automatically optically bonding the first substrate and the second substrate, and resuming, by the processor, the automated process of the optical bonding operation.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: December 18, 2018
    Assignee: PRECISION VALVE & AUTOMATION, INC.
    Inventors: Andrew John Nally, Alexander M. Giordano, Edward F. Carey, Jonathan Neal Urquhart
  • Patent number: 10144155
    Abstract: The present invention relates to a production method for a glassy carbon mold, and, more specifically, relates to a production method for a glassy carbon mold including the steps of: placing a mixture having a thermosetting resin, a curing agent, and a viscosity adjusting solvent between a thermosetting resin substrate and a master pattern formed by a micro-nano process; pressing either the master pattern or the thermosetting resin substrate and applying heat to form a cured thermosetting resin pattern part on the substrate; and removing the master pattern, and subjecting the substrate and the cured thermosetting resin pattern.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 4, 2018
    Assignee: CHUNG-ANG UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Seok Min Kim, Jong Won Seok, Tae Hyoung Kim, Jong Hyun Ju
  • Patent number: 10124559
    Abstract: Bulk materials having a kinetically limited nano-scale diffusion bond is provided. The bulk materials having a kinetically limited nano-scale diffusion bond includes transparent material, absorbent opaque material and a diffusion bond. The transparent material has properties that allow an electromagnetic beam of a select wavelength to pass there through without more than minimal energy absorption. The absorbent opaque material has properties that significantly absorb energy from the electromagnetic beam. The diffusion bond is formed by the electromagnetic beam bonding the transparent material to the absorbent opaque material. Moreover, the diffusion bond has a thickness that is less than 1000 nm.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: November 13, 2018
    Assignees: MEDTRONIC, INC., CORNING INCORPORATED
    Inventors: Michael S. Sandlin, David A. Ruben, Raymond M. Karam, Georges Roussos, Thomas M. Wynne
  • Patent number: 10119103
    Abstract: A cleaning liquid including hydrofluoric acid, a tetrazole compound, and water. The tetrazole compound may be represented by the following Formula (B1) in which R1 is a hydrogen atom or an organic group and R2 is a hydrogen atom, a hydroxyl group, a mercapto group, an amino group, or an organic group.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: November 6, 2018
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Tatsuo Goto, Kenji Seki
  • Patent number: 10072929
    Abstract: A circuit device includes a clock signal generation circuit that generates a clock signal through an oscillation circuit, and a detection circuit including a circuit operating through an operation signal based on the clock signal. The clock signal generation circuit includes a first frequency adjustment unit which is capable of adjusting an oscillation frequency before an physical quantity transducer and the circuit device are connected to each other, and a second frequency adjustment unit which is capable of adjusting the oscillation frequency in a state where the physical quantity transducer and the circuit device are connected to each other.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: September 11, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Teppei Higuchi, Katsuhiko Maki
  • Patent number: 10073064
    Abstract: According to a method for manufacturing a device in which an electrode of an element is electrically connected to a penetrating wire in a substrate, a structure is prepared in which the element is arranged on the first substrate having a through hole formed therein: and a second substrate is prepared which has an electroconductive seed layer formed thereon. Then, a wall part is formed on the first substrate; a seed layer is joined to a face on an element side of the structure through a bonding layer; the bonding layer is removed; and the seed layer is exposed in the inside of the opening. The inside of the wall part and the through hole is filled with a conductor, with the use of the seed layer through electrolytic plating.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: September 11, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shinichiro Watanabe, Shinan Wang
  • Patent number: 10062720
    Abstract: The present disclosure relates to an integrated circuit, and an associated method of formation. In some embodiments, the integrated circuit comprises a deep trench grid disposed at a back side of a substrate. A passivation layer lines the deep trench grid within the substrate. The passivation layer includes a first high-k dielectric layer and a second high-k dielectric layer disposed over the first high-k dielectric layer. A first dielectric layer is disposed over the passivation layer, lining the deep trench grid and extending over an upper surface of the substrate. A second dielectric layer is disposed over the first dielectric layer and enclosing remaining spaces of the deep trench grid to form air-gaps at lower portions of the deep trench grid. The air-gaps are sealed by the first dielectric layer or the second dielectric layer below the upper surface of the substrate.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Chih-Hui Huang, Shyh-Fann Ting, Shih Pei Chou, Sheng-Chan Li
  • Patent number: 10062469
    Abstract: Articles with graphene are selectively transparent to electromagnetic radiation. The articles transmit electromagnetic radiation in the infrared and visible light bands while inhibiting incident radio frequency radiation. The articles have high electrical conductivity and may be used in windows and domes.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: August 28, 2018
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Jitendra S. Goela, Nathaniel E. Brese
  • Patent number: 10039193
    Abstract: A method of manufacturing conductive patterns includes the steps of a) printing and curing UV curable inkjet to define a cured inkjet ink pattern on a metal sheet bonded to a non-conductive substrate; b) etching the metal sheet not covered by the cured ink pattern to expose the non-conductive substrate; and c) applying an alkaline solution to dissolve the cured inkjet ink pattern within 5 minutes.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: July 31, 2018
    Assignee: AGFA-GEVAERT
    Inventors: Rita Torfs, Johan Loccufier
  • Patent number: 10021789
    Abstract: An object is to provide a laminated polyimide substrate, and a method for the production thereof, in which various properties are ensured and/or provided by effectively controlling changes over time under stringent conditions, while ensuring sufficient adhesion between a polyimide film and metal layer. A laminated polyimide substrate comprises a polyimide layer, an alkali-treated layer derived from the polyimide layer, and a metal layer, arranged in that order, wherein the alkali-treated layer contains an anionic functional group, and is a laminated structure having a layer containing a metal catalyst arranged on the metal layer side and a layer containing a complex of the metal catalyst arranged on the polyimide layer side.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: July 10, 2018
    Assignee: EBARA-UDYLITE CO., LTD.
    Inventors: Shinya Ochi, Ryuichi Nakagami, Makoto Kohtoku, Mika Hamada
  • Patent number: 10000853
    Abstract: A system and method for removing metal from a substrate in a controlled manner is disclosed. The system includes a chamber, with one or more gas inlets to allow the flow of gasses into the chamber, at least one exhaust pump, to exhaust gasses from the chamber, and a heater, capable of modifying the temperature of the chamber. In some embodiments, one or more gasses are introduced into the chamber at a first temperature. The atoms in these gasses chemically react with the metal on the surface of the substrate to form a removable compound. The gasses are then exhausted from the chamber, leaving the removable compound on the surface of the substrate. The temperature of the chamber is then elevated to a second temperature, greater than the sublimation temperature of the removable compound. This increased temperature allows the removable compound to become gaseous and be exhausted from the chamber.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: June 19, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tsung-Liang Chen, Benjamin Schmiege, Jeffrey W. Anthis, Glen Gilchrist
  • Patent number: 9987830
    Abstract: According to various embodiments, a method for processing a carrier may include: forming a layer structure over the carrier, the layer structure including a support layer and a two-dimensional layer over the support layer; wherein the layer structure has at least one opening that exposes a portion of the carrier; forming an auxiliary layer structure, wherein the auxiliary layer structure at least partially covers the layer structure and at least partially fills the at least one opening; and removing the support layer of the layer structure.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: June 5, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Matthias Koenig, Guenther Ruhl
  • Patent number: 9984923
    Abstract: A method of forming a semiconductor structure includes forming at least one trench in a dielectric layer, forming a barrier layer on a bottom of said at least one trench, sidewalls of said at least one trench and a top surface of the dielectric layer, the barrier layer having a non-uniform thickness, and selectively thinning at least a first portion of the barrier layer using one or more cycles comprising forming an oxidized layer in the first portion of the barrier layer using a neutral beam oxidation and removing the oxidized layer using an etching process.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Cornelius Brown Peethala, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 9981471
    Abstract: The present disclosure relates to a method for the application of an antiwetting coating on at least one surface of a substrate of semiconductor material comprising the steps of: a) applying on said at least one surface a metal layer of a material chosen in the group constituted by noble metals, coining metals, their oxides and their alloys; and b) applying on said metal layer a layer of a thiol of formula R—SH, where R is a linear alkyl chain having from 3 to 20 carbon atoms and, optionally, at least one hetero-atom, for obtaining an antiwetting coating. The disclosure further regards a method for the production of a nozzle plate for ink-jet printing and to an integrated ink-jet printhead provided with a nozzle plate obtained according to the method of the disclosure.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: May 29, 2018
    Assignee: STMicroelectronics S.R.L.
    Inventor: Fabrizio Porro
  • Patent number: 9977522
    Abstract: A touch panel and a method of manufacturing the touch panel are provided. The touch panel includes a substrate comprising a wiring area and a sensor area, a sensing pattern located on a surface of the substrate in the sensor area, and a wiring line located on the surface of the substrate in the wiring area and electrically connected to the sensing pattern. The sensing pattern includes a plurality of first fine metal lines arranged irregularly in a mesh, and a first photosensitive layer pattern residue located between at least two of the first fine metal lines.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: May 22, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ki Hyun Cho, Cheol Kyu Kim, Sung kyun Park, Sun Haeng Cho
  • Patent number: 9961780
    Abstract: A method for manufacturing a resin multilayer board formed from a thermoplastic resin, which method allows for improvement in accuracy of the position of a component relative to the resin multilayer board, is provided. A method for manufacturing a resin multilayer board includes: a step of bonding a component to a pressure-sensitive adhesive layer of a pressure-sensitive adhesive sheet having the pressure-sensitive adhesive layer on a surface thereof; a step of opposing a thermoplastic resin sheet to the pressure-sensitive adhesive layer, and fixing the component bonded to the pressure-sensitive adhesive sheet and the thermoplastic resin sheet to each other by heating; a step of peeling the pressure-sensitive adhesive sheet from the component fixed to the thermoplastic resin sheet; and stacking and thermally welding a plurality of thermoplastic resin sheets including the thermoplastic resin sheet to which the component has been transferred.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: May 1, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hirofumi Shinagawa, Shigeru Tago, Masaki Kawata, Yuki Ito
  • Patent number: 9960106
    Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Chiung-Han Yeh
  • Patent number: 9945042
    Abstract: There are provided a chip electronic component and a manufacturing method thereof, and more particularly, a chip electronic component having an internal coil structure capable of preventing the occurrence of short-circuits between coil portions and having a high aspect ratio (AR) by increasing a thickness of a coil as compared to a width of the coil, and a manufacturing method thereof.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: April 17, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hye Yeon Cha, Dong Hwan Lee, Jung Hyuk Jung, Chan Yoon, Hye Min Bang, Tae Young Kim
  • Patent number: 9941708
    Abstract: Systems, methods, and apparatus are disclosed for power transfer including a plurality of coil structures located over a ferrite element, the plurality of coil structures configured to generate a high flux region and a low flux region, the low flux region being located between the plurality of coil structures, and a tuning capacitance located directly over the ferrite element in the low flux region.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: April 10, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Nicholas Athol Keeling, Michael Le Gallais Kissin, Mickel Bipin Budhia, Chang-Yu Huang, Jonathan Beaver, Hao Hao, Claudio Armando Camasca Ramirez
  • Patent number: 9941316
    Abstract: Various embodiments include methods and apparatuses for forming and using pixels for image sensors. In one embodiment, an image sensor is disclosed. The image sensor includes an optically sensitive material; a plurality of electrodes proximate the optically sensitive material, including at least a first electrode, a second electrode and a third electrode; and a charge store. The first electrode is coupled to the charge store, and the first electrode and the second electrode are configured to provide a bias to the optically sensitive material to direct photocarriers to the charge store. Other methods and apparatuses are disclosed.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: April 10, 2018
    Assignee: INVISAGE TECHNOLOGIES, INC.
    Inventors: Edward Hartley Sargent, Jess Jan Young Lee, Emanuele Mandelli, Jae Park
  • Patent number: 9939567
    Abstract: Embodiments of the invention provide a color filter substrate and a manufacturing method for the same, and a display device. The color filter substrate comprises a plurality of spacers. The spacer has a cross-sectional shape in a direction parallel to the color filter substrate, and the cross-sectional shape including a first supporting portion extending along a first direction and a second supporting portion extending along a second direction, which is connected to an end portion of the first supporting portion, the first direction being perpendicular to the second direction.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: April 10, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jun Long, Hongkun Zhang, Rui Li, Gang Yang
  • Patent number: 9933655
    Abstract: A polarizer includes a substrate; a plurality of metal lines on the substrate, the plurality of metal lines each having a first width and a first height and being spaced apart from and parallel to each other with a first gap therebetween; and a hydrophobic coating layer on the metal line. The polarizer may be directly formed on the substrate, allowing for manufacture of light-weight and thin film structure of display device.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: April 3, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Taeyoung Ahn, Jihoon Oh
  • Patent number: 9922923
    Abstract: To provide a technique capable of easily forming a resin opening of a desired shape. As a solution, a base is prepared which has a first surface region and a second surface region around the first surface region, and which has a wiring formed thereon. Subsequently, a resist which covers the first surface region is formed. Then, the first surface region and the second surface region are covered with a resin body such that the resist is included therein, and the resist is exposed from the resin body. After that, the exposed resist is removed, so that a resin opening that exposes the base in the first surface region is formed in the resin body.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: March 20, 2018
    Assignee: KABUSHIKI KAISHA EASTERN
    Inventor: Yoshiaki Narisawa
  • Patent number: 9892879
    Abstract: Encapsulated MEMS switches are disclosed along with methods of manufacturing the same. A non-polymer based sacrificial layer is used to form the actuation member of the MEMS switch while a polymer based sacrificial layer is used to form the enclosure that encapsulates the MEMS switch. The first non-polymer based sacrificial layer allows for highly reliable MEMS switches to be manufactured while also protecting the MEMS switch from carbon contamination. The polymer based sacrificial layer allows for the manufacture of more spatially efficient encapsulated MEMS switches.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: February 13, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Jonathan Hale Hammond, Julio Costa
  • Patent number: 9882167
    Abstract: A method for protecting an electronic device comprising an organic device body. The method involves the use of a hybrid layer deposited by chemical vapor deposition. The hybrid layer comprises a mixture of a polymeric material and a non-polymeric material, wherein the weight ratio of polymeric to non-polymeric material is in the range of 95:5 to 5:95, and wherein the polymeric material and the non-polymeric material are created from the same source of precursor material. Also disclosed are techniques for impeding the lateral diffusion of environmental contaminants.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: January 30, 2018
    Assignees: The Trustees of Princeton University, Universal Display Corporation
    Inventors: Prashant Mandlik, Sigurd Wagner, Jeffrey A. Silvernail, Ruiqing Ma, Julia J. Brown, Lin Han
  • Patent number: 9881875
    Abstract: A method of manufacturing electronic module is provided. The method can perform selective partial molding by forming the tapes in a predetermined area on the circuit substrate, setting electronic components out the predetermined area on the circuit substrate, forming the molding member encapsulating the whole circuit substrate and removing the tapes along of the molding member thereon. Following, forming an EMI shielding layer on the molding member and setting optoelectronics in the predetermined area on the circuit substrate could protect the electronic components from electromagnetic disturbance and avoid the optoelectronics being encapsulated.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: January 30, 2018
    Assignee: UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD.
    Inventors: Jen-Chun Chen, Tsung Jung Cheng, Chia Cheng Liu
  • Patent number: 9875906
    Abstract: A method for forming patterns in a semiconductor device includes providing a substrate and a patterning-target layer formed over the substrate; forming a first feature in a first hard mask layer formed over the patterning-target layer; and forming a second feature in a second hard mask layer formed over the patterning-target layer. The first hard mask layer has a different etching selectivity from the second hard mask layer. The method further includes selectively removing a portion of the first feature within a first trench to form a reshaped first feature. In an embodiment, the first trench exposes a portion of the second feature, and the selectively removing of the first portion of the first feature does not etch the portion of the second feature.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: January 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shih-Ming Chang
  • Patent number: 9876225
    Abstract: Anode active materials, anodes, and batteries are provided. In one embodiment, an anode active material includes particles consisting essentially of a material selected from the group consisting of silicon and an alloy of silicon. An average degree of circularity of the particles is 90% or less.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: January 23, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenichi Kawase, Tomoo Takada, Kensuke Yamamoto
  • Patent number: 9870023
    Abstract: A method of manufacturing a display panel, including providing a plurality of display substrates spaced apart from each other by a predetermined area disposed therebetween when viewed in a plan view, each of the display substrates including a display area, on which an image is displayed, and each of the display substrates being flexible; attaching a first film onto the display substrates to overlap with the display substrates; attaching a second film onto the first film; and substantially and simultaneously cutting the first and second films along a cutting line defined in an area overlapping with the predetermined area.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: January 16, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jun Namkung, Soonryong Park, Chulwoo Jeong
  • Patent number: 9859397
    Abstract: In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the <111> direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sanghoon Lee, Effendi Leobandung, Renee Mo, Brent A. Wacaser
  • Patent number: 9846509
    Abstract: Alternating touchscreen conductors in each layer of a touchscreen display are connected to separate touchscreen controllers. Each controller completely and separately resolves a location anywhere on the display so that a failure of either controller, or the failure of conductors connected to either controller, do not degrade touchscreen usability. Conductors in separate layers, connected to separate controllers may be isolated via insulators to prevent undesirable shorts. Conductors are shaped to minimize the area covered by insulators and maximize the area of useful conductor overlap.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: December 19, 2017
    Assignee: Rockwell Collins, Inc.
    Inventors: Donald E. Mosier, Craig E. Harwood
  • Patent number: 9842695
    Abstract: A ceramic-capacitor includes a first electrically-conductive-layer, a second electrically-conductive-layer arranged proximate to the first electrically-conductive-layer, and a dielectric-layer interposed between the first electrically-conductive-layer and the second electrically-conductive-layer. The dielectric-layer is formed of a lead-lanthanum-zirconium-titanate material (PLZT), wherein the PLZT is characterized by a dielectric-constant greater than 125, when measured at 25 degrees Celsius and zero Volts bias, and an excitation frequency of ten-thousand Hertz (10 kHz). A method for increasing a dielectric constant of the lead-lanthanum-zirconium-titanate material (PLZT) includes the steps of depositing PLZT to form a dielectric-layer of a ceramic-capacitor, and heating the ceramic-capacitor to a temperature not greater than 300° C.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: December 12, 2017
    Assignee: DELPHI TECHNOLOGIES, INC.
    Inventors: Ralph S. Taylor, Manuel Ray Fairchild, Uthamalingam Balachjandran, Tae H. Lee
  • Patent number: 9834843
    Abstract: The invention provides a process for forming crack-free dielectric films on a substrate. The process comprises the application of a dielectric precursor layer of a thickness from about 0.3 ?m to about 1.0 ?m to a substrate. The deposition is followed by low temperature heat pretreatment, prepyrolysis, pyrolysis and crystallization step for each layer. The deposition, heat pretreatment, prepyrolysis, pyrolysis and crystallization are repeated until the dielectric film forms an overall thickness of from about 1.5 ?m to about 20.0 ?m and providing a final crystallization treatment to form a thick dielectric film. The process provides a thick crack-free dielectric film on a substrate, the dielectric forming a dense thick crack-free dielectric having an overall dielectric thickness of from about 1.5 ?m to about 20.0 ?m.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: December 5, 2017
    Assignee: UCHICAGO ARGONNE, LLC
    Inventors: Beihai Ma, Manoj Narayanan, Uthamalingam Balachandran, Sheng Chao, Shanshan Liu
  • Patent number: 9823584
    Abstract: A method for fabricating an electrochemical sensing test piece comprises steps: forming an electrode layer on a substrate; etching the electrode layer to reduce the area of the electrode layer to be smaller than the area of the substrate, wherein the electrode layer has a test zone and a reading zone neighboring the test zone; forming an insulation member surrounding the test zone and covering the perimeter of the test zone; forming an enzyme layer on the test zone; and forming an insulation layer on the enzyme layer and the periphery of the reading zone and fabricating the insulation layer to have an opening revealing a portion of the enzyme layer. The insulation member fixes the effective reaction area of the tested material and increases measurement accuracy.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: November 21, 2017
    Assignee: Cheeshin Technology Co., Ltd.
    Inventor: Kuo-Chen Hsu
  • Patent number: 9795964
    Abstract: Techniques for use of wafer bonding techniques for sealing of microfluidic chips are provided. In one aspect, a wafer bonding sealing method includes the steps of: forming a first oxide layer coating surfaces of a first wafer, the first wafer having at least one fluidic chip; forming a second oxide layer on a second wafer; and bonding the first wafer to the second wafer via an oxide-to-oxide bond between the first oxide layer and the second oxide layer to form a bonded wafer pair, wherein the second oxide layer seals the at least one fluidic chip on the first wafer. The second wafer can be at least partially removed after performing the bonding, and fluidic ports may be formed in the second oxide layer. A fluidic chip device is also provided.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joshua T. Smith, Cornelia K. Tsang, Chao Wang, Benjamin H. Wunsch
  • Patent number: 9788418
    Abstract: Provided herein is a method for manufacturing a conductive transparent substrate, the method including forming a plurality of main electrodes on the substrate such that the main electrodes are distanced from one another; and forming a connecting electrode that electrically connects two or more main electrodes such that the plurality of main electrodes are grouped into a plurality of group electrodes that are electrically disconnected from one another, thereby producing a conductive transparent substrate with excellent transmittance in a process of high yield.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: October 10, 2017
    Assignee: INKTEC CO., LTD.
    Inventors: Kwang-Choon Chung, Ji Hoon Yoo, Joonki Seong, Byung Hun Kim, Nam-Boo Cho, Myung-Bong Yoo
  • Patent number: 9779282
    Abstract: The present invention relates to a capacitive fingerprint sensing device for sensing a fingerprint pattern. The sensing device comprises a protective dielectric top layer having an outer surface forming a sensing surface to be touched by the finger; a two-dimensional array of electrically conductive sensing structures arranged underneath the top layer; readout circuitry coupled to each of the electrically conductive sensing structures to receive a sensing signal indicative of a distance between the finger and the sensing structure; and an electroacoustic transducer arranged underneath the top layer and configured to generate an acoustic wave, and to transmit the acoustic wave through the protective dielectric top layer towards the sensing surface to induce an ultrasonic vibration potential in a ridge of finger placed in contact with the sensing surface.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 3, 2017
    Assignee: Fingerprint Cards AB
    Inventor: Farzan Ghavanini
  • Patent number: 9760002
    Abstract: A method of forming a circuit board includes forming a conductive pattern on a substrate; forming a first negative resist on the substrate after formation of the conductive pattern; partially exposing the first negative resist on the surface of the conductive pattern to form a first via exposure portion; forming a second negative resist on the substrate after formation of the first via exposure portion; partially exposing the second negative resist on the first via exposure portion to form a second via exposure portion larger than the first via exposure portion; developing the first negative resist and the second negative resist after formation of the second via exposure portion to form a via opening reaching the conductive pattern; and filling the via opening with a conductive material.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Mori, Hirokazu Noma, Keishi Okamoto
  • Patent number: 9741652
    Abstract: A wiring substrate includes a wiring layer on a projection of an insulating layer. The wiring layer includes a first metal layer on an end face of the projection with a peripheral portion of the end face exposed, a second metal layer that is on the first metal layer and wider than the end face, and a third metal layer. The second metal layer includes first and second opposite surfaces with the second surface on the first metal layer with a peripheral portion thereof exposed. The third metal layer covers side surfaces of the first metal layer, and the first surface, the peripheral portion of the second surface, and side surfaces of the second metal layer, and fills in a region where the end face and the peripheral portion of the second surface face each other. The materials of the second and third metal layers are different.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 22, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO. LTD.
    Inventors: Yuta Sakaguchi, Yusuke Gozu, Noriyoshi Shimizu
  • Patent number: 9735126
    Abstract: A solder alloy is providing, the solder alloy including zinc, aluminum, magnesium and gallium, wherein the aluminum constitutes by weight 8% to 20% of the alloy, the magnesium constitutes by weight 0.5% to 20% of the alloy and the gallium constitutes by weight 0.5% to 20% of the alloy, the rest of the alloy including zinc.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: August 15, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Manfred Mengel, Alexander Heinrich, Steffen Orso, Thomas Behrens, Oliver Eichinger, Lim Fong, Evelyn Napetschnig, Edmund Riedl
  • Patent number: 9719177
    Abstract: An etching chamber is equipped with an actively-cooled element preferentially adsorbs volatile compounds that are evolved from a polymeric layer of a wafer during etching, which compounds will act as contaminants if re-deposited on the wafer, for example on exposed metal contact portions where they may interfere with subsequent deposition of metal contact layers. In desirable embodiments, a getter sublimation pump is also provided in the etching chamber as a source of getter material. Methods of etching in such a chamber are also disclosed.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: August 1, 2017
    Assignee: EVATEC AG
    Inventor: Juergen Weichart
  • Patent number: 9699914
    Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: July 4, 2017
    Assignee: AVERATEK CORPORATION
    Inventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma
  • Patent number: 9693453
    Abstract: A wiring board includes a base layer, a plurality of connection terminals and a surface layer. The base layer is electrically insulative. The plurality of connection terminals are conductive and formed on the base layer. The surface layer is electrically insulative, and fills gaps between the plurality of connection terminals on the base layer. The connection terminals include a base portion made of a conductive first metal and a coating portion made of a conductive second metal that is different from the first metal. The coating portion penetrates the surface layer, and coats the base portion to the base layer.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: June 27, 2017
    Assignee: NGK SPARK PLUS CO., LTD.
    Inventors: Takahiro Hayashi, Seiji Mori, Tatsuya Ito