Forming Or Treating Electrical Conductor Article (e.g., Circuit, Etc.) Patents (Class 216/13)
  • Patent number: 10667406
    Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.
    Type: Grant
    Filed: September 16, 2018
    Date of Patent: May 26, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Cheng-Chieh Chiu, Chia-Chan Chang, Chun-Yi Kuo, Yu-Cheng Lin
  • Patent number: 10643780
    Abstract: Techniques and mechanisms for providing a flexible inductor. In an embodiment, the flexible inductor comprises a metal foil or other planar conductor, and inductive bodies disposed on opposite respective sides of the planar conductor. The inductive bodies each comprise a respective flexible suspension media and ferromagnetic particles disposed therein. A thickness of the planar conductor is in a range of 0.1 millimeters (mm) to 0.3 mm. In another embodiment, different layers of one inductive body vary from one another with respect to a thickness, a ferromagnetic material, a suspension media, an average size of ferromagnetic particles or a volume fraction of ferromagnetic particles.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventor: Arvind Sundaram
  • Patent number: 10643810
    Abstract: A zero-power plasmonic microelectromechanical system (MEMS) device is capable of specifically sensing electromagnetic radiation and performing signal processing operations. Such devices are highly sensitive relays that consume no more than 10 nW of power, utilizing the energy in detected electromagnetic radiation to detect and discriminate a target without the need of any additional power source. The devices can continuously monitor an environment and wake up an electronic circuit upon detection of a specific trigger signature of electromagnetic radiation, such as vehicular exhaust, gunfire, an explosion, a fire, a human or animal, and a variety of sources of radiation from the ultraviolet to visible light, to infrared, to terahertz radiation.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: May 5, 2020
    Assignee: Northeastern University
    Inventors: Matteo Rinaldi, Zhenyun Qian, Sungho Kang, Vageeswar Rajaram
  • Patent number: 10633743
    Abstract: A system and method for removing metal from a substrate in a controlled manner is disclosed. The system includes a chamber, with one or more gas inlets to allow the flow of gasses into the chamber, at least one exhaust pump, to exhaust gasses from the chamber, and a heater, capable of modifying the temperature of the chamber. In some embodiments, one or more gasses are introduced into the chamber at a first temperature. The atoms in these gasses chemically react with the metal on the surface of the substrate to form a removable compound. The gasses are then exhausted from the chamber, leaving the removable compound on the surface of the substrate. The temperature of the chamber is then elevated to a second temperature, greater than the sublimation temperature of the removable compound. This increased temperature allows the removable compound to become gaseous and be exhausted from the chamber.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: April 28, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tsung-Liang Chen, Benjamin Schmiege, Jeffrey W. Anthis, Glen Gilchrist
  • Patent number: 10615210
    Abstract: The present disclosure relates to a semiconductor device, a manufacturing method, a solid state image sensor, and electronic equipment that can achieve further improvement in reliability. Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: April 7, 2020
    Assignee: SONY CORPORATION
    Inventor: Masaki Haneda
  • Patent number: 10610971
    Abstract: A method for producing a recess or through-opening in a substrate includes applying pulsed laser radiation to the substrate. The laser radiation is focused using an optical system at an original focal depth and, by non-linear self-focusing within the pulse duration of an individual pulse, is also focused by the optical system at a focal depth different from the original focal depth. A difference between the focal depths corresponds to or is greater than the longitudinal extent of the recess or though-opening to be produced. The laser radiation modifies the substrate along a beam axis of the laser radiation in the region of the recess or through-opening, but does not result in removal of the substrate material necessary to form the recess or the through-opening. The substrate material in the modified region is anisotropically removed to produce the recess or through-opening in the substrate.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: April 7, 2020
    Assignee: LPKF LASER & ELECTRONICS AG
    Inventors: Robin Alexander Krueger, Norbert Ambrosius, Roman Ostholt
  • Patent number: 10578505
    Abstract: A process for manufacturing a MEMS pressure sensor having a micromechanical structure envisages: providing a wafer having a substrate of semiconductor material and a top surface; forming a buried cavity entirely contained within the substrate and separated from the top surface by a membrane suspended above the buried cavity; forming a fluidic-communication access for fluidic communication of the membrane with an external environment, set at a pressure the value of which has to be determined; forming, suspended above the membrane, a plate made of polysilicon, separated from the membrane by an empty space; and forming electrical-contact elements for electrical connection of the membrane and of the plate, which are designed to form the plates of a sensing capacitor, the value of capacitance of which is indicative of the value of pressure to be detected. A corresponding MEMS pressure sensor having the micromechanical structure is moreover described.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: March 3, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Lorenzo Baldo, Sarah Zerbini, Enri Duqi
  • Patent number: 10580819
    Abstract: The present disclosure relates to a solid-state imaging device, a method for manufacturing the same, and an electronic device capable of increasing utilization efficiency of a substrate. The solid-state imaging device includes a first semiconductor substrate provided with a sensor circuit having a photoelectric conversion part, and a second semiconductor substrate and a third semiconductor substrate provided with respective circuits different from the sensor circuit. The first semiconductor substrate, the second semiconductor substrate, and the third semiconductor substrate are stacked on each other in three layers, and a metal element for an electrode constituting an electrode for external connection is disposed in the first semiconductor substrate. An electrode for a measuring terminal is disposed within the second semiconductor substrate or the third semiconductor substrate, and the first semiconductor substrate is stacked after performing a predetermined measurement.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 3, 2020
    Assignee: Sony Corporation
    Inventor: Hiroshi Takahashi
  • Patent number: 10566386
    Abstract: A method of manufacturing a variable memory device includes forming a switching layer on a first conductive layer, forming a heating layer on the switching layer, the heating layer extending in a first direction, performing a first patterning process on the first conductive layer, the switching layer, and the heating layer to form a first trench extending in a second direction intersecting the first direction, forming variable resistance patterns on the heating layer, forming a second conductive layer on the variable resistance patterns, and performing a second patterning process on the switching layer, the heating layer, and the second conductive layer to form a second trench extending in the first direction and being between the variable resistance patterns.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ji-Hyun Jeong
  • Patent number: 10545594
    Abstract: An array substrate includes a substrate, a first signal line and a second signal line on the substrate, an insulating layer covering the first signal line and the second signal line, and a groove penetrating through the insulating layer. The first signal line and the second signal line are arranged in a same layer and separated from each other. The groove is between the first signal line and the second signal line.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: January 28, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Chong Liu, Haisheng Zhao, Zhilian Xiao, Hongxi Xiao, Wei Wang, Xiaoguang Pei
  • Patent number: 10538090
    Abstract: A method for manufacturing a perforated substrate includes forming a through-hole extending through a substrate from a first surface to a second surface opposite the first surface; forming a film on the first surface, a sidewall of the through-hole, and the second surface; forming a resist on the first surface; patterning the resist such that the resist closes an opening of the through-hole in the first surface; etching the film on the first surface using the resist as a mask; before the etching step, forming an inspection member on the second surface such that the inspection member closes an opening of the through-hole in the second surface; and determining whether there is a film patterning defect or a flaw that causes a film patterning defect.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 21, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Seiichiro Yaginuma, Masataka Nagai, Masaya Uyama
  • Patent number: 10510992
    Abstract: A method for exposing an electrode terminal covered with an organic film in a light-emitting device without damaging the electrode terminal is provided. In a region of the electrode terminal to which electric power from an external power supply or an external signal is input, an island-shaped organic compound-containing layer is formed and the organic film is formed thereover. The organic film is removed by utilizing low adhesion of an interface between the organic compound-containing layer and the electrode terminal, whereby the electrode terminal can be exposed without damage to the electrode terminal.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 17, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Chida, Kaoru Hatano, Tomoya Aoyama, Ryu Komatsu, Masatoshi Kataniwa
  • Patent number: 10497648
    Abstract: An embedded electronics package and method of manufacture includes a support substrate, a power semiconductor component coupled to a first side of the support substrate, and a logic semiconductor component coupled to a second side of the support substrate, opposite the first side. A first insulating material surrounds the logic semiconductor component. A logic interconnect layer is electrically coupled to the logic semiconductor component by at least one conductive micro-via extending through a portion of the first insulating material. A power interconnect layer is electrically coupled to the power semiconductor component by at least one conductive macro-via extending through a thickness of the support substrate. The power interconnect layer is thicker than the logic interconnect layer.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: December 3, 2019
    Assignee: General Electric Company
    Inventor: Raymond Albert Fillion
  • Patent number: 10468190
    Abstract: A capacitor component includes a body with a plurality of first and second internal electrodes alternately stacked with dielectric layers interposed therebetween. First and second connection electrodes extend in a thickness direction of the body and are respectively connected to the first and second internal electrodes. First and second lower electrodes are on a lower surface of the body and are respectively connected to the first and second connection electrodes.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong Won Seo, Jin Kyung Joo, Taek Jung Lee, Jin Woo Chun
  • Patent number: 10468202
    Abstract: A conductive paper electrode includes a paper, a carbon powder layer, a graphite layer and a nanostructural layer. The carbon powder layer is positioned over the paper. The graphite layer is positioned over the carbon powder layer. The nanostructural layer is positioned over the graphite layer. An electrochemical capacitor includes two conductive paper electrodes and an electrolyte interposed therebetween.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: November 5, 2019
    Assignee: NATIONAL SYNCHROTRON RADIATION RESEARCH CENTER
    Inventors: Ming-Jay Deng, Kueih-Tzu Lu, Jin-Ming Chen
  • Patent number: 10468267
    Abstract: Exemplary cleaning or etching methods may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. Methods may include forming a plasma within the remote plasma region to generate plasma effluents of the fluorine-containing precursor. The methods may also include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned within the processing region, and the substrate may include a region of exposed oxide and a region of exposed metal. Methods may also include providing a hydrogen-containing precursor to the processing region. The methods may further include removing at least a portion of the exposed oxide.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: November 5, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Zhijun Chen, Lin Xu, Anchuan Wang, Nitin Ingle
  • Patent number: 10460852
    Abstract: The present invention relates to an electrode having a multilayer nanomesh structure using single-crystalline copper and a method for manufacturing same, the electrode comprising: a substrate; a single-crystalline copper electrode layer formed on the substrate and having a hive-shaped pattern with a nano-sized line width; and a metal oxide layer formed on the single-crystalline copper electrode layer, this providing an electrode having excellent optical transmittance, low electrical sheet resistance, and excellent mechanical stability. The present invention is technically characterized by an electrode having a multilayer nanomesh structure using single-crystalline copper, the electrode comprising: a substrate; a single-crystalline copper electrode layer formed on the substrate and having a hive-shaped pattern with a nano-sized line width; and a metal oxide layer formed on the single-crystalline copper electrode layer.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: October 29, 2019
    Assignee: PUSAN NATIONAL UNIVERSITY INDUSTRIAL-UNIVERSITY COOPERATION FOUNDATION
    Inventors: Se-young Jeong, Ji-young Kim, Won-kyung Kim
  • Patent number: 10424716
    Abstract: A method for producing a piezoelectric device includes a laminate formation step in which a laminate including a piezoelectric thin film, a support substrate, a metal layer, and a silicon oxide film respectively stacked on both of an upper surface and a lower surface of the metal layer interposed between the piezoelectric thin film and the support substrate is formed, a semi-conducting layer formation step in which a semi-conducting layer is formed by oxidizing the metal layer, and a functional electrode formation step in which a functional electrode that is electro-mechanically coupled to the piezoelectric thin film is formed on a first principal surface of the piezoelectric thin film. The semi-conducting layer is a layer composed of a mixture of a metal constituting the metal layer and an oxide thereof, or a layer composed of a semiconductor which is an oxide of a metal constituting the metal layer.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: September 24, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takashi Iwamoto
  • Patent number: 10398026
    Abstract: A laminated substrate includes: a first substrate; a second substrate having a through-hole; a third substrate; a first adhesive layer bonding a rear surface of the first substrate and a front surface of the second substrate; a second adhesive layer bonding a rear surface of the second substrate and a front surface of the third substrate; a first post penetrating through the first adhesive layer, electrically connecting the first substrate to the second substrate, and made of an alloy of a high melting point metal and a low melting point metal; a second post penetrating through the second adhesive layer, electrically connecting the second substrate to the third substrate, and made of an alloy of the high melting point metal and the low melting point metal; and an electronic component fixed to the front surface of the third substrate and disposed in the through-hole of the second substrate.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: August 27, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, Hitachi Chemical Company, Ltd.
    Inventors: Akihito Goto, Masahiro Sakata, Masaki Yamaguchi
  • Patent number: 10396355
    Abstract: Provided is an anode active material for a secondary battery and a method of fabricating the anode active material. A silicon-based active material composite according to an embodiment of the inventive concept includes silicon and silicon oxide obtained by oxidizing at least a part of the silicon, and an amount of oxygen with respect to a total weight of the silicon and the silicon oxide is restricted to 9 wt % to 20 wt %.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: August 27, 2019
    Assignee: Nexeon Ltd.
    Inventors: Young Tai Cho, Seung Chul Park, Seon Park, Hee Young Seo, Jee Hye Park, Yong Eui Lee, Chul Hwan Kim
  • Patent number: 10373930
    Abstract: The invention discloses a package structure with at least one portion of a first conductive element disposed in a through-opening of a first substrate. A conductive structure is disposed on the first substrate and the first conductive element, wherein the conductive structure is electrically connected to the first substrate and said at least one first I/O terminal of the first conductive element. The conductive structure comprises at least one of a second conductive element, a second substrate or a conductive pattern.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: August 6, 2019
    Assignee: CYNTEC CO., LTD
    Inventors: Jeng-Jen Li, Bau-Ru Lu
  • Patent number: 10367470
    Abstract: The present disclosure relates to a Wafer-Level-Packaged (WLP) Bulk Acoustic Wave (BAW) device that includes a BAW resonator, a WLP enclosure, and a surface mount connection structure. The BAW resonator includes a piezoelectric layer with an opening and a bottom electrode lead underneath the piezoelectric layer, such that a portion of the bottom electrode lead is exposed through the opening of the piezoelectric layer. The WLP enclosure includes a cap and an outer wall that extends from the cap toward the piezoelectric layer to form a cavity. The opening of the piezoelectric layer is outside the cavity. The surface mount connection structure covers a portion of a top surface of the cap and extends continuously over a side portion of the WLP enclosure and to the exposed portion of the bottom electrode lead through the opening of the piezoelectric layer.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: July 30, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Matthew L. Wasilik, Buu Quoc Diep, Ian Y. Yee, Bang Nguyen, Ebrahim Andideh, Robert Kraft
  • Patent number: 10356910
    Abstract: The invention provides a manufacturing method for flexible printed circuit board, by liquefying the flexible insulating material and the metal material, coating the liquefied materials and solidifying the coated layers to form respectively the flexible insulating layer and the anti-EMI layer of the anti-EMI structure. As such, an adhesive layer is eliminated to achieve reducing the thickness of the flexible insulating layer and the anti-EMI layer and the material consumption, resulting in reduced production cost, reduced thickness of the flexible printed circuit board with anti-EMI structure, and improved quality.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: July 16, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Juan Chen
  • Patent number: 10333155
    Abstract: The present invention provides a porous medium with increased hydrophobicity and a method of manufacturing the same, in which a micro-nano dual structure is provided by forming nanoprotrusions with a high aspect ratio by performing plasma etching on the surface of a porous medium with a micrometer-scale surface roughness and a hydrophobic thin film is deposited on the surface of the micro-nano dual structure, thus significantly increasing hydrophobicity. When this highly hydrophobic porous medium is used as a gas diffusion layer of a fuel cell, it is possible to efficiently discharge water produced during electrochemical reaction of the fuel cell, thus preventing flooding in the fuel cell. Moreover, it is possible to sufficiently supply reactant gases such as hydrogen and air (oxygen) to a membrane electrode assembly (MEA), thus improving the performance of the fuel cell.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: June 25, 2019
    Assignees: Hyundai Motor Company, Korea Institute of Science and Technology
    Inventors: Bo Ki Hong, Sae Hoon Kim, Kwang Ryeol Lee, Myoung Woon Moon
  • Patent number: 10332657
    Abstract: A method for forming gold nanowires on a substrate is provided. The method includes a) attaching noble metal nanoparticles onto the substrate; and b) contacting the noble metal nanoparticles with an aqueous solution comprising a ligand, gold ions and a reducing agent, wherein the ligand is an organic compound having a thiol group. Gold nanowires formed by a method according to the method, and an electronic device comprising the gold nanowires are also provided.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: June 25, 2019
    Assignee: Nanyang Technological University
    Inventors: Hongyu Chen, Jiating He, Yawen Wang
  • Patent number: 10319653
    Abstract: A semiconductor apparatus includes a semiconductor device, on-semiconductor-device metal pad and metal interconnect each electrically connected to the semiconductor device, a through electrode and a solder bump each electrically connected to the metal interconnect, a first insulating layer on which the semiconductor device is placed, a second insulating layer formed on the semiconductor device, a third insulating layer formed on the second layer. The metal interconnect is electrically connected to the semiconductor device via the on-semiconductor-device metal pad at an upper surface of the second layer, penetrates the second layer from its upper surface, and is electrically connected to the through electrode at an lower surface of the second layer, and an under-semiconductor-device metal interconnect is between the first layer and the semiconductor device, and the under-semiconductor-device metal interconnect is electrically connected to the metal interconnect at the lower surface of the second layer.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: June 11, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Katsuya Takemura, Kyoko Soga, Satoshi Asai, Kazunori Kondo, Michihiro Sugo, Hideto Kato
  • Patent number: 10319524
    Abstract: A thin-film capacitor includes electrode layers stacked in a stacking direction; dielectric layers stacked between the electrode layers; an opening portion that includes a side surface penetrating at least a part of the electrode layers and at least a part of the dielectric layers in the stacking direction from a top side and a bottom surface exposing one of the electrode layers; and a wiring portion disposed in the opening portion to be separated from the side surface of the opening portion, and electrically connected to the electrode layer exposed from the bottom surface of the opening portion. The dielectric layer that is stacked immediately on the electrode layer exposed from the bottom surface of the opening portion among the dielectric layers includes an extension portion extending in the opening portion from the side surface of the opening portion to the wiring portion side.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: June 11, 2019
    Assignee: TDK CORPORATION
    Inventors: Kenichi Yoshida, Kazuhiro Yoshikawa, Michihiro Kumagae, Norihiko Matsuzaka, Junki Nakamoto
  • Patent number: 10318039
    Abstract: A pressure-sensitive touch panel, a method for manufacturing the pressure-sensitive touch panel, and a touch display screen are provided. The pressure-sensitive touch panel includes a substrate and a touch sensor and a pressure sensor arranged on the substrate. The touch sensor includes a first electrode and a second electrode, and the pressure sensor includes an upper electrode, a lower electrode and a dielectric layer arranged between the upper electrode and the lower electrode. The upper electrode and the first electrode are arranged in the same layer and formed of the same material, the lower electrode and the second electrode are arranged in the same layer and formed of the same material, and the dielectric layer is formed of an elastic insulation material.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: June 11, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jiawei Xu, Qingpu Wang, Youlu Li
  • Patent number: 10306767
    Abstract: A manufacturing method of a substrate structure including vias includes the following steps. A substrate is provided, wherein a material of the substrate includes polyimide. An etching stop layer is formed on the substrate, wherein the etching stop layer covers two opposite surfaces of the substrate. A patterned process is performed on the etching stop layer to form a plurality of openings exposing a part of the substrate. An etching process is performed on the substrate to remove the part of the substrate exposed by the openings and form a plurality of vias.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: May 28, 2019
    Assignee: UNIFLEX Technology Inc.
    Inventors: Yi-Chun Liu, Yuan-Chih Lee, Hung-Tai Ting
  • Patent number: 10269591
    Abstract: A method of selectively removing silicon nitride is provided. The method includes: providing a wafer having silicon nitride on a surface of the wafer; providing a mixture of phosphoric acid and a silicon-containing material; and delivering the mixture to the surface of the wafer to remove the silicon nitride. Single wafer etching apparatuses of selectively removing silicon nitride are also provided.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Hsueh Changchien, Yu-Ming Lee, Chi-Ming Yang
  • Patent number: 10269841
    Abstract: A sensor package includes a sensor, an encapsulation layer, a redistribution layer, a photo-imageable dielectric (PID) layer and via plugs. The encapsulation layer exposes the active surface of the sensor, and the top surface of the encapsulation layer is coplanar with the active surface of the sensor. The redistribution layer covers the top surface of the encapsulation layer and the active surface of the sensor. The PID layer covers the redistribution layer, the encapsulation layer and the active surface of the sensor. The via plugs are disposed around the sensor and through the encapsulation layer. The via plugs are electrically connected to the redistribution layer and the active surface of the sensor. The cross section of the via plug at the top surface of the encapsulation layer has a first hole diameter, and the cross section of the via plug at the bottom surface of the encapsulation layer has a second hole diameter. The first hole diameter is less than the second hole diameter.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: April 23, 2019
    Assignee: PHOENIX & CORPORATION
    Inventors: Che-Wei Hsu, Shih-Ping Hsu
  • Patent number: 10263221
    Abstract: A method for exposing an electrode terminal covered with an organic film in a light-emitting device without damaging the electrode terminal is provided. In a region of the electrode terminal to which electric power from an external power supply or an external signal is input, an island-shaped organic compound-containing layer is formed and the organic film is formed thereover. The organic film is removed by utilizing low adhesion of an interface between the organic compound-containing layer and the electrode terminal, whereby the electrode terminal can be exposed without damage to the electrode terminal.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: April 16, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Chida, Kaoru Hatano, Tomoya Aoyama, Ryu Komatsu, Masatoshi Kataniwa
  • Patent number: 10199215
    Abstract: Methods and apparatus for processing a substrate are described herein. Methods for passivating dielectric materials include forming alkyl silyl moieties on exposed surfaces of the dielectric materials. Suitable precursors for forming the alkyl silyl moieties include (trimethylsilyl)pyrrolidine, aminosilanes, and dichlorodimethylsilane, among others. A capping layer may be selectively deposited on source/drain materials after passivation of the dielectric materials. Apparatus for performing the methods described herein include a platform comprising a transfer chamber, a pre-clean chamber, an epitaxial deposition chamber, a passivation chamber, and an atomic layer deposition chamber.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: February 5, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Abhishek Dube, Schubert S. Chu, Jessica S. Kachian, David Thompson, Jeffrey Anthis
  • Patent number: 10191380
    Abstract: [Problem] To provide a composition capable of improving surface roughness of resist patterns, and also to provide a pattern formation method employing the composition. [Solution] The present invention provides a composition containing a particular nitrogen-containing compound, an anionic surfactant having a sulfo group, and water; and also provides a pattern formation method containing a step of applying the composition to a resist pattern beforehand developed and dried.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: January 29, 2019
    Assignee: AZ Electronic Materials (Luxembourg) S.a.r.l.
    Inventors: Kazuma Yamamoto, Tatsuro Nagahara
  • Patent number: 10181381
    Abstract: A variable capacitor device that includes a dielectric layer comprising a shape-memory polymer, a first metal plate and a second metal plate, wherein the dielectric layer is sandwiched between the first and the second metal plates. The shape-memory polymer has a first thickness at a first temperature under a first external compressive load, a second thickness at a second temperature under a second external compressive load, wherein the first thickness is greater than the second thickness, the second temperature is greater than the first temperature, and the second external compressive load is greater than the first external compressive load. The shape memory polymer having the second thickness is configured to convert to the shape-memory polymer having the first thickness when sequentially subjected to the first external compressive load and the second temperature.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: January 15, 2019
    Assignee: King Abdulaziz University
    Inventors: Faten Ebrahim S. Al-Hazmi, Fahrettin Yakuphanoglu, Ahmed A. Al-Ghamdi, Yusuf Al-Turki
  • Patent number: 10156713
    Abstract: A wavelength variable interference filter includes a fixed reflection film, a movable reflection film, and an actuator that changes a gap between the films. A wavelength of output light is first wavelength ??. A center wavelength in a target wavelength region is measurement center wavelength ?0. A peak center wavelength in reflection characteristics of the movable reflection film is first center wavelength ?1. A peak center wavelength in reflection characteristics of the fixed reflection film is second center wavelength ?2. The gap between the films when light of the first wavelength ?? is transmitted is d?(?1 , ?2). When a pair of optical films face each other, a center wavelength in reflection characteristics of the pair is the measurement center wavelength ?0, and the light of the first wavelength ?? is outputted, the gap between the pair of optical films is d?(?0, ?0). Further, d?(?1, ?2)<d?(?0, ?0).
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: December 18, 2018
    Assignee: Seiko Epson Corporation
    Inventor: Tomonori Matsushita
  • Patent number: 10155371
    Abstract: An automated bonding sequence system and method for customizing a bonding sequence is provided. The method includes the steps of detecting that a first substrate is in close proximity with the a second substrate, during an optical bonding operation, wherein at least the first substrate includes an amount of adhesive for optically bonding to the second substrate, stopping an automated process of optically bonding of the optical bonding operation, in response to the detecting, recording operator feedback control signals, the operator feedback control signals being received from a controller being operated by an operator to contact the first substrate and the second substrate, analyzing the operator feedback control signals to determine a bonding sequence for automatically optically bonding the first substrate and the second substrate, and resuming, by the processor, the automated process of the optical bonding operation.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: December 18, 2018
    Assignee: PRECISION VALVE & AUTOMATION, INC.
    Inventors: Andrew John Nally, Alexander M. Giordano, Edward F. Carey, Jonathan Neal Urquhart
  • Patent number: 10144155
    Abstract: The present invention relates to a production method for a glassy carbon mold, and, more specifically, relates to a production method for a glassy carbon mold including the steps of: placing a mixture having a thermosetting resin, a curing agent, and a viscosity adjusting solvent between a thermosetting resin substrate and a master pattern formed by a micro-nano process; pressing either the master pattern or the thermosetting resin substrate and applying heat to form a cured thermosetting resin pattern part on the substrate; and removing the master pattern, and subjecting the substrate and the cured thermosetting resin pattern.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 4, 2018
    Assignee: CHUNG-ANG UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Seok Min Kim, Jong Won Seok, Tae Hyoung Kim, Jong Hyun Ju
  • Patent number: 10124559
    Abstract: Bulk materials having a kinetically limited nano-scale diffusion bond is provided. The bulk materials having a kinetically limited nano-scale diffusion bond includes transparent material, absorbent opaque material and a diffusion bond. The transparent material has properties that allow an electromagnetic beam of a select wavelength to pass there through without more than minimal energy absorption. The absorbent opaque material has properties that significantly absorb energy from the electromagnetic beam. The diffusion bond is formed by the electromagnetic beam bonding the transparent material to the absorbent opaque material. Moreover, the diffusion bond has a thickness that is less than 1000 nm.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: November 13, 2018
    Assignees: MEDTRONIC, INC., CORNING INCORPORATED
    Inventors: Michael S. Sandlin, David A. Ruben, Raymond M. Karam, Georges Roussos, Thomas M. Wynne
  • Patent number: 10119103
    Abstract: A cleaning liquid including hydrofluoric acid, a tetrazole compound, and water. The tetrazole compound may be represented by the following Formula (B1) in which R1 is a hydrogen atom or an organic group and R2 is a hydrogen atom, a hydroxyl group, a mercapto group, an amino group, or an organic group.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: November 6, 2018
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Tatsuo Goto, Kenji Seki
  • Patent number: 10072929
    Abstract: A circuit device includes a clock signal generation circuit that generates a clock signal through an oscillation circuit, and a detection circuit including a circuit operating through an operation signal based on the clock signal. The clock signal generation circuit includes a first frequency adjustment unit which is capable of adjusting an oscillation frequency before an physical quantity transducer and the circuit device are connected to each other, and a second frequency adjustment unit which is capable of adjusting the oscillation frequency in a state where the physical quantity transducer and the circuit device are connected to each other.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: September 11, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Teppei Higuchi, Katsuhiko Maki
  • Patent number: 10073064
    Abstract: According to a method for manufacturing a device in which an electrode of an element is electrically connected to a penetrating wire in a substrate, a structure is prepared in which the element is arranged on the first substrate having a through hole formed therein: and a second substrate is prepared which has an electroconductive seed layer formed thereon. Then, a wall part is formed on the first substrate; a seed layer is joined to a face on an element side of the structure through a bonding layer; the bonding layer is removed; and the seed layer is exposed in the inside of the opening. The inside of the wall part and the through hole is filled with a conductor, with the use of the seed layer through electrolytic plating.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: September 11, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shinichiro Watanabe, Shinan Wang
  • Patent number: 10062720
    Abstract: The present disclosure relates to an integrated circuit, and an associated method of formation. In some embodiments, the integrated circuit comprises a deep trench grid disposed at a back side of a substrate. A passivation layer lines the deep trench grid within the substrate. The passivation layer includes a first high-k dielectric layer and a second high-k dielectric layer disposed over the first high-k dielectric layer. A first dielectric layer is disposed over the passivation layer, lining the deep trench grid and extending over an upper surface of the substrate. A second dielectric layer is disposed over the first dielectric layer and enclosing remaining spaces of the deep trench grid to form air-gaps at lower portions of the deep trench grid. The air-gaps are sealed by the first dielectric layer or the second dielectric layer below the upper surface of the substrate.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Chih-Hui Huang, Shyh-Fann Ting, Shih Pei Chou, Sheng-Chan Li
  • Patent number: 10062469
    Abstract: Articles with graphene are selectively transparent to electromagnetic radiation. The articles transmit electromagnetic radiation in the infrared and visible light bands while inhibiting incident radio frequency radiation. The articles have high electrical conductivity and may be used in windows and domes.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: August 28, 2018
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Jitendra S. Goela, Nathaniel E. Brese
  • Patent number: 10039193
    Abstract: A method of manufacturing conductive patterns includes the steps of a) printing and curing UV curable inkjet to define a cured inkjet ink pattern on a metal sheet bonded to a non-conductive substrate; b) etching the metal sheet not covered by the cured ink pattern to expose the non-conductive substrate; and c) applying an alkaline solution to dissolve the cured inkjet ink pattern within 5 minutes.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: July 31, 2018
    Assignee: AGFA-GEVAERT
    Inventors: Rita Torfs, Johan Loccufier
  • Patent number: 10021789
    Abstract: An object is to provide a laminated polyimide substrate, and a method for the production thereof, in which various properties are ensured and/or provided by effectively controlling changes over time under stringent conditions, while ensuring sufficient adhesion between a polyimide film and metal layer. A laminated polyimide substrate comprises a polyimide layer, an alkali-treated layer derived from the polyimide layer, and a metal layer, arranged in that order, wherein the alkali-treated layer contains an anionic functional group, and is a laminated structure having a layer containing a metal catalyst arranged on the metal layer side and a layer containing a complex of the metal catalyst arranged on the polyimide layer side.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: July 10, 2018
    Assignee: EBARA-UDYLITE CO., LTD.
    Inventors: Shinya Ochi, Ryuichi Nakagami, Makoto Kohtoku, Mika Hamada
  • Patent number: 10000853
    Abstract: A system and method for removing metal from a substrate in a controlled manner is disclosed. The system includes a chamber, with one or more gas inlets to allow the flow of gasses into the chamber, at least one exhaust pump, to exhaust gasses from the chamber, and a heater, capable of modifying the temperature of the chamber. In some embodiments, one or more gasses are introduced into the chamber at a first temperature. The atoms in these gasses chemically react with the metal on the surface of the substrate to form a removable compound. The gasses are then exhausted from the chamber, leaving the removable compound on the surface of the substrate. The temperature of the chamber is then elevated to a second temperature, greater than the sublimation temperature of the removable compound. This increased temperature allows the removable compound to become gaseous and be exhausted from the chamber.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: June 19, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tsung-Liang Chen, Benjamin Schmiege, Jeffrey W. Anthis, Glen Gilchrist
  • Patent number: 9987830
    Abstract: According to various embodiments, a method for processing a carrier may include: forming a layer structure over the carrier, the layer structure including a support layer and a two-dimensional layer over the support layer; wherein the layer structure has at least one opening that exposes a portion of the carrier; forming an auxiliary layer structure, wherein the auxiliary layer structure at least partially covers the layer structure and at least partially fills the at least one opening; and removing the support layer of the layer structure.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: June 5, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Matthias Koenig, Guenther Ruhl
  • Patent number: 9984923
    Abstract: A method of forming a semiconductor structure includes forming at least one trench in a dielectric layer, forming a barrier layer on a bottom of said at least one trench, sidewalls of said at least one trench and a top surface of the dielectric layer, the barrier layer having a non-uniform thickness, and selectively thinning at least a first portion of the barrier layer using one or more cycles comprising forming an oxidized layer in the first portion of the barrier layer using a neutral beam oxidation and removing the oxidized layer using an etching process.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Cornelius Brown Peethala, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 9981471
    Abstract: The present disclosure relates to a method for the application of an antiwetting coating on at least one surface of a substrate of semiconductor material comprising the steps of: a) applying on said at least one surface a metal layer of a material chosen in the group constituted by noble metals, coining metals, their oxides and their alloys; and b) applying on said metal layer a layer of a thiol of formula R—SH, where R is a linear alkyl chain having from 3 to 20 carbon atoms and, optionally, at least one hetero-atom, for obtaining an antiwetting coating. The disclosure further regards a method for the production of a nozzle plate for ink-jet printing and to an integrated ink-jet printhead provided with a nozzle plate obtained according to the method of the disclosure.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: May 29, 2018
    Assignee: STMicroelectronics S.R.L.
    Inventor: Fabrizio Porro