Forming Or Treating Electrical Conductor Article (e.g., Circuit, Etc.) Patents (Class 216/13)
  • Patent number: 11064611
    Abstract: A method for fabricating a printed circuit, comprising: darkening a surface location of a conductive material with one or more ultrafast pulses of laser radiation and ablating the conductive material at the surface location with one or more longer duration pulses of laser radiation to produce traces or micro via patterns on the surface of a PCB. A hole for a blind micro via is produced by ablating the conductive material at the darkened surface location with one or more longer duration pulses of laser radiation and cleaning a second conductive material under the substrate with one or more further longer duration pulses of laser radiation.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 13, 2021
    Assignee: IPG PHOTONICS CORPORATION
    Inventor: David C. Clark
  • Patent number: 11049889
    Abstract: This disclosure provides an array substrate, a method for fabricating the same, a display panel, and a display device, where a first photo-resist layer is stripped in a changed order in that the first photo-resist layer on a source-drain is stripped through wet etching before a ohm contact layer film and an active layer film are etched in an electrically-conductive channel area (i.e., an electrically-conductive channel of a TFT is etched) to form an ohm contact layer and an active layer.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: June 29, 2021
    Assignees: Beijing BOE Display Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xiao Han, Jinchao Bai, Xiangqian Ding, Huibin Guo
  • Patent number: 11042086
    Abstract: An embodiment of this disclosure provides a nano-imprinting method, including: applying an imprinting adhesive on a to-be-processed layer of a substrate located in an imprinting chamber; charging the imprinting chamber with a preset gas at a temperature higher than a boiling point of the preset gas, and pressing a nano-imprinting template on the imprinting adhesive; reducing an ambient temperature of the imprinting chamber to a temperature lower than the boiling point of the preset gas and maintaining the temperature for a preset time, such that the preset gas becomes a liquid; irradiating ultraviolet light from a side of the nano-imprinting template away from the imprinting adhesive to cure the imprinting adhesive; raising the ambient temperature of the imprinting chamber to be higher than the boiling point of the preset gas, such that the liquefied preset gas turns back into a gas; and demolding the nano-imprinting template from the imprinting adhesive.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: June 22, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yanhui Lu, Xin Gu, Kang Guo, Zhen Liu, Xiao Zhang, Wei Tan
  • Patent number: 11039539
    Abstract: A manufacturing method for flexible printed circuit board is provided, in which a flexible insulating material and a metal material are liquefied and the liquefied materials are coated and solidified to form a flexible insulating layer and an anti-EMI layer of an anti-EMI structure, respectively. As such, an adhesive layer can be eliminated and the thickness of the flexible insulating layer and the anti-EMI layer can be reduced and an amount of materials consumed is also reduced, resulting in reduction of production cost, reduction of thickness of the flexible printed circuit board with anti-EMI structure, and improved quality.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: June 15, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Juan Chen
  • Patent number: 11008644
    Abstract: A method of non-ablatively laser patterning a multi-layer structure, the multi-layer structure including a substrate, a first layer disposed on the substrate, a second layer disposed on the first layer, and a third layer disposed on the second layer, the method including generating at least one laser pulse having laser parameters selected for non-ablatively changing the conductivity a selected portion of the third layer such that the selected portion becomes non-conductive, and directing the pulse to the multi-layer structure, wherein the conductivity of the first layer is not substantially changed by the pulse.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 18, 2021
    Assignee: nLIGHT, Inc.
    Inventors: Adam Dittli, Robert J. Martinsen
  • Patent number: 10981355
    Abstract: Bulk materials having a kinetically limited nano-scale diffusion bond is provided. The bulk materials having a kinetically limited nano-scale diffusion bond includes transparent material, absorbent opaque material and a diffusion bond. The transparent material has properties that allow an electromagnetic beam of a select wavelength to pass there through without more than minimal energy absorption. The absorbent opaque material has properties that significantly absorb energy from the electromagnetic beam. The diffusion bond is formed by the electromagnetic beam bonding the transparent material to the absorbent opaque material. Moreover, the diffusion bond has a thickness that is less than 1000 nm.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: April 20, 2021
    Assignees: Medtronic, Inc, Corning Incorporated
    Inventors: Michael S. Sandlin, David A. Ruben, Raymond M. Karam, Georges Roussos, Thomas M. Wynne
  • Patent number: 10962882
    Abstract: A circuit pattern is quickly created or changed by exposing the circuit pattern on a board without using a photo mask on which the circuit pattern is formed. There is provided a circuit pattern manufacturing apparatus including a forming unit that forms a circuit pattern by irradiating, with a light beam, a circuit pattern forming sheet including an insulating sheet base material layer and a mixture layer made of a mixture containing a conductive material and a photo-curing resin. The forming unit includes, as an optical engine, a housing, a laser diode, a prism mirror, an inclined mirror, a bottom mirror, and a driving mirror.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: March 30, 2021
    Assignee: KANTATSU CO., LTD.
    Inventors: Eiji Oshima, Tomio Kusakabe
  • Patent number: 10957615
    Abstract: A workpiece (100) having substrate, such as a glass substrate, can be etched by a laser or by other means to create recessed features (200, 202). A laser-induced forward transfer (LIFT) process or metal oxide printing process can be employed to impart a seed material (402), such as a metal, onto the glass substrate, especially into the recessed features (200, 202). The seeded recessed features can be plated, if desired, by conventional techniques, such as electroless plating, to provide conductive features (500) with predictable and better electrical properties. The workpieces (100) can be connected in a stacked such that subsequently stacked workpieces (100) can be modified in place.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 23, 2021
    Assignee: ELECTRO SCIENTIFIC INDUSTRIES, INC
    Inventors: Joel Schrauben, Jan Kleinert
  • Patent number: 10947413
    Abstract: A process for chemical mechanical polishing cobalt to planarize the surface and remove at least some of the cobalt from a substrate. The process includes providing a polishing composition, containing, as initial components: water; an oxidizing agent; colloidal silica abrasive particles; aspartic acid or salts thereof; a phosphonic acid having an alkyl group of greater than ten carbon atoms, wherein the phosphonic acid having the alky group of greater than ten carbon atoms is included in amounts sufficient to enable high cobalt removal rates of ?2000 ?/min and substantial cobalt corrosion inhibition; and providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the cobalt is polished away and cobalt corrosion is substantially inhibited.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 16, 2021
    Assignee: Rohm and Haas Electronic Materials CMP Holdings
    Inventor: Murali Ganth Theivanayagam
  • Patent number: 10888003
    Abstract: There is provided a copper foil provided with a carrier exhibiting a high peeling resistance against the developer in the photoresist developing process and achieving high stability of mechanical peel strength of the carrier. The copper foil provided with a carrier comprises a carrier; an interlayer disposed on the carrier, the interlayer having a first surface adjacent to the carrier and containing 1.0 atom % or more of at least one metal selected from the group consisting of Ti, Cr, Mo, Mn, W and Ni and a second surface remote from the carrier and containing 30 atom % or more of Cu; a release layer disposed on the interlayer; and an extremely-thin copper layer disposed on the release layer.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: January 5, 2021
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventor: Yoshinori Matsuura
  • Patent number: 10865484
    Abstract: The invention relates to a solution for etching titanium based materials, comprising from about 27 w % to about 39 w % hydrogen peroxide, from about 0.2 w % to about 0.5 w % potassium hydroxide, and at about 0.002 w % to about 0.02 w % 1,2-Diaminocyclohexane-N,N,N,N Tetra acetic Acid (CDTA), the rest being water, said solution comprising no corrosion inhibitor, and said solution having a pH comprised between about 7 and about 8. The invention further relates to a chemical composition for preparing such a solution by mixing said composition with concentrated hydrogen peroxide, said chemical composition comprising potassium hydroxide from about 5 w % to about 30 w %, C.D.T.A. at a concentration ranging from about 1% to about 5% of the potassium hydroxide concentration, the rest being water.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: December 15, 2020
    Assignee: TECHNIC FRANCE
    Inventors: Christian Pizzetti, Marine Cazes, Jérôme Daviot, Philippe Vernin
  • Patent number: 10844175
    Abstract: A polyamide acid which contains at least one diamine compound selected from among diamine compounds represented by general formula (8) within the range of 3-60 parts by mole in total per 100 parts by mole of all diamine components, while containing a biphenyl tetracarboxylic acid dianhydride within the range of 40-100 parts by mole and a pyromellitic acid dianhydride within the range of 0-60 parts by mole per 100 parts by mole of all acid anhydride components; and a thermoplastic polyimide which is obtained curing this polyamide acid. (In formula (8), linking group X represents a single bond or a divalent group selected from among —CONH—; each Y independently represents a hydrogen atom, a monovalent hydrocarbon group having 1-3 carbon atoms or an alkoxy group; n represents an integer of 0-2; and each of p and q independently represents an integer of 0-4.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 24, 2020
    Assignee: NIPPON STEEL Chemical & Material Co., Ltd.
    Inventors: Yoshiki Suto, Teppei Nishiyama
  • Patent number: 10800972
    Abstract: An etching composition selectively removes a titanium nitride film from a stacked conductive film structure including a titanium nitride (TiN) film and a tantalum nitride (TaN) film. The etching composition configured to etch titanium nitride (TiN) includes 5 wt % to 30 wt % of hydrogen peroxide, 15 wt % to 50 wt % of acid compound, and 0.001 wt % to 5 wt % of corrosion inhibitor, with respect to a total weight of the etching composition, wherein the acid compound includes at least one of phosphoric acid (H3PO4), nitric acid (HNO3), hydrochloric acid (HCl), hydroiodic acid (HI), hydrobromic acid (HBr), perchloric acid (HClO4), silicic acid (H2SiO3), boric acid (H3BO3), acetic acid (CH3COOH), propionic acid (C2H5COOH), lactic acid (CH3CH(OH)COOH), and glycolic acid (HOCH2COOH).
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 13, 2020
    Assignees: Samsung Electronics Co., Ltd., Soulbrain Co., Ltd.
    Inventors: Hyo Sun Lee, Ho Young Kim, Sang Won Bae, Min Goo Kim, Jung Hun Lim, Yong Jae Choi
  • Patent number: 10784454
    Abstract: A method for making a polymer solar cell includes the following steps: placing a portion of a carbon nanotube layer into a polymer solution, wherein the carbon nanotube layer includes a plurality of carbon nanotubes; curing the polymer solution to form a polymer layer including a first polymer surface and a second polymer surface opposite to the first polymer surface, wherein the portion of the carbon nanotube layer is embedded in the polymer layer, and another portion of the carbon nanotube layer is exposed from the polymer layer; and forming a cathode electrode on a surface of the carbon nanotube layer away from the polymer layer, and forming an anode electrode on the first polymer surface, wherein the anode electrode is spaced apart from the carbon nanotube layer.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: September 22, 2020
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wen Ning, Peng Liu, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10757819
    Abstract: A core or sub-composite structure is provided including a dielectric layer between a first conductive film and a second conductive film. The first conductive film may include a first peelable/removable cover layer formed on or coupled to a first conductive layer. The second conductive film may include a second peelable/removable cover layer formed on or coupled to a second conductive layer.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: August 25, 2020
    Assignee: SANMINA CORPORATION
    Inventors: Shinichi Iketani, Dale Kersten
  • Patent number: 10748858
    Abstract: High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 18, 2020
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Ilyas Mohammed, Masud Beroz
  • Patent number: 10741725
    Abstract: To provide a transparent substrate with excellent appearance and with high visibility when observed from a predetermined direction, and a process for producing it. A transparent substrate comprising a substrate having a curved surface on at least a part of its front surface, and an antiglare layer formed on the center region and the edge region of the curved surface, wherein the absolute value of the difference between the 60° specular glossiness at the center region and the 60° specular glossiness at the edge region is higher than 20%.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: August 11, 2020
    Assignee: AGC Inc.
    Inventors: Azusa Takai, Satoshi Mototani
  • Patent number: 10714355
    Abstract: A shape of a hole can be improved. The plasma etching method includes a recess forming of forming a recess having a depth smaller than a thickness of a silicon oxide film by etching the silicon oxide film by plasma; a removing process of removing a reaction product adhering to the recess by plasma generated from a fluorocarbon gas; and a penetrating process of forming a hole penetrating the silicon oxide film by etching the recess, from which the reaction product is removed, by plasma.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 14, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroki Sato, Hisashi Hirose
  • Patent number: 10714545
    Abstract: A method for manufacturing a touch control display screen is provided. The method includes sequentially forming a thin film transistor layer, an OLED display layer, and a thin film encapsulation layer on a substrate; sequentially forming a first insulation layer, a bridge layer, a second insulation layer, a touch control electrode layer, and a protection layer on the thin film encapsulation layer; and using a multi-transmittance mask plate to perform a mask process for the first insulation layer and the second insulation layer, so as to pattern the first insulation layer and the second insulation layer.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: July 14, 2020
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Xiaoliang Feng
  • Patent number: 10707221
    Abstract: Embodiments of an etching method for a material layer of a NAND memory device are disclosed. An example method of chemically etching a material layer on one or more substrates includes mixing an etchant solution within a bath and allowing the etchant solution to reach a quiescent state. After the etchant solution has reached the quiescent state, the method includes loading the one or more substrates into the bath. The one or more substrates includes a plurality of openings having the material layer disposed on an inside surface of the plurality of openings. The method also includes allowing the one or more substrates to remain in the bath for a predetermined time period, such that a thickness of the material layer is reduced by the etchant solution.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: July 7, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Er Wei Wang, Yonggang Yang
  • Patent number: 10699952
    Abstract: Methods comprising depositing a film material to form an initial film in a trench in a substrate surface are described. The film is treated to expand the film to grow beyond the substrate surface.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: June 30, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Atashi Basu, Abhijit Basu Mallick, Ziqing Duan, Srinivas Gandikota
  • Patent number: 10667406
    Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.
    Type: Grant
    Filed: September 16, 2018
    Date of Patent: May 26, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Cheng-Chieh Chiu, Chia-Chan Chang, Chun-Yi Kuo, Yu-Cheng Lin
  • Patent number: 10643780
    Abstract: Techniques and mechanisms for providing a flexible inductor. In an embodiment, the flexible inductor comprises a metal foil or other planar conductor, and inductive bodies disposed on opposite respective sides of the planar conductor. The inductive bodies each comprise a respective flexible suspension media and ferromagnetic particles disposed therein. A thickness of the planar conductor is in a range of 0.1 millimeters (mm) to 0.3 mm. In another embodiment, different layers of one inductive body vary from one another with respect to a thickness, a ferromagnetic material, a suspension media, an average size of ferromagnetic particles or a volume fraction of ferromagnetic particles.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventor: Arvind Sundaram
  • Patent number: 10643810
    Abstract: A zero-power plasmonic microelectromechanical system (MEMS) device is capable of specifically sensing electromagnetic radiation and performing signal processing operations. Such devices are highly sensitive relays that consume no more than 10 nW of power, utilizing the energy in detected electromagnetic radiation to detect and discriminate a target without the need of any additional power source. The devices can continuously monitor an environment and wake up an electronic circuit upon detection of a specific trigger signature of electromagnetic radiation, such as vehicular exhaust, gunfire, an explosion, a fire, a human or animal, and a variety of sources of radiation from the ultraviolet to visible light, to infrared, to terahertz radiation.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: May 5, 2020
    Assignee: Northeastern University
    Inventors: Matteo Rinaldi, Zhenyun Qian, Sungho Kang, Vageeswar Rajaram
  • Patent number: 10633743
    Abstract: A system and method for removing metal from a substrate in a controlled manner is disclosed. The system includes a chamber, with one or more gas inlets to allow the flow of gasses into the chamber, at least one exhaust pump, to exhaust gasses from the chamber, and a heater, capable of modifying the temperature of the chamber. In some embodiments, one or more gasses are introduced into the chamber at a first temperature. The atoms in these gasses chemically react with the metal on the surface of the substrate to form a removable compound. The gasses are then exhausted from the chamber, leaving the removable compound on the surface of the substrate. The temperature of the chamber is then elevated to a second temperature, greater than the sublimation temperature of the removable compound. This increased temperature allows the removable compound to become gaseous and be exhausted from the chamber.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: April 28, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tsung-Liang Chen, Benjamin Schmiege, Jeffrey W. Anthis, Glen Gilchrist
  • Patent number: 10610971
    Abstract: A method for producing a recess or through-opening in a substrate includes applying pulsed laser radiation to the substrate. The laser radiation is focused using an optical system at an original focal depth and, by non-linear self-focusing within the pulse duration of an individual pulse, is also focused by the optical system at a focal depth different from the original focal depth. A difference between the focal depths corresponds to or is greater than the longitudinal extent of the recess or though-opening to be produced. The laser radiation modifies the substrate along a beam axis of the laser radiation in the region of the recess or through-opening, but does not result in removal of the substrate material necessary to form the recess or the through-opening. The substrate material in the modified region is anisotropically removed to produce the recess or through-opening in the substrate.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: April 7, 2020
    Assignee: LPKF LASER & ELECTRONICS AG
    Inventors: Robin Alexander Krueger, Norbert Ambrosius, Roman Ostholt
  • Patent number: 10615210
    Abstract: The present disclosure relates to a semiconductor device, a manufacturing method, a solid state image sensor, and electronic equipment that can achieve further improvement in reliability. Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: April 7, 2020
    Assignee: SONY CORPORATION
    Inventor: Masaki Haneda
  • Patent number: 10578505
    Abstract: A process for manufacturing a MEMS pressure sensor having a micromechanical structure envisages: providing a wafer having a substrate of semiconductor material and a top surface; forming a buried cavity entirely contained within the substrate and separated from the top surface by a membrane suspended above the buried cavity; forming a fluidic-communication access for fluidic communication of the membrane with an external environment, set at a pressure the value of which has to be determined; forming, suspended above the membrane, a plate made of polysilicon, separated from the membrane by an empty space; and forming electrical-contact elements for electrical connection of the membrane and of the plate, which are designed to form the plates of a sensing capacitor, the value of capacitance of which is indicative of the value of pressure to be detected. A corresponding MEMS pressure sensor having the micromechanical structure is moreover described.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: March 3, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Lorenzo Baldo, Sarah Zerbini, Enri Duqi
  • Patent number: 10580819
    Abstract: The present disclosure relates to a solid-state imaging device, a method for manufacturing the same, and an electronic device capable of increasing utilization efficiency of a substrate. The solid-state imaging device includes a first semiconductor substrate provided with a sensor circuit having a photoelectric conversion part, and a second semiconductor substrate and a third semiconductor substrate provided with respective circuits different from the sensor circuit. The first semiconductor substrate, the second semiconductor substrate, and the third semiconductor substrate are stacked on each other in three layers, and a metal element for an electrode constituting an electrode for external connection is disposed in the first semiconductor substrate. An electrode for a measuring terminal is disposed within the second semiconductor substrate or the third semiconductor substrate, and the first semiconductor substrate is stacked after performing a predetermined measurement.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 3, 2020
    Assignee: Sony Corporation
    Inventor: Hiroshi Takahashi
  • Patent number: 10566386
    Abstract: A method of manufacturing a variable memory device includes forming a switching layer on a first conductive layer, forming a heating layer on the switching layer, the heating layer extending in a first direction, performing a first patterning process on the first conductive layer, the switching layer, and the heating layer to form a first trench extending in a second direction intersecting the first direction, forming variable resistance patterns on the heating layer, forming a second conductive layer on the variable resistance patterns, and performing a second patterning process on the switching layer, the heating layer, and the second conductive layer to form a second trench extending in the first direction and being between the variable resistance patterns.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ji-Hyun Jeong
  • Patent number: 10545594
    Abstract: An array substrate includes a substrate, a first signal line and a second signal line on the substrate, an insulating layer covering the first signal line and the second signal line, and a groove penetrating through the insulating layer. The first signal line and the second signal line are arranged in a same layer and separated from each other. The groove is between the first signal line and the second signal line.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: January 28, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Chong Liu, Haisheng Zhao, Zhilian Xiao, Hongxi Xiao, Wei Wang, Xiaoguang Pei
  • Patent number: 10538090
    Abstract: A method for manufacturing a perforated substrate includes forming a through-hole extending through a substrate from a first surface to a second surface opposite the first surface; forming a film on the first surface, a sidewall of the through-hole, and the second surface; forming a resist on the first surface; patterning the resist such that the resist closes an opening of the through-hole in the first surface; etching the film on the first surface using the resist as a mask; before the etching step, forming an inspection member on the second surface such that the inspection member closes an opening of the through-hole in the second surface; and determining whether there is a film patterning defect or a flaw that causes a film patterning defect.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 21, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Seiichiro Yaginuma, Masataka Nagai, Masaya Uyama
  • Patent number: 10510992
    Abstract: A method for exposing an electrode terminal covered with an organic film in a light-emitting device without damaging the electrode terminal is provided. In a region of the electrode terminal to which electric power from an external power supply or an external signal is input, an island-shaped organic compound-containing layer is formed and the organic film is formed thereover. The organic film is removed by utilizing low adhesion of an interface between the organic compound-containing layer and the electrode terminal, whereby the electrode terminal can be exposed without damage to the electrode terminal.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 17, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Chida, Kaoru Hatano, Tomoya Aoyama, Ryu Komatsu, Masatoshi Kataniwa
  • Patent number: 10497648
    Abstract: An embedded electronics package and method of manufacture includes a support substrate, a power semiconductor component coupled to a first side of the support substrate, and a logic semiconductor component coupled to a second side of the support substrate, opposite the first side. A first insulating material surrounds the logic semiconductor component. A logic interconnect layer is electrically coupled to the logic semiconductor component by at least one conductive micro-via extending through a portion of the first insulating material. A power interconnect layer is electrically coupled to the power semiconductor component by at least one conductive macro-via extending through a thickness of the support substrate. The power interconnect layer is thicker than the logic interconnect layer.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: December 3, 2019
    Assignee: General Electric Company
    Inventor: Raymond Albert Fillion
  • Patent number: 10468202
    Abstract: A conductive paper electrode includes a paper, a carbon powder layer, a graphite layer and a nanostructural layer. The carbon powder layer is positioned over the paper. The graphite layer is positioned over the carbon powder layer. The nanostructural layer is positioned over the graphite layer. An electrochemical capacitor includes two conductive paper electrodes and an electrolyte interposed therebetween.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: November 5, 2019
    Assignee: NATIONAL SYNCHROTRON RADIATION RESEARCH CENTER
    Inventors: Ming-Jay Deng, Kueih-Tzu Lu, Jin-Ming Chen
  • Patent number: 10468267
    Abstract: Exemplary cleaning or etching methods may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. Methods may include forming a plasma within the remote plasma region to generate plasma effluents of the fluorine-containing precursor. The methods may also include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned within the processing region, and the substrate may include a region of exposed oxide and a region of exposed metal. Methods may also include providing a hydrogen-containing precursor to the processing region. The methods may further include removing at least a portion of the exposed oxide.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: November 5, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Zhijun Chen, Lin Xu, Anchuan Wang, Nitin Ingle
  • Patent number: 10468190
    Abstract: A capacitor component includes a body with a plurality of first and second internal electrodes alternately stacked with dielectric layers interposed therebetween. First and second connection electrodes extend in a thickness direction of the body and are respectively connected to the first and second internal electrodes. First and second lower electrodes are on a lower surface of the body and are respectively connected to the first and second connection electrodes.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong Won Seo, Jin Kyung Joo, Taek Jung Lee, Jin Woo Chun
  • Patent number: 10460852
    Abstract: The present invention relates to an electrode having a multilayer nanomesh structure using single-crystalline copper and a method for manufacturing same, the electrode comprising: a substrate; a single-crystalline copper electrode layer formed on the substrate and having a hive-shaped pattern with a nano-sized line width; and a metal oxide layer formed on the single-crystalline copper electrode layer, this providing an electrode having excellent optical transmittance, low electrical sheet resistance, and excellent mechanical stability. The present invention is technically characterized by an electrode having a multilayer nanomesh structure using single-crystalline copper, the electrode comprising: a substrate; a single-crystalline copper electrode layer formed on the substrate and having a hive-shaped pattern with a nano-sized line width; and a metal oxide layer formed on the single-crystalline copper electrode layer.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: October 29, 2019
    Assignee: PUSAN NATIONAL UNIVERSITY INDUSTRIAL-UNIVERSITY COOPERATION FOUNDATION
    Inventors: Se-young Jeong, Ji-young Kim, Won-kyung Kim
  • Patent number: 10424716
    Abstract: A method for producing a piezoelectric device includes a laminate formation step in which a laminate including a piezoelectric thin film, a support substrate, a metal layer, and a silicon oxide film respectively stacked on both of an upper surface and a lower surface of the metal layer interposed between the piezoelectric thin film and the support substrate is formed, a semi-conducting layer formation step in which a semi-conducting layer is formed by oxidizing the metal layer, and a functional electrode formation step in which a functional electrode that is electro-mechanically coupled to the piezoelectric thin film is formed on a first principal surface of the piezoelectric thin film. The semi-conducting layer is a layer composed of a mixture of a metal constituting the metal layer and an oxide thereof, or a layer composed of a semiconductor which is an oxide of a metal constituting the metal layer.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: September 24, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takashi Iwamoto
  • Patent number: 10396355
    Abstract: Provided is an anode active material for a secondary battery and a method of fabricating the anode active material. A silicon-based active material composite according to an embodiment of the inventive concept includes silicon and silicon oxide obtained by oxidizing at least a part of the silicon, and an amount of oxygen with respect to a total weight of the silicon and the silicon oxide is restricted to 9 wt % to 20 wt %.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: August 27, 2019
    Assignee: Nexeon Ltd.
    Inventors: Young Tai Cho, Seung Chul Park, Seon Park, Hee Young Seo, Jee Hye Park, Yong Eui Lee, Chul Hwan Kim
  • Patent number: 10398026
    Abstract: A laminated substrate includes: a first substrate; a second substrate having a through-hole; a third substrate; a first adhesive layer bonding a rear surface of the first substrate and a front surface of the second substrate; a second adhesive layer bonding a rear surface of the second substrate and a front surface of the third substrate; a first post penetrating through the first adhesive layer, electrically connecting the first substrate to the second substrate, and made of an alloy of a high melting point metal and a low melting point metal; a second post penetrating through the second adhesive layer, electrically connecting the second substrate to the third substrate, and made of an alloy of the high melting point metal and the low melting point metal; and an electronic component fixed to the front surface of the third substrate and disposed in the through-hole of the second substrate.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: August 27, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, Hitachi Chemical Company, Ltd.
    Inventors: Akihito Goto, Masahiro Sakata, Masaki Yamaguchi
  • Patent number: 10373930
    Abstract: The invention discloses a package structure with at least one portion of a first conductive element disposed in a through-opening of a first substrate. A conductive structure is disposed on the first substrate and the first conductive element, wherein the conductive structure is electrically connected to the first substrate and said at least one first I/O terminal of the first conductive element. The conductive structure comprises at least one of a second conductive element, a second substrate or a conductive pattern.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: August 6, 2019
    Assignee: CYNTEC CO., LTD
    Inventors: Jeng-Jen Li, Bau-Ru Lu
  • Patent number: 10367470
    Abstract: The present disclosure relates to a Wafer-Level-Packaged (WLP) Bulk Acoustic Wave (BAW) device that includes a BAW resonator, a WLP enclosure, and a surface mount connection structure. The BAW resonator includes a piezoelectric layer with an opening and a bottom electrode lead underneath the piezoelectric layer, such that a portion of the bottom electrode lead is exposed through the opening of the piezoelectric layer. The WLP enclosure includes a cap and an outer wall that extends from the cap toward the piezoelectric layer to form a cavity. The opening of the piezoelectric layer is outside the cavity. The surface mount connection structure covers a portion of a top surface of the cap and extends continuously over a side portion of the WLP enclosure and to the exposed portion of the bottom electrode lead through the opening of the piezoelectric layer.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: July 30, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Matthew L. Wasilik, Buu Quoc Diep, Ian Y. Yee, Bang Nguyen, Ebrahim Andideh, Robert Kraft
  • Patent number: 10356910
    Abstract: The invention provides a manufacturing method for flexible printed circuit board, by liquefying the flexible insulating material and the metal material, coating the liquefied materials and solidifying the coated layers to form respectively the flexible insulating layer and the anti-EMI layer of the anti-EMI structure. As such, an adhesive layer is eliminated to achieve reducing the thickness of the flexible insulating layer and the anti-EMI layer and the material consumption, resulting in reduced production cost, reduced thickness of the flexible printed circuit board with anti-EMI structure, and improved quality.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: July 16, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Juan Chen
  • Patent number: 10332657
    Abstract: A method for forming gold nanowires on a substrate is provided. The method includes a) attaching noble metal nanoparticles onto the substrate; and b) contacting the noble metal nanoparticles with an aqueous solution comprising a ligand, gold ions and a reducing agent, wherein the ligand is an organic compound having a thiol group. Gold nanowires formed by a method according to the method, and an electronic device comprising the gold nanowires are also provided.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: June 25, 2019
    Assignee: Nanyang Technological University
    Inventors: Hongyu Chen, Jiating He, Yawen Wang
  • Patent number: 10333155
    Abstract: The present invention provides a porous medium with increased hydrophobicity and a method of manufacturing the same, in which a micro-nano dual structure is provided by forming nanoprotrusions with a high aspect ratio by performing plasma etching on the surface of a porous medium with a micrometer-scale surface roughness and a hydrophobic thin film is deposited on the surface of the micro-nano dual structure, thus significantly increasing hydrophobicity. When this highly hydrophobic porous medium is used as a gas diffusion layer of a fuel cell, it is possible to efficiently discharge water produced during electrochemical reaction of the fuel cell, thus preventing flooding in the fuel cell. Moreover, it is possible to sufficiently supply reactant gases such as hydrogen and air (oxygen) to a membrane electrode assembly (MEA), thus improving the performance of the fuel cell.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: June 25, 2019
    Assignees: Hyundai Motor Company, Korea Institute of Science and Technology
    Inventors: Bo Ki Hong, Sae Hoon Kim, Kwang Ryeol Lee, Myoung Woon Moon
  • Patent number: 10319524
    Abstract: A thin-film capacitor includes electrode layers stacked in a stacking direction; dielectric layers stacked between the electrode layers; an opening portion that includes a side surface penetrating at least a part of the electrode layers and at least a part of the dielectric layers in the stacking direction from a top side and a bottom surface exposing one of the electrode layers; and a wiring portion disposed in the opening portion to be separated from the side surface of the opening portion, and electrically connected to the electrode layer exposed from the bottom surface of the opening portion. The dielectric layer that is stacked immediately on the electrode layer exposed from the bottom surface of the opening portion among the dielectric layers includes an extension portion extending in the opening portion from the side surface of the opening portion to the wiring portion side.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: June 11, 2019
    Assignee: TDK CORPORATION
    Inventors: Kenichi Yoshida, Kazuhiro Yoshikawa, Michihiro Kumagae, Norihiko Matsuzaka, Junki Nakamoto
  • Patent number: 10318039
    Abstract: A pressure-sensitive touch panel, a method for manufacturing the pressure-sensitive touch panel, and a touch display screen are provided. The pressure-sensitive touch panel includes a substrate and a touch sensor and a pressure sensor arranged on the substrate. The touch sensor includes a first electrode and a second electrode, and the pressure sensor includes an upper electrode, a lower electrode and a dielectric layer arranged between the upper electrode and the lower electrode. The upper electrode and the first electrode are arranged in the same layer and formed of the same material, the lower electrode and the second electrode are arranged in the same layer and formed of the same material, and the dielectric layer is formed of an elastic insulation material.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: June 11, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jiawei Xu, Qingpu Wang, Youlu Li
  • Patent number: 10319653
    Abstract: A semiconductor apparatus includes a semiconductor device, on-semiconductor-device metal pad and metal interconnect each electrically connected to the semiconductor device, a through electrode and a solder bump each electrically connected to the metal interconnect, a first insulating layer on which the semiconductor device is placed, a second insulating layer formed on the semiconductor device, a third insulating layer formed on the second layer. The metal interconnect is electrically connected to the semiconductor device via the on-semiconductor-device metal pad at an upper surface of the second layer, penetrates the second layer from its upper surface, and is electrically connected to the through electrode at an lower surface of the second layer, and an under-semiconductor-device metal interconnect is between the first layer and the semiconductor device, and the under-semiconductor-device metal interconnect is electrically connected to the metal interconnect at the lower surface of the second layer.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: June 11, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Katsuya Takemura, Kyoko Soga, Satoshi Asai, Kazunori Kondo, Michihiro Sugo, Hideto Kato
  • Patent number: 10306767
    Abstract: A manufacturing method of a substrate structure including vias includes the following steps. A substrate is provided, wherein a material of the substrate includes polyimide. An etching stop layer is formed on the substrate, wherein the etching stop layer covers two opposite surfaces of the substrate. A patterned process is performed on the etching stop layer to form a plurality of openings exposing a part of the substrate. An etching process is performed on the substrate to remove the part of the substrate exposed by the openings and form a plurality of vias.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: May 28, 2019
    Assignee: UNIFLEX Technology Inc.
    Inventors: Yi-Chun Liu, Yuan-Chih Lee, Hung-Tai Ting