Abstract: An aqueous slurry-less composition for chemical-mechanical-polishing of a silicon dioxide workpiece comprising: a cationic surfactant that is soluble and ionized at neutral to alkaline pH conditions, in which the cationic surfactant is present in an aqueous slurry-less composition in an amount less than its critical micelle concentration.

Abstract: The method for producing a micromechanical component includes the following steps: producing a semi-finished micromechanical component; producing openings and forming a cavity; sealing the opening with sealing lids; removing material on the top surface of the first membrane layer, the surface of the first membrane layer being exposed and planarized. The invention also relates to a micromechanical component which can be produced according to the above method and to its use in sensors such as pressure sensors, microphones, or acceleration sensors.

Abstract: A substrate on which a plurality of thin films having a plurality of cross-sections corresponding to the cross-section of a micro-structure are formed is placed on a substrate holder. The substrate holder is elevated to bond a thin film formed on the substrate to the surface of a stage, and by lowering the substrate holder, the thin film is separated from the substrate and transferred to the stage side. The transfer process is repeated to laminate a plurality of thin films on the stage and to form the micro-structure. Accordingly, there are provided a micro-structure having high dimensional precision, especially high resolution in the lamination direction, which can be manufactured from a metal or an insulator such as ceramics and can be manufactured in the combined form of structural elements together, and a manufacturing method and an apparatus thereof.

Abstract: A method of using a finishing element having a fixed abrasive finishing surface including organic boundary lubricants for finishing semiconductor wafers is described. The organic lubricants form an organic lubricating boundary layer in the operative finishing interface in a preferred coefficient of friction range. The selected coefficient of friction helps improve finishing and reduces unwanted surface defects. Differential lubricating boundary layer method are described to differentially finish semiconductor wafers. Planarization and localized finishing can be improved using differential lubricating boundary layer methods of finishing.

Abstract: A plasma polishing apparatus has a table which holds a wafer and is rotated at a high speed by a drive base. The drive base is supported on a horizontal drive stage, so that the table is linearly and reciprocally movable. A plasma generator for converting a process gas into a plasma by high-frequency inductive coupling is arranged above the table. The plasma generator has an outlet port from which the plasma flows out toward the target surface of the wafer. The plasma from the outlet port is drawn upon high-speed rotation of the wafer, diffused as a laminar flow on the target surface of the wafer, and uniformly polishes the entire target surface.

Abstract: The invention provides a method of planarizing an irregular surface of a semiconductor wafer. In one embodiment, the method comprises applying a photoresist material over recessed areas and protruding areas of the irregular surface, etching the photoresist, etching partially into protruding areas of the irregular surface to remove a portion of the irregular surface, and polishing the irregular surface to a substantially planar surface. In some embodiments method may include chemically and mechanically polishing the irregular surface.

Abstract: A wafer flattening process and system enables a reduction of the surface roughness of a wafer resulting from local etching. A silicon wafer W is brought into close proximity to a nozzle portion 20 to feed SF6 gas to an alumina discharge tube 2, a plasma generator 1 is used to cause plasma discharge and spray a first activated species gas from the nozzle portion 20 to the silicon wafer W side, an X-Y drive mechanism 4 is used to make the nozzle portion 20 scan to perform a local etching step. Then the silicon wafer W is moved away from the nozzle portion 20 and O2 gas and CF4 gas are fed to the alumina discharge tube. At this time, the O2 gas is set to be greater in amount than the CF4 gas. When this mixed gas is made to discharge to generate plasma, a second activated species gas diffuses from the nozzle portion 20 to the entire surface of the silicon wafer W.

Abstract: A method for fabricating stacked vias for microelectronic components. The method has a first step of providing a first patterned interconnect layer on a substrate. A first insulating layer is then applied on the first interconnect layer. A first via is formed in the first insulating layer and is in contact with the first interconnect layer. A second patterned interconnect layer is applied on the first insulating layer, leaving free a region around the first via. A second insulating layer is then deposited on the second interconnect layer and on the region left free around the first via. A second via is formed in the second insulating layer in such a way that it meets the first via directly.

Abstract: A method for manufacturing a planar reflective light valve backplane includes the steps of providing a substrate (e.g., a reflective backplane) including a plurality of surface projections (e.g., pixel mirrors) defining gaps therebetween, forming an etch-resistant layer on the substrate, forming a fill layer on the etch resistant layer, and etching the fill layer to expose portions of the etch resistant layer overlying the projections, leaving a portion of the fill layer in the gaps. A particular method includes an optional step of forming a protective layer over the exposed portions of the etch-resistant layer and the fill layer. In another particular method, the etch resistant layer includes an optical thin film layer and an etch-resistant cap layer.

Abstract: Planarizing machines, carrier heads for planarizing machines and methods for planarizing microelectronic-device substrate assemblies in mechanical or chemical-mechanical planarizing processes. In one embodiment of the invention, a carrier head includes a backing plate, a bladder attached to the backing plate, and a retaining ring extending around the backing plate. The backing plate has a perimeter edge, a first surface, and a second surface opposite the first surface. The second surface of the backing plate can have a perimeter region extending inwardly from the perimeter edge and an interior region extending inwardly from the perimeter region. The perimeter region, for example, can have a curved section extending inwardly from the perimeter edge of the backing plate or from a flat rim at the perimeter edge. The curved section can curve toward and/or away from the first surface to influence the edge pressure exerted against the substrate assembly during planarization.

Abstract: The inventive method cleans residual titanium accumulations and other undesirable materials from a planarized surface of a wafer to produce a planarized surface with less than about fifty defects per wafer. After a metallic layer of material has been planarized using a CMP process, loose residual particles of undesirable material are removed from the planarized surface. The residual titanium accumulations remaining on the planarized surface are then detached from the planarized surface, which produces additional, new particles on the surface of the wafer. The additional particles produced by the detaching step are then scrubbed from the planarized surface until the planarized surface has less than approximately 50 defects per wafer.

Abstract: Fabrication of an MO disc, the formation of a master pattern of servo and track information, and the subsequent transfer of that pattern to a series of pits and grooves on a substrate. On top of that substrate, at least one sacrificial layer is provided atop a relatively hard layer. The recording stack may be provided with both silicon nitride and silicon dioxide top layers, with the silicon dioxide layer acting as a sacrificial layer to ensure that the hard layer, of silicon nitride, remains at the end of the process. A layer of aluminum or aluminum alloy may be deposited, with the aluminum plugs filling the grooves and pits (created by the embossed servo information) to a level higher than any of the adjacent layers of silicon dioxide, silicon nitride, or similar dielectric layer.

Abstract: The present invention is for a method wherein a printed circuit board can be fabricated in an electroless process with a minimum number of manufacturing steps using mild etchant conditions on an intermediary seed layer to produce low-defect, fine conductive line printed circuit boards.

Abstract: The invention concerns a PC board with laminates for electrical circuits, the PC board comprising at least one carrier (1) and at least one copper surface layer (7), intended to, after the removal of selected parts, e.g. by etching, function as conductors on the PC board. The new thing is that the carrier at least at some parts has a surface roughness of up to mainly the same size as the thickness of the copper layer and that at least at the above named rough parts is arranged a surface levelling layer (5a,b) between the carrier (1) and the copper layer (7). Further, the invention concerns a method for producing PC board laminate for electrical circuits as above, the laminate comprising a copper layer and a carrier that has a surface roughness of mainly the same size as the thickness of the copper layer.

Abstract: Within a method for forming an aperture fill layer within an aperture there is first provided a topographic substrate which has formed therein a pair of mesas which defines an aperture. There is then formed over the topographic substrate and into the aperture a blanket aperture fill layer while employing a high density plasma chemical vapor deposition (HDP-CVD) method, where the blanket aperture fill layer is formed to a thickness greater than a depth of the aperture while forming a pair of protrusions over the pair of mesas. There is then etched, while employing a sputter etch method, the blanket aperture fill layer to form an etched blanket aperture fill layer such that the pair of protrusions of the blanket aperture fill layer formed over the pair of mesas is etched more rapidly than a portion of the blanket aperture fill layer formed within the aperture.

Abstract: A method of manufacturing a semiconductor device having rectangular cross-sectional interfaces between a conductive line and a conductive via. A first layer of photoresist is patterned to expose portions of the semiconductor device under which conductive wires and combination conductive wires and vias are to be formed. A second layer of photoresist is patterned to expose portions of the semiconductor device under which combination conductive wires and vias are to be formed. A second layer of interlayer dielectric in which conductive wires are to be formed and a first layer of interlayer dielectric in which conductive vias are to be formed are simultaneously anisotropically etched to form cavities, which are simultaneously filled with a conductive material.

Abstract: A dual damascene structure is created in a dielectric layer, the structure contains a barrier layer while a cap layer may or may not be provided over the layer of dielectric for further protection of the dual damascene structure. The surface of the copper in the dual damascene structure is recessed, a thin film is deposited and planarized/partially removed by either CMP or a plasma etch thereby providing a sturdy surface above the copper of the dual damascene structure that prevents dishing and erosion of this surface.

Abstract: A substrate on which a plurality of thin films having a plurality of cross-sections corresponding to the cross-section of a micro-structure are formed is placed on a substrate holder. The substrate holder is elevated to bond a thin film formed on the substrate to the surface of a stage, and by lowering the substrate holder, the thin film is separated from the substrate and transferred to the stage side. The transfer process is repeated to laminate a plurality of thin films on the stage and to form the micro-structure. Accordingly, there are provided a micro-structure having high dimensional precision, especially high resolution in the lamination direction, which can be manufactured from a metal or an insulator such as ceramics and can be manufactured in the combined form of structural elements together, and a manufacturing method and an apparatus thereof.

Abstract: A system and method for decapsulating a chip-scale package having a first width are disclosed. The method and system include coupling the chip-scale package to a substantially rigid receptacle. The receptacle has a second width and a periphery. The second width is larger than the first width. The chip-scale package does not extend to the periphery of the receptacle. The method and system further include holding the receptacle in proximity to the periphery and decapsulating the chip-scale package.

Abstract: A method for manufacturing a mechanical grating device is presented. The device consists of a plurality of parallel-suspended ribbons that are deformed using, for example, an electrostatic force to actuate alternate ribbons. Actuation is a deformation of the ribbon resulting from an applied voltage to affect the height of the ribbons above a substrate.

Abstract: The present invention discloses a method for fabricating a trench isolation structure in a semiconductor device. A first insulating layer and a first anti-oxidation layer are formed on a semiconductor substrate. Then, a predetermined region of the surface of the substrate is exposed. Thereafter, a trench is formed by etching the exposed surface of the substrate. A second insulating layer is formed along an inner surface of the trench. Next, the first anti-oxidation layer is isotropically etched to a predetermined thickness. A second anti-oxidation layer is formed on the resultant structure. A third insulating layer is formed on the second anti-oxidation layer. The third insulating layer and the first and second anti-oxidation layers are planarized. Finally, the first anti-oxidation layer is removed.

Abstract: A method of polishing selected ceramics and metals is provided wherein the selected ceramic or metal material is rubbed against a solid surface in the presence of a nonabrasive liquid medium which only attacks the selected ceramic or metal material under friction. Examples of materials for the tribochemical polishing process includes ceramics such as silicon, silicon nitride, silicon carbide, silicon oxide, titanium carbide and aluminum nitride and metals such as tungsten. Both ceramic and metal surfaces can be polished, as in a damascene structure of an integrated circuit.

Abstract: The process proposed allows provision of a matrix topography for electronic memory devices using self-alignment etchings capable of removing those spurious electrical contacts between adjacent memory cells. The self-aligned etching process proposed for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate. Provided on the semiconductor substrate is a plurality of active elements extending along separate parallel lines, e.g., memory cell bit lines, and comprising gate regions formed by a first conducting layer, a dielectric interpoly layer and a second conducting layer with said regions being insulated from each other by dielectric insulation films to form said architecture with said word lines being defined photolithographically by protective strips.

Abstract: A two-step chemical mechanical polishing (CMP) process is provided for low dishing of metal lines in trenches in an insulation (oxide) layer, e.g., of silicon dioxide of a thickness of about 100-2000 nm, of a semiconductor wafer, e.g., of silicon, during its fabrication. The first step involves chemically mechanically polishing a metal layer, e.g., of copper of a thickness of about 200-2000 nm, disposed on the oxide layer and having a lower portion located in the trenches for forming metal lines and an upper portion overlying the lower portion. The first step polishing is effected at a high downforce, e.g., 3-8 psi, to remove at a high rate the upper portion of the metal layer substantially without removing the lower portion thereof and substantially without dishing of the lower portion located in the trenches. The second step involves continuing the CMP at a lower downforce, e.g.

Abstract: A new method of forming metal interconnects with air gaps between adjacent interconnects in the manufacture of an integrated circuit device is achieved. A semiconductor substrate is provided. The metal interconnects are formed overlying the semiconductor substrate. A silicon nitride liner layer is deposited. A gap filling oxide layer is deposited to fill gaps between adjacent metal interconnects. The gap filling oxide layer is polished down to the silicon nitride liner layer. A silicon nitride thin layer is deposited. The silicon nitride thin layer is patterned using an oversized, reverse mask of the metal interconnects. The patterning of the silicon nitride thin layer creates openings to thereby expose a portion of the gap filling oxide. The gap filling oxide layer is etched away. A self-sealing oxide layer is deposited overlying the silicon nitride thin layer and the silicon nitride liner layer.

Abstract: Chemical mechanical polishing of a silicon layer, such as a polycrystalline silicon, is improved by initially chemical mechanically polishing the silicon layer with an oxide-polishing slurry. Then the silicon layer is chemical mechanically polished with a silicon-polishing slurry until the substrate is planarized.

Abstract: A method for forming copper interconnects, without inducing copper diffusion, by eliminating the copper chemical-mechanical polishing process. A semiconductor structure is provided having a first metal layer thereover. A first inter-metal dielectric layer is formed over the first metal layer and planarized. A first resist layer is formed over the first inter-metal dielectric layer, and the first resist layer and the first inter-metal dielectric layer are patterned to form via openings with the first metal layer forming the bottoms of the via openings. A barrier/seed layer, comprising a barrier layer and an overlying seed layer, is formed on the sidewalls and bottoms of the via openings. A self-align layer, composed of a high-resistivity, inorganic material, is formed over the barrier/seed layer. The self-align layer is patterned to reform the via openings and to form trench openings, exposing the barrier/seed layer on the bottoms and sidewalls of the via openings and on the bottoms of the trench openings.

Abstract: A method of fabricating a flux concentrator for use in magnetic memory devices including the steps of providing at least one magnetic memory bit (10) and forming proximate thereto a material stack defining a copper (Cu) damascene bit line (56) including a flux concentrating layer (52). The method includes the steps of depositing a bottom dielectric layer (32), an optional etch stop (34) layer, and a top dielectric layer (36) proximate the magnetic memory bit (10). A trench (38) is etched in the top dielectric layer (36) and the bottom dielectric layer (32). A first barrier layer (42) is deposited in the trench (38). Next, a metal system (29) is deposited on a surface of the first barrier layer (42). The metal system (29) includes a copper (Cu) seed material (44), and a plated copper (Cu) material (46), a first outside barrier layer (50), a flux concentrating layer (52), and a second outside barrier layer (54). The metal system (29) is patterned and etched to define a copper (Cu) damascene bit line (56).

Abstract: A method for forming a self-align stop layer for borderless contact process is disclosed. In one embodiment, the present invention provides a semiconductor device which can simplify borderless contact fabrication, which includes providing a substrate incorporating a device. Sequentially, a pad oxide, a pad polysilicon, and a first dielectric layer are formed over the substrate. A first photoresist layer is formed over the first dielectric layer and then the first dielectric layer, the pad polysilicon, the pad oxide, and the substrate are etched using the photoresist layer as a mask to form an isolation inside said substrate. Consequentially, a second dielectric layer is deposited over the device and the isolation inside the substrate. The second dielectric layer is removed wherein the surface of the second dielectric layer is lower than the top surface of the substrate by a chemical mechanical polishing (CMP) and etching back.

Abstract: A method for manufacturing an even dielectric layer. A substrate having a patterned conductive layer formed thereon is provided. A first dielectric layer with a relatively high dopant dosage is formed on the substrate and the patterned conductive layer. A second dielectric layer with a relatively low dopant dosage is formed on the first dielectric layer. A chemical-mechanical polishing process is formed.

Abstract: A surface treatment method for use in integrated circuit fabrication includes providing a substrate assembly having a surface. A liquid is provided adjacent the surface resulting in an interface therebetween. An electrical potential difference is applied across the interface and the surface is treated as the electrical potential difference is applied across the interface. The liquid may be a planarization liquid when the treatment of the surface includes planarizing a substrate assembly or the liquid may be a coating material when the treatment of the surface includes applying a coating material on the surface.

Abstract: An apparatus and method is disclosed; both of which use electrochemistry to selectively grow and remove hard oxide coatings on metals, and capacitive double layers on non-metals and semiconductors in order to predict and control the rate of surface abrasion during planarization of the surface of such materials.

Abstract: Chemical mechanical polishing of a silicon layer, such as a polycrystalline silicon, is improved by initially chemical mechanically polishing the silicon layer with an oxide-polishing slurry. Then the silicon layer is chemical mechanically polished with a silicon-polishing slurry until the substrate is planarized.

Abstract: A new method for removing particle residue from the surface of semiconductor wafers that contain wolfram plugs. A series of polishing and buffing steps is performed; the first of this is a wolfram CMP using a hard polishing pad. An oxide buffing operation is further performed on the wafer surface; a soft pad is used for this buffing operation. The buffing operation is followed by a wolfram CMP that is applied for a short period of time using a soft polishing pad thereby removing the protruding top of the wolfram plug and the oxide particles from the vicinity of the wolfram plugs.

Abstract: Particulate and metal ion contamination is removed from a surface, such as a semiconductor wafer containing copper damascene or dual damascene features, employing aqueous composition comprising a fluoride containing compound; a dicarboxylic acid and/or salt thereof; and a hydroxycarboxylic acid and/or salt thereof.

Abstract: A method of planarizing a structure having an interpoly layer is disclosed. The method includes forming an undoped silica glass layer on at least a polysilicon region formed on a semiconductor substrate. Next, a spin-on-glass layer is formed over the undoped silica glass layer. Finally, the spin-on-glass layer is etched back, thereby planarizing the structure having the interpoly layer.

Abstract: A process for forming a nanoporous dielectric silica coating on a surface of a substrate. The process includes spin-depositing alkoxysilane composition onto a surface of a substrate; spin depositing a surface hydrophobizing agent or a solvent onto an edge portion of the substrate to thereby remove the alkoxysilane composition from that area; and then curing the alkoxysilane composition to form a nanoporous dielectric silica coating. In another embodiment, an alkoxysilane composition layer is deposited onto a surface of a substrate. Then a solvent for the alkoxysilane substantially removes a portion of the alkoxysilane layer on the edge portion of the surface. This results in a transfer or cascading of a quantity of the alkoxysilane from a region adjacent to the edge portion to form a relatively thinner layer of the alkoxysilane onto the edge portion of the substrate surface. Then the relatively thinner alkoxysilane layer is removed prior to curing the alkoxysilane.

Abstract: A method for fabricating a passivation layer. An isolation layer is formed on a metal layer over the substrate. The isolation layer on the metal layer is removed by chemical-mechanical polishing and dry etching. The planarization of the metal layer thus is obtained. A passivation layer having a certain structure and a thickness combination of different layers is formed over the substrate. The reflection rate of the metal layer is significantly enhanced.

Abstract: The dimensional precision and accuracy of sub-micron-sized, in-laid metallization patterns, e.g., of electroplated copper or copper alloy, formed in the surface of a dielectric layer are significantly improved by utilizing a layer of a sputter-resistant mask material formed of a high atomic mass metallic element or compound thereof during reactive ion etching of the dielectric layer by a fluorine-containing plasma for forming sub-micron-dimensioned recesses therein. After filling of the recesses, planarization, as by CMP, is conducted wherein excess thickness of the metal layer is removed, together with underlying portions of the sputter-resistant mask layer.

Abstract: The reliability of in-laid metallization patterns, e.g., of copper or a copper-based alloy is significantly enhanced by voidlessly filling recesses formed in the dielectric layer surface by an electroplating process. Embodiments of the present invention include preventing "pinching-off" of the recess opening due to formation of overhanging nucleation/seed layer deposits at the corners of the opening as a result of locally increased rates of deposition. Embodiments of the present invention also include providing a dual-layered dielectric layer comprising dielectric materials having different lateral etching rates when subjected to a preselected etching process, for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, which tapered width profile effectively prevents formation of overhanging deposits, which overhanging deposits can result in occlusion and void formation during electroplating to fill the recesses.

Abstract: A method for fabricating a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a planarizable layer. The planarizable layer has a lower residual portion of the planarizable layer and an upper removable portion of the planarizable layer, where one of the lower residual portion of the planarizable layer and the upper removable portion of the planarizable layer has a colorant incorporated therein. The colorant is positioned at a location which assists in monitoring and controlling an endpoint of a chemical mechanical polish (CMP) planarizing method employed in planarizing the planarizable layer. There is then planarized through the chemical mechanical polish (CMP) planarizing method the planarizable layer while employing the colorant concentration to determine the endpoint of the chemical mechanical polish (CMP) planarizing method.

Abstract: In-laid metallization patterns, e.g., of copper or copper alloy, are formed in the surface of a dielectric layer with significantly improved reliability by voidlessly filling recesses formed in the dielectric layer surface by electroplating. Embodiments include preventing "pinching-off" of the recess opening due overhanging nucleation/seed layer deposits at the corners of the opening as a result of localized increased rates of deposition. Embodiments also include providing a dual-layered dielectric layer comprising different dielectric materials and performing a first, isotropic etching process of the upper (sacrificial) lamina of the dielectric layer for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, followed by a second, anisotropic etching process for extending the recess at a substantially constant width for a predetermined depth into the lower lamina of the dielectric layer.

Abstract: The reliability of in-laid metallization patterns, e.g., of copper or copper alloy, is significantly enhanced by voidlessly filling recesses in a substrate by an electroplating process, wherein "pinching-off" of the recess opening due to earlier formation of overhanging nucleation/seed layer deposits at the corners of the opening as a result of increased rates of deposition thereat is prevented. Embodiments include selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface by means of a directed beam etching or ablation process while rotating the substrate, which tapered width profile effectively prevents formation of overhanging deposits thereat which can result in occlusion and void formation during filling of the recesses by electroplating.

Abstract: A method of manufacturing a bonding substrate is disclosed. An oxide film is formed on at least one of two semiconductor substrates, and the two substrates are brought into close contact with each other via the oxide film. The substrates are heat-treated in an oxidizing atmosphere in order to firmly join the substrates together. Subsequently, the peripheral portion of a device-fabricating substrate is ground to a predetermined thickness, and an unjoined portion at the periphery of the device-fabricating substrate is completely removed through etching. The device-fabricating substrate is then ground and/or polished in order to reduce the thickness of the device-fabricating substrate to a desired thickness. The step of grinding the peripheral portion of the device-fabricating substrate to a predetermined thickness is performed by relative and radial movement of a grinding stone from the peripheral portion of the substrate toward the center thereof.

Abstract: The invention is a process for reducing roughness of a surface of a superconductor material (23) having an undesirable surface roughness (30 and 32) and a trilayer superconductor integrated circuit (100). The process for reducing roughness of a surface of superconductor material having an undesirable surface roughness includes coating the surface with an oxide layer (40) to fill the undesirable surface roughness and to produce an exposed oxide surface (42) with a roughness less than the surface roughness; and etching the exposed oxide surface to remove a thickness of the oxide layer followed by removing at least a portion of the oxide layer filling the undesirable surface roughness and a portion of the surface of the superconductor material to produce an exposed etched surface (44) comprised of at least the superconductor material which has a surface roughness less than the undesirable surface roughness.

Abstract: A method of processing an assembly to prepare the assembly for etch patterning, the assembly including a row or bar mounted on a substrate, the row or bar bordered by a recess, the method including placing the assembly within a frame; applying a contiguous adhesive film across said assembly and said frame; depositing a fluid in said frame, said fluid forming in said recess; and removing said contiguous adhesive film.

Abstract: A process for forming a via in a semiconductor device using a self-aligned tungsten pillar to connect upper and lower conductive layers separated by a dielectric. A Ti/TiN layer is formed on an underlying substrate layer, an aluminum-copper layer is formed on the Ti/TiN layer, a TiN layer is formed on the aluminum-copper layer and a tungsten layer is formed on the TiN layer. In one continuous etching step, the stack of tungsten, TiN, Al--Cu, Ti/TiN is then patterned and etched. A first dielectric is deposited overlying the exposed regions of the substrate layer and the conductive stack. The wafer is then planarized to expose the top of the tungsten layer. The wafer is again patterned and the tungsten is etched using the titanium nitride as an etch stop. A second dielectric is deposited to fill the resulting gaps and CMP processes are used to planarize the wafer and expose the top of the tungsten pillar.

Abstract: In a CMP process for flatting a surface of a film on a semiconductor wafer, ionized water is used as rinsing liquid in the post-polishing step performed after the main CMP polishing step. With ionized water as rinsing liquid, abrasive particles adhered to the film surface during the main polishing step are removed.

Abstract: An organic electroluminescent device and a method for fabricating the same are disclosed, the method including the steps of (1) forming a plurality of first electrode stripes on a transparent substrate at fixed intervals, (2) forming an array of partition walls made of an electrically insulating material on the first electrode elements; having a trapezoidal structure with the lower side wider than the upper side, (3) forming an organic eletroluminescent multilayer, the second electrode, and the first protection layer in succession on the entire surface including on top of the partition walls, (4) removing upper portions of films, unequivocally including the second electrode layer on top of the partition walls, whereby electrically isolating any two adjacent pixels, and (5) forming the second protection layer on top of the etched-out surface, whereby simplifying fabrication processes, improving product yield and reducing product cost.

Abstract: A method of planarizing comprising providing a substrate having an uneven surface topography, forming a layer on the substrate, wherein the layer has a graded resistance to polishing, and polishing the layer.