Planarizing A Nonplanar Surface Patents (Class 216/38)
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Patent number: 7510641Abstract: A continuous process of forming a highly smooth surface on a metallic tape by passing a metallic tape having an initial roughness through an acid bath contained within a polishing section of an electropolishing unit over a pre-selected period of time, and, passing a mean surface current density of at least 0.18 amperes per square centimeter through the metallic tape during the period of time the metallic tape is in the acid bath whereby the roughness of the metallic tape is reduced. Such a highly smooth metallic tape can serve as a base substrate in subsequent formation of a superconductive coated conductor.Type: GrantFiled: July 21, 2003Date of Patent: March 31, 2009Assignee: Los Alamos National Security, LLCInventors: Sascha Kreiskott, Vladimir Matias, Paul N. Arendt, Stephen R. Foltyn, Lawrence E. Bronisz
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Patent number: 7494597Abstract: Disclosed are a method and apparatus for etching disk-shaped members, especially a method and apparatus for etching semiconductor wafers. In a method wherein wafers (30) are rotated and etched in an etching chamber (12) which is filled with an etching solution, a non-rotating cell plate (26) is disposed between two rotating wafers (30). In an etching apparatus wherein multiple wafers (30) are supported and rotated by a rod (16), the cell plate (26) is disposed between each two wafers (30). The cell plate (26) has a surface area roughly equivalent to that of the wafer (30).Type: GrantFiled: July 29, 2004Date of Patent: February 24, 2009Assignee: Sumco Techxiv CorporationInventors: Tadamitsu Miyazaki, Kazuya Hirayama, Hisaya Fukunaga, Hiroyasu Futamura
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Publication number: 20090045164Abstract: During processing of a semiconductor wafer bearing a structure including a low-k dielectric layer, a cap layer and the metal-diffusion barrier layer, a chemical mechanical polishing method applied to remove the metal-diffusion barrier material involves two phases. In the second phase of the barrier-CMP method, when the polishing interface is close to the low-k dielectric material, the polishing conditions are changed so as to be highly selective, producing a negligible removal rate of the low-k dielectric material. The polishing conditions can be changed in a number of ways including: changing parameters of the composition of the barrier slurry composition, and mixing an additive into the barrier slurry.Type: ApplicationFiled: February 3, 2006Publication date: February 19, 2009Applicant: Freescale Semiconductor, Inc.Inventors: Janos Farkas, Philippe Monnoyer, Brad Smith, Mark Zaleski
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Publication number: 20090047731Abstract: A cellular electrophysiological measurement device includes a thin plate and a frame. The thin plate has a first surface with a depression and a second surface with a through-hole. The frame is in contact with an outer periphery on the second surface of thin plate. The thin plate has a laminated structure of at least two layers including a first material layer on the first surface and a second material layer on the second surface. The frame is formed of a third material layer. The structure allows the cellular electrophysiological measurement device to be not so vulnerable to breakage of thin plate and other damages, thereby having high production yield.Type: ApplicationFiled: May 31, 2006Publication date: February 19, 2009Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Masaya Nakatani, Takashi Yoshida, Masatoshi Kojima
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Publication number: 20090039056Abstract: Provided is a planarizing method in which a planarization with high flatness can be performed, without being restricted by the distribution of film thickness in the applied resist film. The planarizing method comprises the steps of: forming a resist film on a film to be planarized formed on a substrate; exposing the resist film with the amounts of exposure light in respective sections into which an area in which the film to be planarized is formed is divided, the amounts of exposure light being determined so as to realize film thicknesses to be left for planarization of the resist film in the respective sections; developing the exposed resist film, to form a resist film pattern with a controlled distribution of film thickness; and etching the resist film pattern and the film to be planarized, until eliminating the thickness amounts to be eliminated of the film to be planarized.Type: ApplicationFiled: August 10, 2007Publication date: February 12, 2009Applicant: TDK CORPORATIONInventors: Akifumi KAMIJIMA, Hideyuki YATSU, Hitoshi HATATE
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Publication number: 20080314870Abstract: This invention provides a substrate processing method including a step of covering in advance the surface of a substrate W with water (28), a step of holding the substrate W generally horizontally with the surface facing upward and rotating it in a horizontal plane (10), and a step of blowing to the substrate top surface drying gas flow that is thin in area in comparison with the substrate W surface (30, 40), in which the water is removed from the substrate top surface by the rotation in the horizontal plane while blowing the drying gas flow, a substrate processing apparatus for implementing the above method, and a control program for use with the above method and apparatus. With this invention, it is possible to dry a cleaned substrate without locally leaving water droplets.Type: ApplicationFiled: January 30, 2006Publication date: December 25, 2008Inventors: Yuki Inoue, Akira Fukunaga, Takahiro Ogawa
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Patent number: 7468322Abstract: A method is provided for removing conductive material from a metal layer deposited on a wafer having die level thickness variations on its surface. The method includes contacting the metal layer with a composition capable of planarizing die level thickness variations while using a current having a current density within a range of between about 5 mA/cm2 and about 40 mA/cm2, applying a first current to the wafer having a current density within a range of between about 5 mA/cm2 and about 20 mA/cm2 to remove a first portion of the metal layer to thereby planarize the wafer surface, and administering a second current to the wafer having a current density within a range of between about 20 mA/cm2 and about 40 mA/cm2 to remove a second portion of the metal layer and to leave a third portion of the metal layer on the wafer having a predetermined thickness.Type: GrantFiled: April 26, 2005Date of Patent: December 23, 2008Assignee: Novellus Systems, Inc.Inventor: Vishwas Hardikar
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Publication number: 20080277378Abstract: Method for polishing copper by chemical-mechanical planarization. The method of the present invention includes dissolving MoO3 in an oxidizing agent and deionized water to form a first slurry; filtering the first slurry; adding supplemental ceramic/metal oxide nano-particles to the first slurry after filtering, forming an aqueous slurry; introducing the aqueous slurry between the copper and a polishing pad; and, polishing the copper by moving the polishing pad and the copper relative to one another.Type: ApplicationFiled: June 27, 2008Publication date: November 13, 2008Applicant: Climax Engineered Materials, LLCInventors: S.V. Babu, Sharath Hegde, Sunil Chandra Jha, Udaya B. Patri, Youngki Hong
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Publication number: 20080264901Abstract: Disclosed is a chemical mechanical polishing planarization method for copper surface, including the following steps: depositing a dielectric layer on the copper surface, and polishing the copper surface having the dielectric layer thereon. The method for planarizing a copper surface by chemical mechanical polishing process according to the present invention can achieve the planarization of the surfaces of both the copper and the dielectric layer, so as to avoid the occurrence of the dishing phenomenon.Type: ApplicationFiled: April 15, 2008Publication date: October 30, 2008Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Xuan Zhu, Mengfeng Tsai
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Publication number: 20080233330Abstract: A liquid material containing a silicone material or organosilica is applied to a roughly polished surface of a polycrystalline silicon substrate to form a smooth thin film covering steps and grain boundary portions; thereafter, the thin film is subjected to a heat treatment at an appropriate temperature to allow the organic components thereof to evaporate off, thereby forming an SiO2 film; and the resulting SiO2 film is then subjected to precision polishing, such as a CMP process, to impart the substrate with a high planarity. This method makes it possible to give a planar and smooth surface with no effect reflecting differences in crystal orientation among polycrystalline grains or the presence of grain boundaries. The Si substrate for magnetic recording media thus obtained exhibits a sufficient impact resistance and an excellent surface planarity.Type: ApplicationFiled: March 18, 2008Publication date: September 25, 2008Applicant: Shin-Etsu Chemical Co., Ltd.Inventor: Ken Ohashi
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Publication number: 20080217291Abstract: A substrate mounting stage that prevents poor attraction of substrates so as to improve the operating rate of a substrate processing apparatus. The substrate mounting stage is disposed in the substrate processing apparatus and has a substrate mounting surface on which a substrate is mounted. The arithmetic average roughness (Ra) of the substrate mounting surface is not less than a first predetermined value, and the initial wear height (Rpk) of the substrate mounting surface is not more than a second predetermined value.Type: ApplicationFiled: February 11, 2008Publication date: September 11, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Masakazu HIGUMA, Yasuharu Sasaki, Tadashi Aoto, Eiichiro Kikuchi
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Patent number: 7413988Abstract: A method for planarizing a semiconductor substrate is provided. The method initiates with tracking a signal corresponding to a thickness of a conductive film disposed on the semiconductor substrate. Then, a second derivative is calculated from data representing the tracked signal. Next, the onset of planarization is identified based upon a change in the second derivative. A CMP system configured to identify a transition between stages of the CMP operation is also provided.Type: GrantFiled: June 27, 2003Date of Patent: August 19, 2008Assignee: Lam Research CorporationInventors: Ramesh Gopalan, Sridharan Srivatsan, Katgenhalli Y. Ramanujam, Tom Ni, Conan Chiang
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Publication number: 20080176403Abstract: In a method of chemically and mechanically polishing a layer, a substrate on which the layer having stepped portions is formed is prepared. The layer is primarily chemically and mechanically polished at a temperature of about 30° C. to about 80° C. to remove the stepped portions of the layer. The layer is secondarily chemically and mechanically polished without the stepped portions at a temperature of about 5° C. to about 25° C. to form a flat layer having a desired thickness. Thus, the stepped portions may be rapidly removed in an initial period so that the method may have an improved throughput.Type: ApplicationFiled: November 8, 2007Publication date: July 24, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-Yong Kim, Chang-Ki Hong, Bo-Un Yoon, Byoung-Ho Kwon
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Patent number: 7402529Abstract: A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.Type: GrantFiled: May 26, 2005Date of Patent: July 22, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Jaynal A. Molla, John D'Urso, Kelly Kyler, Bradley N. Engel, Gregory W. Grynkewich, Nicholas D. Rizzo
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Publication number: 20080166525Abstract: A method is disclosed for bonding two elements by means of a bonding agent such as a glue layer, wherein the bonding agent is removable, and wherein between the bonding agent and at least one element, a sacrificial layer is applied which is selectively removable with respect to that element. According to embodiments, the elements comprise a die or a substrate bonded to a carrier wafer. The nature and type of the die or substrate and of the carrier can vary within the scope of embodiments of the invention. Also disclosed is a composite substrate obtainable by methods of the invention.Type: ApplicationFiled: December 21, 2007Publication date: July 10, 2008Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)Inventors: Bart Swinnen, Eric Beyne
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Publication number: 20080160777Abstract: A cleaning method for a processing chamber of semiconductor substrates is provided which is capable of rapidly removing deposits and accretions generated inside the chamber of processing semiconductor substrates of a high-dielectric-constant oxide and of preventing any reaction product depositing. The cleaning method for a processing chamber of semiconductor substrates includes activating a mixed gases which contains a halogenated gas and either an oxygen-contained gas or an oxidizing gas during a plasma treatment or a heating treatment in order to etch off the deposits or accretions.Type: ApplicationFiled: December 22, 2005Publication date: July 3, 2008Inventors: Kouichi Ono, Tomohiro Kitagawa, Minoru Inoue, Masanori Oosawa
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Publication number: 20080152936Abstract: The present invention relates to a method for providing a high density relief structure in a recording stack (10) of a master substrate (12), particularly a master substrate (12) for making a stamper for the mass-fabrication of optical discs or a master substrate for creating a stamp for micro contact printing, the method comprising the following steps: —providing a recording stack (10) comprising a dielectric layer (14) and means (16, 18; 20) for supporting heat induced phase transitions within the dielectric layer (14); causing a heat induced phase transition in regions (22) of the dielectric layer (14) where pits (24) are to be formed by applying laser pulses; and removing the regions (22) of the dielectric layer (14), which have experienced a phase transition, by an etching process; or removing the regions (26) of the dielectric layer (14), which have not experienced a phase transition, by an etching process.Type: ApplicationFiled: January 2, 2006Publication date: June 26, 2008Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.Inventors: Erwin Rinaldo Meinders, Hinke Sijvert Petronella Bouwmans, Julien Jean Xavier De Loynes De Fumichon, Patrick Godefridus Jacobus Maria Peeters
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Publication number: 20080149591Abstract: A composition and associated method for the chemical mechanical planarization (CMP) of tungsten-containing substrates on semiconductor wafers are described. The composition contains an anionic fluorosurfactant, a per-type oxidizer (e.g., hydrogen peroxide), and iron. The composition and associated method are effective in affording greatly reduced levels of tungsten etching during tungsten CMP. In some embodiments, certain aspartic acid compounds are also present in the composition and are effective in affording even lower levels of tungsten etching during tungsten CMP.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Inventors: Junaid Ahmed Siddiqui, Rachel Dianne McConnell, Ann Marie Meyers
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Patent number: 7383629Abstract: A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided, as is a method of making the substrate.Type: GrantFiled: November 19, 2004Date of Patent: June 10, 2008Assignee: Endicott Interconnect Technologies, Inc.Inventors: John M. Lauffer, Voya R. Markovich, Michael Wozniak
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Patent number: 7377836Abstract: Methods of refining using a plurality of refining elements are discussed. A refining apparatus having refining elements that can be smaller than the workpiece being refined are disclosed. New refining methods, refining apparatus, and refining elements disclosed. Methods of refining using frictional refining, chemical refining, tribochemical refining, and electrochemical refining and combinations thereof are disclosed. A refining apparatus having magnetically responsive refining elements that can be smaller than the workpiece being refined are disclosed. The refining apparatus can supply a parallel refining motion to the refining element(s) for example through magnetic coupling forces. The refining apparatus can supply multiple different parallel refining motions to multiple different refining elements for example solely through magnetic coupling forces to improve refining quality and versatility. A refining chamber can be used. New methods of control are refining disclosed.Type: GrantFiled: April 12, 2004Date of Patent: May 27, 2008Assignee: Beaver Creek Concepts IncInventor: Charles J. Molnar
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Patent number: 7378029Abstract: A method for manufacturing a magnetic recording medium is provided, by which a magnetic recording medium having a recording layer formed in a concavo-convex pattern, a sufficiently flat surface, and high recording and reproducing precision is efficiently manufactured. In a non-magnetic material filling step, a non-magnetic material is deposited over a recording layer formed in a predetermined concavo-convex pattern over a substrate to fill concave portions of the concavo-convex pattern with the non-magnetic material. In a flattening step, an excess part of the non-magnetic material above the recording layer is removed by dry etching, to flatten surfaces of the recording layer and the non-magnetic material. Processing conditions are set so as to substantially equalize an etching rate of the non-magnetic material with an etching rate of the recording layer with respect to the dry etching in the flattening step.Type: GrantFiled: February 17, 2005Date of Patent: May 27, 2008Assignee: TDK CorporationInventors: Kazuhiro Hattori, Shuichi Okawa, Takahiro Suwa, Mikiharu Hibi
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Publication number: 20080099429Abstract: Methods for repairing patterned structure of electronic devices. A first substrate with a patterned structure thereon is provided, wherein the patterned structure includes at least one defect. The defect corresponds to a defect region while the patterned structure corresponds to a main region. A first surface treatment is performed on the defect region such that the surface characteristics on the defect region are different from those on the main region. The defect region is repaired by inkjet printing. A second surface treatment is performed on the defect region such that the surface characteristics on the defect region are the same as those on the main region.Type: ApplicationFiled: July 25, 2007Publication date: May 1, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chao-Kai Cheng, Chieh-Yi Huang, Wan-Wen Chiu, Chun-Hung Lin, Chia-Chang Chang
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Publication number: 20080093337Abstract: The invention is a method of bonding a first fluid conduit (14) to one or more other fluid conduits (12) or elements such as an electrode (92) or heating element. The method comprises positioning a first fluid conduit (14) substantially in contact with the other fluid conduits or elements (12) wherein a bond region (16) is created. The bond region is wetted with a liquefied thermoplastic polymer (34) which is then subsequently cooled forming a substantially fluid tight bond between the first fluid conduit (14) and the other fluid conduits or elements (14).Type: ApplicationFiled: July 16, 2004Publication date: April 24, 2008Applicant: WATERS INVESTMENTS LIMITEDInventors: Theodore Dourdeville, Dennis DellaRovere
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Patent number: 7348275Abstract: A processing method for a semiconductor wafer which is generally circular, and which has on the face thereof an annular surplus region present in an outer peripheral edge portion of the face, and a circular device region surrounded by the surplus region, the device region having many rectangular regions defined by streets arranged in a lattice pattern, each of the rectangular regions having a semiconductor device disposed therein. The processing method includes a back grinding step of grinding a region in the back of the wafer corresponding to the device region to form a circular concavity in the back of the wafer corresponding to the device region.Type: GrantFiled: July 6, 2006Date of Patent: March 25, 2008Assignee: Disco CorporationInventor: Kazuma Sekiya
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Patent number: 7342638Abstract: According to an aspect of the invention, to completely planarize the outermost surface of a laminated structure by appropriately performing a planarizing process, such as a CMP process, in an electro-optical device, such as a liquid crystal device, an electro-optical device includes TFTs that constitute driving circuits to drive data lines and scanning lines that are arranged in a peripheral region around an image display region, and an interlayer insulating film formed on the data lines, scanning lines, TFTs, and the driving circuits. In the interlayer insulating film formed in the peripheral region, after an etching process is performed on at least portions corresponding to regions in which the driving circuits are formed, a CMP process is performed on the peripheral region and the image display region.Type: GrantFiled: May 17, 2004Date of Patent: March 11, 2008Assignee: Seiko Epson CorporationInventor: Yoshikazu Eguchi
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Patent number: 7338610Abstract: A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is removed or reduced to prevent any bubbles included in the chemical solution from adhering to the electrode. Thus, the chemical solution can etch the dielectric layers without being blocked by any bubbles included in a chemical solution.Type: GrantFiled: January 23, 2004Date of Patent: March 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Jun Lee, Byoung-Moon Yoon, In-Seak Hwang, Yong-Sun Ko
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Publication number: 20080048687Abstract: A probe, a method of manufacturing the probe and a probe card having the probe are disclosed. The probe includes a first connecting member, a body and a tip. Specially, the body integrally includes a bump and a beam. The body is fixed to an electric component by the first connecting member. In addition, the probe card may include a printed circuit board and the electric component as well as the above probe. Here, the probe is independently formed. The probe is then fixed to the electric component so that damage to the electric component may be effectively prevented.Type: ApplicationFiled: July 30, 2007Publication date: February 28, 2008Inventor: Moon-Hyuck Jung
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Patent number: 7335600Abstract: A method for removing photoresist is described. A substrate having a photoresist to be removed thereon is provided, and then an ashing process is performed to remove most of the photoresist. The substrate is then subjected to a surface treatment that provides sufficient energy for the extra electrons caused by the ashing process to escape from the substrate, and the remaining photoresist and polymer are stripped with stripping solvents after the surface treatment.Type: GrantFiled: December 15, 2004Date of Patent: February 26, 2008Assignee: United Microelectronics Corp.Inventors: Wen-Sheng Chien, Yen-Wu Hsieh
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Patent number: 7307013Abstract: A method for etching to form a planarized surface is disclosed. Spaced-apart features are formed of a first material, the first material either conductive or insulating. A second material is deposited over and between the first material. The second material is either insulating or conductive, opposite the conductivity of the first material. The second material is preferably self-planarizing during deposition. An unpatterned etch is performed to etch the second material and expose the top of the buried features of the first material. The etch is preferably a two-stage etch: The first stage is selective to the second material. When the second material is exposed, the etch chemistry is changed such that the etch is nonselective, etching the first material and the second material at substantially the same rate until the buried features are exposed across the wafer, producing a substantially planar surface.Type: GrantFiled: June 30, 2004Date of Patent: December 11, 2007Assignee: Sandisk 3D LLCInventors: Usha Raghuram, Michael W. Konevecki, Samuel V. Dunton
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Patent number: 7304263Abstract: The footprint of a reactive atom plasma processing tool can be modified using an aperture device. A flow of reactive gas can be injected into the center of an annular plasma. An aperture can be positioned relative to the plasma such that the effective footprint of the plasma can be changed without adjusting the gas flows or swapping out the tool. Once the aperture and tool are in position relative to a workpiece, reactive atom plasma processing can be used to modify the surface of the workpiece, such as to etch, smooth, polish, clean, and/or deposit material onto the workpiece. If necessary, a coolant can be circulated about the aperture. Multiple apertures can also be used to provide a variety of footprint sizes and/or shapes. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures, and the claims.Type: GrantFiled: August 5, 2004Date of Patent: December 4, 2007Assignee: RAPT Industries, Inc.Inventors: Andrew Chang, Jeffrey W. Carr, Jude Kelley, Peter S. Fiske
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Patent number: 7300595Abstract: A method for filling concave portions of a concavo-convex pattern by which the concave portions of the concavo-convex pattern can be filled to flatten the surface with reliability, and a method for manufacturing a magnetic recording medium by which a magnetic recording medium having a magnetic recording layer of concavo-convex pattern with a sufficiently flat surface can be manufactured efficiently. A filler for filling the concave portions is deposited over the surface of an object to be processed, the object being provided with a concavo-convex pattern. A cladding is further deposited over the filler. Then, an excess part of the filler and the cladding above the surface of the object are removed for flattening, by using a dry etching method having a lower etching rate to the cladding than to the filler.Type: GrantFiled: December 20, 2004Date of Patent: November 27, 2007Assignee: TDK CorporationInventors: Takahiro Suwa, Kazuhiro Hattori, Shuichi Okawa, Mikiharu Hibi
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Patent number: 7288206Abstract: A high-purity alkali etching solution for silicon wafers results in silicon wafers with extremely low metal impurity contamination, and excellent surface flatness. The alkali etching solution contains sodium hydroxide containing 1 ppb or less of the elements Cu, Ni, Mg, and Cr, 5 ppb or less of the elements Pb and Fe, 10 ppb or less of the elements Al, Ca, and Zn, and 1 ppm or less of chloride, sulfate, phosphate, and nitrogen compounds other than nitrate and nitrite, and containing 0.01 to 10 wt % of nitrate and/or nitrite.Type: GrantFiled: December 22, 2004Date of Patent: October 30, 2007Assignee: Siltronic AGInventor: Shigeki Nishimura
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Patent number: 7281317Abstract: A manufacturing method of a flying magnetic head slider includes a step of providing a substrate with a plurality of inductive write head elements formed thereon, each head element having a pair of magnetic poles facing to each other via a magnetic gap, and with a protection layer covering the plurality of inductive write head elements, a step of cutting the substrate to separate into a plurality of bar members, each of the bar members having aligned inductive write head elements, a step of processing the protection layer of each bar member so that a distance from an end edge of the pair of magnetic poles to an edge of a bottom surface of the bar member becomes in a range of 1 to 15 ?m, a step of lapping each bottom surface of the bar member, and cutting each bar member to separate into a plurality of individual magnetic head sliders.Type: GrantFiled: July 8, 2004Date of Patent: October 16, 2007Assignee: SAE Magnetics (H.K.) Ltd.Inventors: Morihiro Ohno, Osamu Fukuroi, Ryuji Fujii
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Patent number: 7279115Abstract: A method is disclosed for preparing a substrate and epilayer for reducing stacking fault nucleation and reducing forward voltage (Vf) drift in silicon carbide-based bipolar devices. The method includes the steps of etching the surface of a silicon carbide substrate with a nonselective etch to remove both surface and subsurface damage, thereafter etching the same surface with a selective etch to thereby develop etch-generated structures from at least any basal plane dislocation reaching the substrate surface that will thereafter tend to either terminate or propagate as threading defects during subsequent epilayer growth on the substrate surface, and thereafter growing a first epitaxial layer of silicon carbide on the twice-etched surface.Type: GrantFiled: March 27, 2006Date of Patent: October 9, 2007Assignee: Cree, Inc.Inventor: Joseph John Sumakeris
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Patent number: 7273563Abstract: A method for manufacturing a magnetic recording medium is provided, which can efficiently manufacture a magnetic recording medium that includes a recording layer formed in a concavo-convex pattern and has good recording and reproduction characteristics. The method includes: a non-magnetic material filling step of depositing a non-magnetic material over a recording layer formed in a predetermined concavo-convex pattern over a substrate so as to fill a concave portion of the concavo-convex pattern with the non-magnetic material; and a flattening step of removing the excess part of the non-magnetic material above the recording layer by dry etching so as to flatten the surfaces of the non-magnetic material and the recording layer. The flattening step includes a former flattening step and a latter flattening step for finishing.Type: GrantFiled: February 3, 2005Date of Patent: September 25, 2007Assignee: TDK CorporationInventors: Kazuhiro Hattori, Shuichi Okawa, Takahiro Suwa, Mikiharu Hibi
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Patent number: 7264742Abstract: A method for removing at least a portion of a structure, such as a layer, film, or deposit, including ruthenium metal and/or ruthenium dioxide includes contacting the structure with a material including ceric ammonium nitrate. A material for removing ruthenium metal and amorphous ruthenium dioxide includes ceric ammonium nitrate and may be in the form of an aqueous solution including ceric ammonium nitrate and, optionally, other solid or liquid solutes providing desired properties. In one application, the method and material may be utilized to etch, shape, or pattern layers or films of ruthenium metal and/or ruthenium dioxide in the fabrication of semiconductor systems and their elements, components, and devices, such as wires, electrical contacts, word lines, bit lines, interconnects, vias, electrodes, capacitors, transistors, diodes, and memory devices.Type: GrantFiled: August 17, 2004Date of Patent: September 4, 2007Assignee: Micron Technology, Inc.Inventor: Donald L. Westmoreland
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Patent number: 7261829Abstract: A method for selective masking is described. In this case, a filling material is applied to a structure which, as a function of the aspect ratio of the structure, forms cavities when the aspect ratio is high. The filling layer is then removed as far as the cavities and, using an etching process, filling material is removed completely from the recesses in which the cavities are formed. In this way, areas are exposed selectively.Type: GrantFiled: January 8, 2003Date of Patent: August 28, 2007Assignee: Infineon Technologies AGInventors: Dirk Efferenn, Hans-Peter Moll
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Patent number: 7255803Abstract: The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma chamber that includes a plasma generating electrode powerable at different first and second frequencies, with the first frequency being lower than the second frequency. A substrate is positioned over the electrode. A plasma is generated over the substrate with the electrode from a first applied power at the first frequency and a second applied power at the second frequency. A ratio of the first applied power to the second applied power is from 0 to 0.25 or at least 6.0. Material is etched from the substrate with the plasma.Type: GrantFiled: July 19, 2006Date of Patent: August 14, 2007Assignee: Micron Technology, Inc.Inventors: Bradley J. Howard, Max F. Hineman
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Patent number: 7247251Abstract: A method for manufacturing a magnetic recording medium is provided, which can efficiently manufacture a magnetic recording medium that includes a recording layer formed in a concavo-convex pattern, has a sufficiently flat surface, and provides good recording and reproduction precision. The method includes: a non-magnetic material filling step of depositing a non-magnetic material over a recording layer formed in a predetermined concavo-convex pattern over a substrate, thereby filling a concave portion of the concavo-convex pattern with the non-magnetic material; and a flattening step of removing the excess part of the non-magnetic material above the recording layer by ion beam etching to flatten the surfaces of the non-magnetic layer and the recording layer.Type: GrantFiled: February 7, 2005Date of Patent: July 24, 2007Assignee: TDK CorporationInventors: Kazuhiro Hattori, Shuichi Okawa, Takahiro Suwa, Mikiharu Hibi
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Patent number: 7246424Abstract: A magnetic device having a magnetic feature, the magnetic feature including a magnetic portion comprising a magnetic material, a region of non-magnetic material adjacent to the magnetic portion, and a stop layer disposed above the region of non-magnetic material, defining a planar upper boundary of the magnetic portion.Type: GrantFiled: April 13, 2004Date of Patent: July 24, 2007Assignee: Seagate Technology LLCInventors: Picheng Huang, Paul E. Anderson, Laura C. Stearns, Song S. Xue
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Patent number: 7220164Abstract: An apparatus and method of using an in situ finishing information for finishing workpieces and semiconductor wafers are described. The method uses operative sensors such as friction sensors for detecting and improving control during finishing. The method can aid control of finishing while using in situ finishing information and cost of manufacture information. The method can aid control of finishing while using organic lubricants, lubricating films, and lubricating boundary layers in the operative finishing interface. The method can generally aid control of differential finishing such as when using differential lubricating films such as lubricating boundary layers. Control can generally aid improvement of differential finishing of workpieces such as semiconductor wafers. Planarization and localized finishing can be used with in situ finishing information such as differential lubricating boundary layer(s) for finishing.Type: GrantFiled: November 6, 2006Date of Patent: May 22, 2007Assignee: Beaver Creek Concepts IncInventor: Charles J. Molnar
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Patent number: 7204934Abstract: A method for processing recess etch operations in substrates is provided including forming a hard mask over the substrate and etching a trench in the substrate using the hard mask, and forming a dielectric layer over the hard mask and in the trench, where the dielectric layer lines the trench. A conductive material is then applied over the dielectric layer such that a blanket of the conductive material lies over the hard mask and fills the trench, and the conductive material is etched to substantially planarize the conductive material. The etching of the conductive material triggers an endpoint just before all of the conductive material is removed from over the dielectric layer that overlies the bard mask. The conductive material is recess etched to remove the conductive material over the dielectric layer that overlies the hard mask and removes at least part of the conductive material from within the trench.Type: GrantFiled: October 31, 2001Date of Patent: April 17, 2007Assignee: Lam Research CorporationInventors: Linda Braly, Vahid Vahedi, Erik Edelberg, Alan Miller
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Patent number: 7140094Abstract: Magnetic heads capable of recording and reading with high sensitivity and resolution are provided by minimizing the outflow of magnetic fluxes from a flux guide to magnetic shields while using a flux guide structure for an MR element. In the magnetic head, magnetic shields exposed on a surface opposite a magnetic recording medium (air bearing surface) and a flux guide exposed between the magnetic heads via a non-magnetic layer are provided, and magnetic fluxes are guided by the flux guide to a magnetoresistive (MR) element formed in a position not exposed on the air bearing surface. The height of the magnetic shields in direction perpendicular to the air bearing surface is less than the distance from the air bearing surface to the MR element.Type: GrantFiled: October 7, 2003Date of Patent: November 28, 2006Assignee: Hitachi, Ltd.Inventor: Hiroaki Nemoto
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Patent number: 7131890Abstract: An apparatus and method of using a in situ finishing information for finishing semiconductor wafers is described. The method uses operative sensors such as friction sensors for detecting and improving control during finishing. The method can aid control of finishing while using in situ finishing information and cost of manufacture information. The method can aid control of finishing while using organic lubricants, lubricating films, and lubricating boundary layers in the operative finishing interface. The method can generally aid control of differential finishing such as when using differential lubricating films such as lubricating boundary layers. Control can generally aid improvement of differential finishing of semiconductor wafers. Planarization and localized finishing can used with in situ finishing information such as differential lubricating boundary layer for finishing. Defects can generally be reduced using the in situ friction finishing information method.Type: GrantFiled: December 8, 2003Date of Patent: November 7, 2006Assignee: Beaver Creek Concepts, Inc.Inventor: Charles J Molnar
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Patent number: 7105452Abstract: The present invention provides a method of planarizing a substrate, the method including, forming, on the substrate, a patterned layer having a first shape associated therewith; and processing the patterned layer, with the first shape compensating for variations in the processing such that upon processing the patterned layer, the patterned layer comprises a substantially planar shape.Type: GrantFiled: August 13, 2004Date of Patent: September 12, 2006Assignee: Molecular Imprints, Inc.Inventor: Sidlgata V. Sreenivasan
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Patent number: 7101259Abstract: A polishing apparatus is used for chemical mechanical polishing a copper (Cu) layer formed on a substrate such as a semiconductor wafer and then cleaning the polished substrate. The polishing apparatus has a polishing section having a turntable with a polishing surface and a top ring for holding a substrate and pressing the substrate against the polishing surface to polish a surface having a semiconductor device thereon, and a cleaning section for cleaning the substrate which has been polished. The cleaning section has an electrolyzed water supply device for supplying electrolyzed water to the substrate to clean the polished surface of the substrate while supplying electrolyzed water to the substrate.Type: GrantFiled: October 28, 2003Date of Patent: September 5, 2006Assignees: Ebara Corporation, Kabushiki Kaisha ToshibaInventors: Norio Kimura, Mitsuhiko Shirakashi, Katsuhiko Tokushige, Masao Asami, Naoto Miyashita, Masako Kodera, Yoshitaka Matsui, Soichi Nadahara, Hiroshi Tomita
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Patent number: 7086141Abstract: A manufacturing method of an MR sensor including a step of stacking an anti-ferromagnetic layer made of an electrically conductive anti-ferromagnetic material, a step of stacking a pinned layer on the anti-ferromagnetic layer, a step of stacking a nonmagnetic spacer layer on the pinned layer, a step of exposing at least once a surface of the nonmagnetic spacer layer to an oxygen-contained atmosphere, a step of stacking a free layer on the nonmagnetic spacer layer, a magnetization direction of the free layer being free depending upon a magnetic filed applied thereto, and a step of providing the pinned layer a magnetization direction fixed by an exchange coupling between the anti-ferromagnetic layer and the pinned layer.Type: GrantFiled: June 20, 2002Date of Patent: August 8, 2006Assignee: TDK CorporationInventors: Yoshihiro Tsuchiya, Tetsuro Sasaki
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Patent number: 7081041Abstract: A method for forming a write head top pole using chemical mechanical polishing with a diamond-like-carbon (DLC) polishing stop layer is disclosed. The method for providing a top pole of a write head includes forming a P2 pole tip, depositing a P2 filling layer to a P2 target thickness, wherein the P2 filling layer around the P2 pole tip is filled to a P2 target thickness while the P2 filling layer creates a topography above the P2 pole tip, depositing a DLC polishing stop layer over the P2 target thickness filling layer, and chemically mechanically polishing (CMP) any topography above the stop layer-covered P2 target thickness filling layer to the stop layer using a selective slurry.Type: GrantFiled: February 28, 2005Date of Patent: July 25, 2006Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Hung-Chin Guthrie, Ming Jiang
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Patent number: 7052620Abstract: A polishing slurry for an aluminum-based metal includes an oxidizing agent having a standard electrode potential of 1.7 V or more, amino acid or amino acid compound, and bi- or higher than bi-valent aromatic carboxylic acid having a carbocycle or a heterocycle.Type: GrantFiled: March 5, 2003Date of Patent: May 30, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Yukiteru Matsui, Gaku Minamihaba
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Patent number: RE39413Abstract: The present invention is a semiconductor wafer that enhances polish-stop endpointing in chemical-mechanical planarization processes. The semiconductor wafer has a substrate with a device feature formed on the substrate, a stratum of low friction material positioned over the substrate, and an upper layer deposited on the low friction material stratum. The low friction stratum has a polish-stop surface positioned at a level substantially proximate to a desired endpoint of the chemical-mechanical planarization process. The upper layer, which is made from either a conductive material or an insulative material, has a higher polishing rate than that of the low friction stratum. In operation, the low friction stratum resists chemical-mechanical planarization with either hard or soft polishing pads to stop the planarization process at the desired endpoint.Type: GrantFiled: May 2, 2002Date of Patent: November 28, 2006Assignee: Micron Technology, Inc.Inventors: Guy F. Hudson, Renee Zahorik, Russell C. Zahorik