Abstract: There is provided a magnetic memory device which has a small switching current for a writing line and which has a small variation therein. A method for producing such a magnetic memory device includes: forming a magnetoresistive effect element; forming a first insulating film so as to cover the magnetoresistive effect element; forming a coating film so as to cover the first insulating film; exposing a top face of the magnetoresistive effect element; forming an upper writing line on the magnetoresistive effect element; exposing the first insulating film on a side portion of the magnetoresistive effect element by removing a part or all of the coating film; and forming a yoke structural member so as to cover at least a side portion of the upper writing line and so as to contact the exposed first insulating film on the side portion of the magnetoresistive effect element.

Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

Abstract: A method is disclosed for preparing a substrate and epilayer for reducing stacking fault nucleation and reducing forward voltage (Vf) drift in silicon carbide-based bipolar devices. The method includes the steps of etching the surface of a silicon carbide substrate with a nonselective etch to remove both surface and sub-surface damage, thereafter etching the same surface with a selective etch to thereby develop etch-generated structures from at least any basal plane dislocation reaching the substrate surface that will thereafter tend to either terminate or propagate as threading defects during subsequent epilayer growth on the substrate surface, and thereafter growing a first epitaxial layer of silicon carbide on the twice-etched surface.

Abstract: A method for reducing noise in a lapping guide. Selected portions of a Giant magnetoresistive device wafer are masked, thereby defining masked and unmasked regions of the wafer in which the unmasked regions include lapping guides. The wafer is bombarded with ions such that a Giant magnetoresistive effect of the unmasked regions is reduced.

Abstract: A fabrication method of a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is respectively applied on terminals of the conductive traces. Then, a non-solderable material is applied over the core layer as to cover the conductive traces except for the insulating material, and the non-solderable material is adapted to be surface-flush with the insulating material, allowing the insulating material to be exposed from the non-solderable material. Finally, the insulating material is removed from the core layer to expose the terminals of the conductive traces, wherein the exposed terminals are used as bond pads or bond fingers where solder balls, solder bumps or bonding wires can be bonded. This circuit board is cost-effectively fabricated by simplified processes, and beneficial in precisely exposing bond pads or bond fingers, thereby significantly improving yield of fabricated circuit boards.

Abstract: The magnetic head of the present invention, includes a second magnetic pole (P2 pole) that is fabricated upon a write gap layer that is deposited upon a flat surface. To achieve the flat surface, a P1 pole pedestal is formed upon the P1 pole layer with a sufficient thickness that the induction coil structure can be fabricated beneath the write gap layer. In the preferred embodiment, an etch stop layer is formed upon the P1 pole layer and an ion etching process is utilized to form the induction coil trenches in an etchable material that is deposited upon the etch stop layer. Following the fabrication of the induction coil structure a CMP process is conducted to obtain a polished flat surface upon which to deposit the write gap layer, and the P2 pole is then fabricated upon the flat write gap layer. The magnetic head of the present invention can be reliably fabricated with a more narrow P2 pole tip base width, such that data tracks written by the magnetic head are likewise narrower.

Abstract: A method for fabricating microelectronic spring structures is disclosed. In an initial step of the method, a layer of sacrificial material is formed over a substrate. Then, a contoured surface is developed in the sacrificial material, such as by molding the sacrificial material using a mold or stamp. The contoured surface provides a mold for at least one spring form, and preferably for an array of spring forms. If necessary, the sacrificial layer is then cured or hardened. A layer of spring material is deposited over the contoured surface of the sacrificial material, in a pattern to define at least one spring form, and preferably an array of spring forms. The sacrificial material is then at least partially removed from beneath the spring form to reveal at least one free-standing spring structure. A separate conducting tip is optionally attached to each resulting spring structure, and each structure is optionally plated or covered with an additional layer or layers of material, as desired.

Abstract: A method of adjusting the relative thickness of an electrode assembly (10) in a plasma processing system (6) capable of supporting a plasma (20, 120) in a reactor chamber (16). The electrode assembly is arranged in the reactor chamber and includes at least one electrode having a lower surface that may have defined by at least one sacrificial protective plate (100). The electrode has a nonuniform thickness resulting from a plasma processing operation performed in the reactor chamber. The method includes a step of forming a plasma (120) designed to selectively etch the at least one electrode at the lower surface, followed by a step of etching the electrode with the aid of the plasma to reduce the nonuniformity in thickness (T(X,Z)) of the at least one electrode. The thickness of the electrode may be measured in situ using an acoustic transducer (210) during the processing of workpieces as well as during the restorative plasma etching of the electrode.

Abstract: In a local dry etching method, position-thickness data of a semiconductor wafer is previously obtained by measuring the wafer surface, components of position-thickness data shorter than a predetermined spatial wavelength are cut off by filtering and nozzle-wafer relative speed for planarizing the surface is calculated using the filtered data.

Abstract: A method of making an etched structure in the fabrication of a MEMS device involves depositing a bulk layer, typically of polysilicon, prone to surface roughness. At least one layer of photo-insensitive spin-on planarizing material, such as silicate-based spin-on glass, is formed on the bulk layer to reduce surface roughness. This is patterned with a photoresist layer. A deep etch is then performed through the photoresist layer into the bulk layer. This technique results in much more precise etch structures.

Abstract: A semiconductor manufacturing method analyzes topography variations in three dimensions for each photolithographic level and determines critical dimension (CD) bias compensation as inputs to mask layout creation. Accurate predictions of topography variation for a specific mask design are made at the die level using known pattern density and CMP planarization length characteristics for a specific pattern. Exhaustive characterization of the photoresist response to de-focus and mask bias is determined by artificially expanding loss of CD through focus. Mask compensation to an expanded range of focus over all lines and spaces is maintained within the specification. 3D mask density data is obtained to determine the height component at each pixel location in the die. The resulting 3D OPC model is then utilized for mask creation.

Abstract: In the method, a cap wafer surface is lithographically etched at time of fabrication, so that a raised ridge onto which bonding material is placed is formed near a perimeter of a desired cavity region. This is done in order to reduce the bonding area between the cap wafer and electronic device wafers, so as to provide a better defined standoff. In another aspect of the method, the cap wager surface is lithographically etched to form recesses or trenches near the perimeter of a cavity region, each recess being filled with a sealing material, and polished if necessary to be flush with the cap wafer surface. Thereafter, the cap wafer surface is etched so that the filled recesses become the raised ridges which are used to bond a cap wafer to an electronic device wafer.

Abstract: The surface of a semiconductor device is polished by first supplying a polishing pad with a slurry that contains a solvent, abrasive grains, and an additive for making the viscosity of the slurry variable so that the top portion of the polishing pad is soaked with the slurry, then supplying the polishing pad with a viscosity modifier for increasing the viscosity of the slurry and hardening the top portion of the polishing pad soaked with the slurry, and finally polishing the surface of the semiconductor device with the slurry having its viscosity increased and the polishing pad having its top portion hardened.

Abstract: A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer includes use of a fixed-abrasive type polishing pad with a substantially abrasive-free slurry in which copper is removed at a rate that is substantially the same as or faster than a rate at which a material, such as tungsten, of the barrier layer is removed. The slurry is formulated so as to oxidize copper at substantially the same rate as or at a faster rate than a material of the barrier layer is oxidized. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry or the oxidation energy of the barrier layer material in the slurry may be greater than that of copper. Systems for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.

Abstract: An apparatus for supplying chemicals in a chemical mechanical polishing (CMP) process includes a plurality of chemical solution supply sources for supplying different chemical solutions in a pump-less manner by using a pressure applied at the chemical solution supply sources, each supply source having an associated feed line, re-circulating line, and means for measuring and controlling flow rates of the chemical solutions supplied through the feed lines. The chemical solutions are delivered via a plurality of delivery lines to a mixer, thereby providing a mixed chemical solution to a chemical injection part of a polishing apparatus. Each means for measuring and controlling flow rates is mounted in the feed lines.

Abstract: A method of processing the surface of a workpiece using an adaptive gas cluster ion beam is disclosed. The invention provides a method of reducing the surface roughness and/or improving the surface smoothing of a workpiece by etching at various etch rates. The workpiece is initially processed with a gas cluster ion beam having an initial etch rate and then the beam is adjusted so that the workpiece is processed with one or more lower etch rates. The advantages are minimum required processing time, minimum remaining roughness of the final surface, and minimum material removal in order to attain a desired level of smoothness.

Abstract: A method of using a finishing element and using organic lubricating films for finishing semiconductor wafers is described. The lubricants in the finishing element can be transferred to operative finishing interface and can form a self-assembling lubricating film. The organic lubricating film thickness can be controlled to improve finishing and reduce unwanted surface defects. Differential organic lubricating film methods are described to differentially finish semiconductor wafers. Planarization and localized finishing can be improved using differential lubricating boundary layer and organic lubricating film methods of finishing.

Abstract: A method of making a magnetic head, which has an air bearing surface (ABS) and a back gap (BG), comprising the steps of: forming a second pole tip of a second pole piece with a top surface and a bottom surface at an ABS site for said ABS; the top surface of the second pole tip having a write region located at the ABS site and a stitch region which is recessed in its entirety from the ABS site toward said back gap; depositing a protective sacrificial layer on the write region of the second pole tip; removing said sacrificial layer from only the stitch region of the second pole tip; and forming a second pole piece yoke of a second pole piece magnetically connected to the stitch region of the second pole tip.

Abstract: A process of removing excess holefill material from a surface of an electronic substrate in which the holefill residue is contacted with a swelling agent followed by planarizing of the surface in the presence of an agent no stronger than a liquid having a pH of about 6 to about 8.

Abstract: An ultrasonic bath (30) is arranged below a wafer processing bath (10). Wafers (40) are processed while ultrasonic waves are transmitted from the ultrasonic bath (30) to the wafer processing bath (10). The wafers (40) are processed while being entirely dipped into the wafer processing bath (10) and rotated by wafer rotating rods (53).

Abstract: An oxygen ion process, Chemical Reactive-Ion Surface Planarization (CRISP), has been developed which enables planarization of thin film surfaces at the atomic level. Narrow/broad band filters produced with vacuum deposited multilayered thin films are designed to selectively reflect/transmit light at specific wavelengths. The optical performance is limited by the ability to control the individual layer thickness, the “roughness” of the individual layer surfaces and the stoichiometry of the layers. The process described herein will enable reduction of surface roughness at the interfaces of multilayered thin films to produce atomically smooth surfaces. The application of this process will result in the production of notch filters of less than 0.3 nm full width at half maximum (FWHM) centered at the desired wavelength.

Abstract: Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

Abstract: A method for homogenizing the thickness of a uniform layer deposited on a layer of a material etched according to functional patterns, consisting of filling the empty areas with dummy patterns; a function, providing the thickness variation of the uniform layer for a given distribution of the functional and dummy patterns, being known; the method comprising:

Abstract: In advanced electrolytic polish (AEP) method, a metal wafer (10) acts as an anodic electrodes and another metal plate (65) is used as a cathodic electrode. A voltage differential is applied to the anode and cathode under a predetermined anodic dissolution current density. This causes a reaction that provides a planarized surface on the metal wafers. Additives are included in the electrolyte solution (55) which adsorb onto the wafer surface urging a higher removal rate at higher spots and a lower removal rate at lower spots. Also, in another embodiment of the present invention is a pulsed-electrolytic process (260) in which positive and negative potentials are applied to the anodic and cathodic electrodes alternately, further encouraging surface planarization. AEP can be used either as a first step followed by a mechanical polish or a second step between initial CMP polish and a third step mechanical polish.

Abstract: A process for fabricating micro-mirrors on a silicon substrate is disclosed, which can markedly improve the flatness of micro-mirrors, reduce the scattering of incident light, and increase S/N ratio. The fabrication process comprises the steps of: forming micro-planes along a certain direction on a silicon substrate to serve as mirrors; forming a SiO2 layer on the silicon substrate; and melting the SiO2 layer on the micro-planes by a heating process and then crystallizing SiO2 again to form micro-mirrors. Further, instead of coating the SiO2 layer, a metal layer can be used to form a eutectic structure with the silicon substrate. After the micro-mirrors are formed, a layer of Au can be coated thereon to increase the reflectance of the micro-mirrors.

Abstract: A method of manufacturing semiconductor devices using an improved planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer using a fixed flexible planar interface material contacting the deformable material.

Abstract: An apparatus for performing a global planarization of a surface of a deformable layer of a wafer on a production scale. The apparatus includes a chamber having a pressing surface and containing a rigid plate and a flexible pressing member or “puck” disposed between the rigid plate and the pressing surface. A wafer having a deformable outermost layer is placed on the flexible pressing member so the deformable layer of the wafer is directly opposite and substantially parallel to the pressing surface. Force is applied to the rigid plate which propagates through the flexible pressing member to press the deformable layer of the wafer against the pressing surface. Preferably, a bellows arrangement is used to ensure a uniformly applied force to the rigid plate. The flexible puck serves to provide a self adjusting mode of uniformly distributing the applied force to the wafer, ensuring the formation of a high quality planar surface.

Abstract: There is described prevention of an increase in the thickness of an oxide film of a silicon wafer, which would otherwise be caused by eruption of gas from a CVD oxide film of another wafer during the course of a high-temperature annealing operation. A semiconductor device, which has a silicon substrate and trench isolation structures for isolating a plurality of active regions from one another, is manufactured by the steps as follows. A first and a second dielectric films are formed on the silicon substrate of one of the conductivity types. The dielectric films are removed from the areas of the silicon substrate where the trench structures are to be formed. The trench structures are formed in the uncovered areas of the silicon substrate to a predetermined depth. An oxide film is deposited into the respective trench structures by means of CVD after the oxide film has been deposited on the interior surface of the respective trench structure.

Abstract: Methods and apparatus are provided for planarizing substrate surfaces with selective removal rates and low dishing. One aspect of the method provides for processing a substrate including providing a substrate to a polishing platen having polishing media disposed thereon, providing an abrasive free polishing composition comprising one or more surfactants to the substrate surface to modify the removal rates of the at least the first dielectric material and the second dielectric material, polishing the substrate surface, and removing the second material at a higher removal rate than the first material from a substrate surface. One aspect of the apparatus provides a system for processing substrates including a platen adapted for polishing the substrate with polishing media and a computer based controller configured to perform one aspect of the method.

Abstract: Disclosed is a coaxial type signal line that solves problems associated with signal interference and the connection of signal lines that are generated in a radio frequency (RF) electrical system. A method for manufacturing the coaxial type signal line includes the steps of forming a groove on a substrate, forming a first ground line on a surface of the groove and a plain surface of the substrate, forming a first dielectric layer including dielectric material on the first ground line formed on the surface of the groove, forming a signal line on the first dielectric layer the signal line for transmitting signals, forming a second dielectric layer including dielectric material on the signal line and the first dielectric layer, and forming a second ground line on the first ground line and the second dielectric layer.

Abstract: A polishing apparatus is used for chemical mechanical polishing a copper (Cu) layer formed on a substrate such as a semiconductor wafer and then cleaning the polished substrate. The polishing apparatus has a polishing section having a turntable with a polishing surface and a top ring for holding a substrate and pressing the substrate against the polishing surface to polish a surface having a semiconductor device thereon, and a cleaning section for cleaning the substrate which has been polished. The cleaning section has an electrolyzed water supply device for supplying electrolyzed water to the substrate to clean the polished surface of the substrate while supplying electrolyzed water to the substrate.

Abstract: An method and apparatus for forming wafers of varying thickness'. The apparatus includes a template. The template is formed of a main disk including a plurality of cavities extending into a first side thereof and a backing plate positioned on a side of the main disk opposite the first side. Holding disks are moistened and positioned within respective cavities for releasably securing a wafer in the cavity. When the template is releasably secured to and rotatable with a rotating head and positioned such that the first side faces a lapping and polishing surface, wafers received by the cavities are lapped and polished upon rotation of the rotating head. A plurality of shims are selectively received within respective cavities between a base of the cavity and the holding disk for adjusting a depth of the cavity thereby adjusting an amount of a wafer to be lapped and polished. The shims have varying thickness' and are color coated, each color being representative of a predetermined thickness for the shim.

Abstract: Reactive atom plasma processing can be used to shape, polish, planarize, and clean surfaces of difficult materials with minimal subsurface damage. The apparatus and methods use a plasma torch, such as a conventional ICP torch. The workpiece and plasma torch are moved with respect to each other, whether by translating and/or rotating the workpiece, the plasma, or both. The plasma discharge from the torch can be used to shape, planarize, polish, clean and/or deposit material on the surface of the workpiece, as well as to thin the workpiece. The processing may cause minimal or no damage to the workpiece underneath the surface, and may involve removing material from, and/or redistributing material on, the surface of the workpiece.

Abstract: A cleaning method for a semiconductor substrate including placing the semiconductor substrate into a cleaning chamber and injecting ozone gas (O3) into the cleaning chamber. This process operates to cleanse the semiconductor substrate without corrosion or etching of the semiconductor substrate; even when the substrate has metal layer made of tungsten.

Abstract: The invention includes methods of forming magnetoresistive devices. In one method, a construction is formed which includes a first magnetic layer, a non-magnetic layer over the first magnetic layer, and a second magnetic layer over the non-magnetic layer. A first pattern is extended through the second magnetic layer and to the non-magnetic layer with an etch selective for the material of the second magnetic layer relative to the material of the non-magnetic layer. A dielectric material is formed over the patterned second magnetic layer, and subsequently a second etch is utilized to extend a second pattern through the non-magnetic layer and at least partway into the first magnetic layer.

Abstract: A scanning probe microscope probe is formed by depositing probe material in a mold that has a cavity in a shape and of a size of the desired form of the scanning probe microscope probe that is being fabricated. In the preferred embodiment, the cavity is formed by lithographically defining, in the body of the mold, the shape and the size of the desired scanning probe microscope probe and etching the body of the mold to form the cavity. Prior to depositing the probe material in the cavity in the mold, the cavity is lined with a release layer which, upon activation after the probe has been formed, permits removal of the probe.

Abstract: A method for preventing deposition of abrasive particles included in a surfactant containing slurry along flow pathways in a chemical mechanical polishing (CMP) slurry delivery system including providing a CMP delivery system having one or more flow pathways for delivering a surfactant containing slurry to at least one polishing station the surfactant containing slurry including abrasive particles; providing at least a fluid contact portion of the one or more flow pathways including at least flow pathway feed lines with a dipole inactive material for contacting the surfactant containing slurry; and, controllably delivering the surfactant containing slurry along the flow pathway feed lines to the at least one polishing station to perform a CMP process.

Abstract: A layer of low k dielectric is formed on a substrate having a conducting electrode formed therein. A via hole is formed in the low k dielectric exposing the conducting electrode. A thin layer of amorphous silicon is deposited on the layer of low k dielectric and on the sidewalls and bottom of a via hole. A layer of resist is then formed and patterned with a trench pattern. A trench is etched in the layer of low k dielectric directly over the via hole using the patterned layer of resist. The patterned layer of resist is then stripped and the trench and via hole are filled with conducting material. The layer of amorphous silicon prevents amine radicals, NHx, which can be released from the low k dielectric, especially during the via hole etching, from interacting with the resist and forming resist scum resulting in via poisoning.

Abstract: Process for the formation of at least one concave relief (124, 145) in a substrate comprising forming at least one embossment of material subject to creep (100) on the substrate (120), —heating of the material subject to creep to a temperature sufficiently high to cause creep of the said material, and—etching of the substrate and the crept material to form relief in the substrate. According to the invention, the crept material is solidified in a state in which it has a concave relief.

Abstract: In integrated circuits produced by etching and damascene techniques, it is common for cracking to occur in dielectric material surrounding an interconnect metal layer integrated into the device, presumably as a result of the transfer of stresses from the interconnect metal layer to the surrounding dielectric material. The present invention addresses this problem by providing an interconnect metal layer that comprises rounded comers which are believed to reduce the stresses transferred to a surrounding dielectric layer.

Abstract: Improved methods, compositions and structures formed therefrom are provided that allow for reduction of roughness in layers (e.g., oxide layers) of a planarized wafer. In one such embodiment, improved methods, compositions and structures formed therefrom for reduction of roughness in layers (e.g., oxide layers) of a planarized wafer are used in conjunction with high modulus polyurethane pads. In one embodiment, improved methods, compositions and structures formed therefrom are provided that reduce rough interlayer dielectric (ILD) conditions for a wafer during CMP processing of such a wafer. Embodiments of a method for forming a microelectronic substrate include mixing a surfactant at least 100 parts per million (ppm) to slurries to form a polishing solution.

Abstract: A composition for removing side wall which includes an aqueous solution containing both nitric acid and at least one of carboxylic acids selected from the group consisting of polycarboxylic acid, aminocarboxylic acid, and salts thereof; a method of removing side wall; and a process for producing a semiconductor device. Use of the composition is effective in removing side wall at a low temperature in a short time in semiconductor device production without corroding the wiring material, e.g., an aluminium alloy. Thus, a semiconductor device having an aluminium alloy wiring which has undergone substantially no corrosion can be efficiently produced.

Abstract: A method for forming an optical waveguide includes depositing a cladding material on a first substrate, forming a trench in the cladding material on the first substrate, and filling the trench with a optically conductive core material. The upper surface of the cladding material and the optically conductive core material are then planarized to produce a substantially planar surface. The method further includes depositing a cladding material on a second substrate, forming a mirror image trench into the cladding material on the second substrate, and filling the mirror image trench with the optically conductive core material. The upper surface of the second cladding layer and the core material therein is then planarized. Thereafter, the first substrate is affixed to the second substrate such that the trench and the mirror image trench are in abutment and form a substantially circular optical core.

Abstract: A high density printed wiring board is prepared by applying an essentially solid material into plated through holes such that the metallized layers within the through hole are unaffected by chemical metal etchants. In this manner, lateral surface metallized layers can exclusively be reduced in thickness by use of said chemical agents. These thinned lateral surface metallized layers are ultimately converted into fine pitch, 25 to 40 microns, circuitry, thereby providing high density boards. Since the through hole wall metallization is unaffected by the etching process, excellent electrical connection between the fine line circuitry is obtained. Various printed wiring board embodiments are also presented.

Abstract: Low K dielectrics, such as porous silica, present a problem during damascene processing in that the trench floor tends to be rough, thus requiring a thicker than desired barrier layer. This problem has been overcome by fully covering the trench floor with a layer of a flowable material following which an etchant is provided that etches both the trench and flowable materials at approximately the same rate. Using this etchant, the trench floor is then uniformly etched until only a small amount of flowable material remains. After removal of any and all remaining flowable material, it is found that the roughness at the trench floor has been reduced by a factor of about 3-5. This allows a barrier layer of normal thickness to be used during the standard copper damascene process without danger of copper leakage. The process is particularly well suited for use with porous silica dielectrics having a dielectric constant less than about 2.5.

Abstract: A method and apparatus is disclosed that provided for the successful and precise smoothing of conductive films on insulating films or substrates. The smoothing technique provides a smooth surface that is substantially free of scratches. By supplying a source of electrons, harmful charging of the films and damage to the films are avoided.

Abstract: A thermoelectric device with improved efficiency is provided. In one embodiment, the thermoelectric device includes an electrical conductor thermally coupled to a cold plate and a thermoelement electrically coupled to the electrical conductor. The thermoelement is constructed from a thermoelectric material and has a plurality of tips through which the thermoelement is electrically coupled to the electrical conductor. The thermoelectric tips provide a low resistive connection while minimizing thermal conduction between the electrical conductor and the thermoelement.

Abstract: Provided are a method of forming a magnetic layer pattern and a method of manufacturing a thin film magnetic head, which can reduce the number of manufacturing steps and thus reduce the manufacturing time. A precursory nonmagnetic layer and a precursory bottom pole layer are formed in this sequence so as to cover a frame pattern formed on an underlayer (a top shield layer) and having an opening. Then, the precursory nonmagnetic layer and the precursory bottom pole layer are patterned by polishing the overall surface by CMP until at least the frame pattern is exposed, and thus a nonmagnetic layer and a bottom pole are selectively formed. The number of manufacturing steps can be reduced and thus the manufacturing time can be reduced, as compared to the case of forming the nonmagnetic layer and the bottom pole without forming the frame pattern.

Abstract: Planarizing solutions, planarizing machines and methods for planarizing microelectronic-device substrate assemblies using mechanical and/or chemical-mechanical planarizing processes. In one aspect of the invention, a microelectronic-device substrate assembly is planarized by abrading material from the substrate assembly using a plurality of first abrasive particles and removing material from the substrate assembly using a plurality second abrasive particles. The first abrasive particles have a first planarizing attribute, and the second abrasive particles have a second planarizing attribute. The first and second planarizing attributes are different from one another to preferably selectively remove topographical features from substrate assembly and/or selectively remove different types of material at the substrate surface.

Abstract: A gas at an extremely low temperature is jet-sprayed onto a warped concave surface of a wafer to correct this warped concave surface flat.