Etching Vapor Produced By Evaporation, Boiling, Or Sublimation Patents (Class 216/73)
  • Patent number: 10847636
    Abstract: A method for forming a semiconductor structure is provided. The method includes the following operations. A substrate is received. The substrate includes a fin structure, a semiconductor layer over the fin structure, and a dielectric layer sandwiched between the fin structure and the semiconductor layer. The semiconductor layer is patterned to form a sacrificial gate layer over a portion of the fin structure. A first cleaning operation is performed with a HF solution. Spacers are formed over sidewalls of the sacrificial gate layer. Recesses are formed in the fin structure at two sides of the sacrificial gate layer. A second cleaning operation is performed with an HF-containing plasma.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun Hsiung Tsai, Ru-Shang Hsiao, Clement Hsingjen Wann
  • Patent number: 10497579
    Abstract: Exemplary cleaning or etching methods may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. Methods may include forming a plasma within the remote plasma region to generate plasma effluents of the fluorine-containing precursor. The methods may also include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned within the processing region, and the substrate may include a region of exposed oxide and a region of exposed metal. Methods may also include providing a hydrogen-containing precursor to the processing region. The methods may further include removing at least a portion of the exposed oxide.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 3, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Zhijun Chen, Lin Xu, Anchuan Wang, Nitin Ingle
  • Patent number: 9873949
    Abstract: A method for producing a nanotip from a tip material provides a substrate which consists of the tip material or has the material in the form of a coating, produces a mask from a mask material selected so that, in a predefined reactive ion etching process, the mask material is removed at a lower etching rate than the tip material, and carries out the reactive ion etching process in an etching chamber. The mask material is additionally selected so that a gaseous component is released therefrom during the reactive ion etching process, the gaseous component not being released from the tip material. The method further comprises detecting the gaseous component while the ion etching process is being carried out, repeatedly determining whether an amount of the gaseous component in the etching chamber reaches a predefined lower threshold, and stopping the reactive ion etching process when the lower threshold is reached.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: January 23, 2018
    Assignee: IHP GmbH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ-INSTITUT FUR INNOVATIVE MIKROELEKTRONIK
    Inventors: Wolfgang Mehr, Andre Wolff
  • Patent number: 9418866
    Abstract: A gas processing method is described. A workpiece is mounted on a platform in a chamber on which a silicon oxide film is formed on a surface of the workpiece; HF gas and a NH3 gas, as reaction gases, are discharged onto the workpiece on the platform from a plurality of gas discharge holes of a shower plate; and a treatment for causing a reaction between the reaction gases and the silicon oxide film on the surface of the workpiece is performed. Subsequently, the reaction product resulting from the treatment is heated and removed by decomposition, whereby etching is performed. The shower plate is divided into a plurality of regions in correspondence with the workpiece, and the gas discharge holes in one or more of the regions are blocked to control a distribution of at least one of the HF gas and the NH3 gas.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: August 16, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Tomoki Suemasa
  • Patent number: 9318412
    Abstract: A method for semiconductor self-aligned patterning includes steps of providing a substrate comprising a first layer and a second layer, wherein the first layer is on top of the second layer; removing a portion of the first layer to form a first pattern; depositing a first conformal layer on the first pattern; depositing a second conformal layer on the first conformal layer; removing a portion of the second conformal layer to expose a portion of the first conformal layer; and thinning the first conformal layer and the second conformal layer alternatively to form a second pattern. A semiconductor self-aligned structure is also provided.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: April 19, 2016
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: An Hsiung Liu, Ya Chih Wang
  • Patent number: 8895449
    Abstract: A method of selectively removing fluorocarbon layers from overlying low-k dielectric material is described. These protective plasma treatments (PPT) are delicate alternatives to traditional post-etch treatments (PET). The method includes sequential exposure to (1) a local plasma formed from a silicon-fluorine precursor followed by (2) an exposure to plasma effluents formed in a remote plasma from a fluorine-containing precursor. The remote plasma etch (2) has been found to be highly selective of the residual material following the local plasma silicon-fluorine exposure. The sequential process (1)-(2) avoids exposing the low-k dielectric material to oxygen which would undesirably increase its dielectric constant.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: November 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Lina Zhu, Sean S. Kang, Srinivas D. Nemani, Chia-Ling Kao
  • Patent number: 8809195
    Abstract: A dry etch method, apparatus, and system for etching a high-k material comprises sequentially contacting the high-k material with a vapor phase reducing agent, and a volatilizing etchant in a cyclical process. In some preferred embodiments, the reducing agent and/or volatilizing etchant is plasma activated. Control over etch rate and/or selectivity are improved by the pulsed process, where, in some embodiments, each step in the cyclical process has a self-limited extent of etching. Embodiments of the method are useful in the fabrication of integrated devices, as well as for cleaning process chambers.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: August 19, 2014
    Assignee: ASM America, Inc.
    Inventor: Kai-Erik Elers
  • Patent number: 8801952
    Abstract: A method of etching silicon oxide from a trench is described which allows more homogeneous etch rates up and down the sides of the trench. One disclosed method includes a sequential introduction of (1) a hydrogen-containing precursor and then (2) a fluorine-containing precursor into a substrate processing region. The temperature of the substrate is low during each of the two steps in order to allow the reaction to proceed and form solid residue by-product. A second disclosed method reverses the order of steps (1) and (2) but still forms solid residue by-product. The solid residue by-product is removed by raising the temperature in a subsequent sublimation step regardless of the order of the two steps.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: August 12, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Anchuan Wang, Jingchun Zhang, Nitin K. Ingle, Young S. Lee
  • Patent number: 8771539
    Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor. The chemical reaction resulting from the combination produces reactants which etch the patterned heterogeneous structures to produce, in embodiments, a thin residual structure exhibiting little deformation. The methods may be used to conformally trim silicon oxide while removing little or no silicon, polysilicon, silicon nitride, titanium or titanium nitride. In an exemplary embodiment, the etch processes described herein have been found to remove mold oxide around a thin cylindrical conducting structure without causing the cylindrical structure to significantly deform.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: July 8, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jingchun Zhang, Anchuan Wang, Nitin K. Ingle
  • Patent number: 8709949
    Abstract: According to embodiments of the present disclosure, a method for removing oxide includes placing a sensor chip assembly having an oxide layer formed on a portion thereof within an enclosed and controlled environment. The portion of the sensor chip assembly is exposed to a reactive gas and a UV light to result in a substantial removal of the oxide layer formed on the portion of the sensor chip assembly.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: April 29, 2014
    Assignee: Raytheon Company
    Inventors: Andreas Hampp, Sean F. Harris, Talieh H. Sadighi, Bengi F. Hanyaloglu
  • Patent number: 8679354
    Abstract: A controlled method of releasing a microstructure comprising a silicon oxide layer located between a substrate layer and a layer to be released from the silicon oxide layer is described. The method comprises the step of exposing the silicon oxide layer to a hydrogen fluoride vapor in a process chamber having controlled temperature and pressure conditions. A by-product of this reaction is water which also acts as a catalyst for the etching process. It is controlled employment of this inherent water source that results in a condensed fluid layer forming, and hence etching taking place, only on the exposed surfaces of the oxide layer. The described method therefore reduces the risk of the effects of capillary induced stiction within the etched microstructure and/or corrosion within the microstructure and the process chamber itself.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: March 25, 2014
    Assignee: Memsstar Limited
    Inventor: Anthony O'Hara
  • Patent number: 8679985
    Abstract: A dry etching method for a silicon nitride film capable of improving throughput is provided. A dry etching method for dry-etching a silicon nitride film 103 includes dry-etching the silicon nitride film 103 without generating plasma by using a processing gas containing at least a hydrogen fluoride gas (HF gas) and a fluorine gas (F2 gas), with respect to a processing target object 100 including the silicon nitride film 103.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: March 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Eiichi Nishimura, Yusuke Shimizu
  • Patent number: 8652970
    Abstract: A processing gas is introduced to remove an oxide film on the surface of a silicon substrate 5. F radicals are allowed to act on the surface of the silicon substrate to etch a silicon layer. Then, NH3 gas, N2 gas and NF3 gas are introduced, allowing NHxFy to act on the oxidized surface of the silicon substrate 5, thereby forming (NH4)2SiF6. The resulting (NH4)2SiF6 is sublimated to remove by-products (SiOF, SiOH) on the surface of the silicon substrate 5.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: February 18, 2014
    Assignee: Ulvac, Inc.
    Inventors: Yoshiyasu Tajima, Seiichi Takahashi, Kyuzo Nakamura
  • Patent number: 8536062
    Abstract: Methods are provided for removing an oxide layer from a metal pad on an integrated circuit in order to reduce contact resistance. In one embodiment, aluminum oxide, on the surface of a bond pad substantially comprised of aluminum, is reacted with a first chemical agent to form an inorganic salt, and the inorganic salt is then reacted with a second chemical agent leaving a substantially bare, that is, unoxidized, aluminum surface.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: September 17, 2013
    Assignee: Advanced Inquiry Systems, Inc.
    Inventor: Jens Ruffler
  • Patent number: 8530356
    Abstract: A method of removing a high molecular weight organic-comprising hard mask or BARC from a surface of a porous low k dielectric material, where a change in the dielectric constant of the low k dielectric material is less than about 5% after application of the method. The method comprises exposing the organic-comprising hard mask or BARC to nitric acid vapor which contains at least 68% by mass HNO3.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: September 10, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Roman Gouk, Steven Verhaverbeke, Han-Wen Chen
  • Patent number: 8444868
    Abstract: The invention is directed to a method for removing copper oxide from a copper surface to provide a clean copper surface, wherein the method involves exposing the copper surface containing copper oxide thereon to an anhydrous vapor containing a carboxylic acid compound therein, wherein the anhydrous vapor is generated from an anhydrous organic solution containing the carboxylic acid and one or more solvents selected from hydrocarbon and ether solvents.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Tien-Jen Cheng, Stephan Grunow, Zhengwen Li, Huilong Zhu
  • Patent number: 8257602
    Abstract: In a system and method of etching a sample disposed in an etching chamber, a plurality of separately stored charges of an etching gas is discharged, one at a time, into a sample etching chamber. The discharge of each charge of etching gas occurs such that a momentary overlap exists in the end discharge of one charge of etching gas with the beginning discharge of another charge of etching gas, whereupon the desired flow of etching gas into the etching chamber is maintained. During discharge of one charge of etching gas, a previously discharged charge of etching gas is recharged. The process of discharging a plurality of separately stored charges of an etching gas, one at a time, and recharging at least one previously discharged charges of etching gas during the discharge of at least one charge of etching gas continues until the sample is etched to a desired extent.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: September 4, 2012
    Assignee: Xactix, Inc.
    Inventors: Kyle S. Lebouitz, David L. Springer
  • Patent number: 8175736
    Abstract: A processing system and method for chemical oxide removal (COR) is presented, wherein the processing system comprises a first treatment chamber and a second treatment chamber, wherein the first and second treatment chambers are coupled to one another. The first treatment chamber comprises a chemical treatment chamber that provides a temperature controlled chamber, and an independently temperature controlled substrate holder for supporting a substrate for chemical treatment. The substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. The second treatment chamber comprises a heat treatment chamber that provides a temperature controlled chamber, thermally insulated from the chemical treatment chamber. The heat treatment chamber provides a substrate holder for controlling the temperature of the substrate to thermally process the chemically treated surfaces on the substrate.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: May 8, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Masayuki Tomoyasu, Merritt Funk, Kevin A. Pinto, Masaya Odagiri, Lemuel Chen, Asao Yamashita, Akira Iwami, Hiroyuki Takahashi
  • Patent number: 8153533
    Abstract: Methods for preventing feature collapse subsequent to etching a layer encasing the features include adding a non-aqueous liquid to a microelectronic topography having remnants of an aqueous liquid arranged upon its surface and subsequently exposing the topography to a pressurized chamber including a fluid at or greater than its saturated vapor pressure or critical pressure. The methods include flushing from the pressurized chamber liquid arranged upon the topography and, thereafter, venting the chamber in a manner sufficient to prevent liquid formation therein. The topography features may be submerged in a liquid while pressurizing the chamber. A process chamber used to prevent feature collapse includes a substrate holder for supporting a microelectronic topography, a vessel configured to contain the substrate holder, and a sealable region surrounding the substrate holder and the vessel. The chamber is configured to sequester wet chemistry supplied to the vessel from metallic surfaces of the sealable region.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: April 10, 2012
    Assignee: Lam Research
    Inventors: James P. DeYoung, Mark I. Wagner
  • Patent number: 8138095
    Abstract: Substrate processing apparatus 100 includes supporting table 103 for not only supporting a target substrate W but also heating the target substrate W; processing chamber 101 having the supporting table disposed therein; and gas supply unit 102 for supplying a processing gas into the processing chamber 101. The processing gas includes organic acid metal complex or organic acid metal salt.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: March 20, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Hidenori Miyoshi
  • Patent number: 8133325
    Abstract: This dry cleaning method for a plasma processing apparatus is a dry cleaning method for a plasma processing apparatus that includes: a vacuum container provided with a dielectric member; a planar electrode and a high-frequency antenna that are provided outside the dielectric member; and a high-frequency power source that supplies high-frequency power to both the high-frequency antenna and the planar electrode, to thereby introduce high-frequency power into the vacuum container via the dielectric member and produce an inductively-coupled plasma, the method comprising the steps of: introducing a gas including fluorine into the vacuum container and also introducing high-frequency power into the vacuum container from the high-frequency power source, to thereby produce an inductively-coupled plasma in the gas including fluorine; and by use of the inductively-coupled plasma, removing a product including at least one of a precious metal and a ferroelectric that is adhered to the dielectric member.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: March 13, 2012
    Assignee: ULVAC, Inc.
    Inventors: Masahisa Ueda, Yutaka Kokaze, Mitsuhiro Endou, Koukou Suu
  • Patent number: 8034720
    Abstract: A substrate processing method that can remove a silicon nitride film without damaging a thermally-oxidized film. A substrate having at least a thermally-oxidized film and a silicon nitride film formed on the thermally-oxidized film is heated to a temperature of not less than 60° C. Then, hydrogen fluoride gas is supplied toward the substrate.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: October 11, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Eiichi Nishimura, Chie Kato, Jun Yamawaku
  • Publication number: 20110240600
    Abstract: A processing gas is introduced to remove an oxide film on the surface of a silicon substrate 5. F radicals are allowed to act on the surface of the silicon substrate to etch a silicon layer. Then, NH3 gas, N2 gas and NF3 gas are introduced, allowing NHxFy to act on the oxidized surface of the silicon substrate 5, thereby forming (NH4)2SiF6. The resulting (NH4)2SiF6 is sublimated to remove by-products (SiOF, SiOH) on the surface of the silicon substrate 5.
    Type: Application
    Filed: March 24, 2010
    Publication date: October 6, 2011
    Applicant: ULVAC ,INC.
    Inventors: Yoshiyasu Tajima, Seiichi Takahashi, Kyuzo Nakamura
  • Patent number: 7877161
    Abstract: A processing system and method for chemical oxide removal (COR) is presented, wherein the processing system comprises a first treatment chamber and a second treatment chamber, wherein the first and second treatment chambers are coupled to one another. The first treatment chamber comprises a chemical treatment chamber that provides a temperature controlled chamber, and an independently temperature controlled substrate holder for supporting a substrate for chemical treatment. The substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. The second treatment chamber comprises a heat treatment chamber that provides a temperature controlled chamber, thermally insulated from the chemical treatment chamber. The heat treatment chamber provides a substrate holder for controlling the temperature of the substrate to thermally process the chemically treated surfaces on the substrate.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: January 25, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Masayuki Tomoyasu, Merritt Lane Funk, Kevin Augustine Pinto, Masaya Odagiri, Lemuel Chen, Asao Yamashita, Akira Iwami, Hiroyuki Takahashi
  • Patent number: 7846347
    Abstract: The invention provides for a method and integrated system for removing a halogen-containing residue from a substrate comprising etching the substrate, heating the substrate and exposing the heated substrate to a plasma that removes the halogen-containing residue.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: December 7, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Mark N. Kawaguchi, James S. Papanu, Scott Williams, Matthew Fenton Davis
  • Patent number: 7638435
    Abstract: In an apparatus and method of vapor etching, a sample (S) to be etched is located in a main chamber (107) from which the atmosphere inside is evacuated. Etching gas is input into the main chamber (107) for a first period of time. Thereafter, the etching gas is evacuated from the main chamber (107) and cooling/purging gas is input into the main chamber for a second interval of time. Thereafter, the cooling/purging gas is evacuated from the main chamber (107). Desirably, the steps of inputting the etching gas into the main chamber (107) for the first period of time, evacuating the etching gas from the main chamber, inputting the cooling/purging gas into the main chamber (107) for the second period of time, and evacuating the cooling/purging gas from the main chamber are repeated until samples have been etched to a desired extent.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: December 29, 2009
    Assignee: Xactix, Inc.
    Inventors: Kyle S. Lebouitz, David L. Springer
  • Patent number: 7625603
    Abstract: A silicon oxide layer is formed by oxidation or decomposition of a silicon precursor gas in an oxygen-rich environment followed by annealing. The silicon oxide layer may be formed with slightly compressive stress to yield, following annealing, an oxide layer having very low stress. The silicon oxide layer thus formed is readily etched without resulting residue using HF-vapor.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: December 1, 2009
    Assignee: Robert Bosch GmbH
    Inventors: Aaron Partridge, Markus Lutz, Silvia Kronmueller
  • Patent number: 7431853
    Abstract: A method and system for release etching a micro-electrical-mechanical-systems (MEMS) device from a substrate. In one aspect, the invention is a method comprising (a) supporting at least one substrate having a sacrificial oxide and a non-sacrificial material in a process chamber at a pressure and at a temperature; (b) introducing a gas phase mixture comprising a halide-containing species and an alcohol vapor selected from a group consisting of ethanol, 1-propanol, and an aliphatic alcohol having four carbon groups into the process chamber, the gas phase mixture having a volumetric ratio of the halide-containing species to the alcohol vapor of approximately 2 or less; and (c) etching the sacrificial oxide with the gas phase mixture. In another aspect, the invention is a system for carrying out the method.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: October 7, 2008
    Assignee: Primaxx, Inc.
    Inventors: Paul D. Mumbauer, Paul Roman, Robert Grant
  • Patent number: 7374696
    Abstract: The invention provides for a method and integrated system for removing a halogen-containing residue from a substrate comprising etching the substrate, heating the substrate and exposing the heated substrate to a plasma that removes the halogen-containing residue.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: May 20, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Mark N. Kawaguchi, James S. Papanu, Scott Williams, Matthew Fenton Davis
  • Patent number: 7365016
    Abstract: A method of etching a sacrificial oxide layer covering an etch-stop silicon nitride underlayer, involves exposing the sacrificial oxide to anhydrous HF at a temperature of less than about 100° C. and/or at vacuum level lower than 40 Torr; and subsequently performing an in-situ vacuum evaporation of etch by-products at a temperature of more than about 100° C. and at vacuum level lower than the 40 Torr without exposure to ambient air.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: April 29, 2008
    Assignee: DALSA Semiconductor Inc.
    Inventors: Luc Ouellet, Ghislain Migneault, Jun Li
  • Patent number: 7291559
    Abstract: In a method of manufacturing a semiconductor device, a dummy sample and an actual device are prepared. The dummy sample and the actual device have substantially an identical layer and an identical resist pattern formed on the layer. Then, a dummy discharge is carried out. The layer and the resist pattern of the dummy sample are etched in an etching device so that the layer and the resist pattern of the dummy device are simultaneously slimmed. Finally, the layer and the resist pattern of the actual device are etched in the etching device after the etching of the dummy sample so that the layer and the resist pattern of the actual device are simultaneously slimmed.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: November 6, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akira Takahashi
  • Patent number: 7279431
    Abstract: An etch release for a MEMS device on a substrate includes etching the substrate with an etchant vapor and a wetting vapor. A thermal bake of the MEMS device, after the etch release may be used to volatilize residues. A supercritical fluid may also be used to remove residual contaminants. The combination of the etchant vapor, such as HF, and the wetting vapor, such as an alcohol vapor, improves the uniformity of the etch undercut on the substrate.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: October 9, 2007
    Assignee: Semitool, Inc.
    Inventor: Eric J. Bergman
  • Patent number: 7189332
    Abstract: Processes for the removal of a layer or region from a workpiece material by contact with a process gas in the manufacture of a microstructure are enhanced by the ability to accurately determine the endpoint of the removal step. A vapor phase etchant is used to remove a material that has been deposited on a substrate, with or without other deposited structure thereon. By creating an impedance at the exit of an etching chamber (or downstream thereof), as the vapor phase etchant passes from the etching chamber, a gaseous product of the etching reaction is monitored, and the endpoint of the removal process can be determined. The vapor phase etching process can be flow through, a combination of flow through and pulse, or recirculated back to the etching chamber.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: March 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Satyadev R. Patel, Gregory P. Schaadt, Douglas B. MacDonald, Niles K. MacDonald, Hongqin Shi
  • Patent number: 7153443
    Abstract: A microstructure and the method for making the same are disclosed herein. The microstructure has structural members, at least one of which comprises an intermetallic compound. In making such a microstructure, a sacrificial material is employed. After completion of forming the structural layers, the sacrificial material is removed by a spontaneous vapor phase chemical etchant.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: December 26, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan Doan, Satyadev Patel
  • Patent number: 7052622
    Abstract: A method of determining the time to release of a movable feature in a multilayer substrate of silicon-containing materials including alternate layers of polysilicon and silicon oxide wherein a mass monitoring device determines the mass of a released feature, and the substrate is etched with anhydrous hydrogen fluoride until the substrate mass is equivalent to that of the released movable feature when the etch time is noted. A suitable mass monitoring device is a quartz crystal microbalance.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: May 30, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey D. Chinn, Robert Z. Bachrach
  • Patent number: 7041224
    Abstract: The etching of a material in a vapor phase etchant is disclosed where a vapor phase etchant is provided to an etching chamber at a total gas pressure of 10 Torr or more, preferably 20 Torr or even 200 Torr or more. The vapor phase etchant can be gaseous acid etchant, a noble gas halide or an interhalogen. The sample/workpiece that is etched can be, for example, a semiconductor device or MEMS device, etc. The material that is etched/removed by the vapor phase etchant is preferably silicon and the vapor phase etchant is preferably provided along with one or more diluents. Another feature of the etching system includes the ability to accurately determine the end point of the etch step, such as by creating an impedance at the exit of the etching chamber (or downstream thereof) so that when the vapor phase etchant passes from the etching chamber, a gaseous product of the etching reaction is monitored, and the end point of the removal process can be determined.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: May 9, 2006
    Assignee: Reflectivity, Inc.
    Inventors: Satyadev R. Patel, Gregory P. Schaadt, Douglas B. MacDonald, Hongqin Shi, Andrew G. Huibers, Peter Heureux
  • Patent number: 6932915
    Abstract: An integrated oxide removal and processing system (10) includes a process module (30) that may intentionally add at least one film layer to a single semiconductor wafer (32). The integrated oxide removal and processing system (10) also includes a transfer chamber module (20) used to align the semiconductor wafer (32) for the process module (30). The transfer chamber module (20) may expose the semiconductor wafer (32) to a vaporous solution that is inert with respect to the semiconductor wafer (32) and operable to remove an oxide layer (110) therefrom. More specifically, the semiconductor wafer (32) includes silicon. In a further embodiment, the vaporous solution includes HF. In yet a further embodiment, the vaporous solution includes 0.049% to 49% HF.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: August 23, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Sylvia H. Pas
  • Patent number: 6887337
    Abstract: An etching apparatus for etching semi combustion samples may include one or more variable volume expansion chambers, two or more fixed volume expansion chambers, or combinations thereof in fluid communication with an etching chamber and a source of etching gas, such as xenon difluoride. The apparatus may further include a source of a mixing gas. An etching apparatus may also include a source of etching gas, an etching chamber in fluid communication with the source of etching gas, a flow controller connected between the source of etching gas and the etching chamber, and a vacuum pump in fluid communication with the etching chamber. A source for providing a gas by sublimation from a solid material is also provided, including a vacuum tight container and a mesh mounted in the interior of the vacuum tight container, wherein the mesh is adapted to receive and restrain the solid material.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: May 3, 2005
    Assignee: XACTIX, Inc.
    Inventors: Kyle S. Lebouitz, Michele Migliuolo
  • Publication number: 20040169011
    Abstract: An object of this invention is to suppress the amount of etchant used. A liquid etchant is stored in an etchant vessel, and vaporized by a vaporization unit. A fragile layer such as a porous layer is selectively etched with the vaporized etchant.
    Type: Application
    Filed: January 12, 2004
    Publication date: September 2, 2004
    Applicant: Canon Kabushiki Kaisha
    Inventors: Kazuhito Takanashi, Kenji Yamagata, Kiyofumi Sakaguchi, Kazutaka Yanagita, Takashi Sugai, Takashi Tsuboi
  • Patent number: 6740247
    Abstract: The invention provides HF vapor process conditions that can be precisely controlled with a high degree of reproducibility for a wide range of starting wafer conditions. These HF vapor processes for, e.g., etching oxide on a semiconductor substrate, cleaning a contaminant on a semiconductor substrate, removing etch residue from a metal structure on a semiconductor substrate, and cleaning a metal contact region of a semiconductor substrate. In the HF vapor process, a semiconductor substrate having oxide, a contaminant, metal etch residue, or a contact region to be processed is exposed to hydrofluoric acid vapor and water vapor in a process chamber held at temperature and pressure conditions that are controlled to form on the substrate no more than a sub-monolayer of etch reactants and products produced by the vapor as the substrate is processed by the vapor.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: May 25, 2004
    Assignee: Massachusetts Institute of Technology
    Inventors: Yong-Pil Han, Herbert H. Sawin
  • Patent number: 6620335
    Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.
    Type: Grant
    Filed: December 7, 1999
    Date of Patent: September 16, 2003
    Assignee: Tegal Corporation
    Inventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer, Robert C. Vail, Kurt A. Olson
  • Patent number: 6602433
    Abstract: A substrate is treated by supplying an etchant and/or deposition gas into a chamber in which the substrate is situated. In order to avoid the problems associated with transportation of toxic gases, the gases required for such processes are delivered directly from a gas generation and delivery system positioned locally to the chamber.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: August 5, 2003
    Assignee: Surface Technology Systems PLC
    Inventors: Jyoti Kiron Bhardwaj, Nicholas Shepherd, Leslie Michael Lea
  • Patent number: 6558559
    Abstract: A method of sacrificial layer etching of micromechanical surface structures, in which a sacrificial layer is deposited on a heatable silicon substrate and is structured. A temperature difference between the substrate and the vapor phase of an etching medium is established in such a way that exposed metal contacts made of aluminum alloys are not attacked at the same time and are not subsequently exposed to any risk of corrosion.
    Type: Grant
    Filed: February 5, 1998
    Date of Patent: May 6, 2003
    Assignee: Robert Bosch GmbH
    Inventors: Volker Becker, Franz Laermer, Michael Offenberg, Andrea Schilp
  • Publication number: 20020195423
    Abstract: The etching of a material in a vapor phase etchant is disclosed where a vapor phase etchant is provided to an etching chamber at a total gas pressure of 10 Torr or more, preferably 20 Torr or even 200 Torr or more. The vapor phase etchant can be gaseous acid etchant, a noble gas halide or an interhalogen. The sample/workpiece that is etched can be, for example, a semiconductor device or MEMS device, etc. The material that is etched/removed by the vapor phase etchant is preferably silicon and the vapor phase etchant is preferably provided along with one or more diluents. Another feature of the etching system includes the ability to accurately determine the end point of the etch step, such as by creating an impedance at the exit of the etching chamber (or downstream thereof) so that when the vapor phase etchant passes from the etching chamber, a gaseous product of the etching reaction is monitored, and the end point of the removal process can be determined.
    Type: Application
    Filed: March 22, 2002
    Publication date: December 26, 2002
    Applicant: REFLECTIVITY, INC.
    Inventors: Satyadev R. Patel, Gregory P. Schaadt, Douglas B. MacDonald, Hongqin Shi, Andrew G. Huibers, Peter Heureux
  • Publication number: 20020121502
    Abstract: The etching of a sacrificial silicon portion in a microstructure such as a microelectromechanical structure by the use of etchant gases that are noble gas fluorides or halogen fluorides is performed with greater selectivity toward the silicon portion relative to other portions of the microstructure by slowing the etch rate. The etch rate is preferably 30 um/hr or less, and can be 3 um/hr or even less. The selectivity is also improved by the addition of non-etchant gaseous additives to the etchant gas. Preferably the non-etchant gaseous additives that have a molar-averaged formula weight that is below that of molecular nitrogen offer significant advantages over gaseous additives of higher formula weights by causing completion of the etch in a shorter period of time while still achieving the same improvement in selectivity. The etch process is also enhanced by the ability to accurately determine the end point of the removal step.
    Type: Application
    Filed: September 17, 2001
    Publication date: September 5, 2002
    Inventors: Satyadev R. Patel, Gregory P. Schaadt, Douglas B. MacDonald, Hongqin Shi
  • Publication number: 20020030035
    Abstract: Recycling process for CdTe/CdS thin film-solar cell modules in which the modules are mechanically disintegrated into module fragments, the module fragments are exposed to an oxygen-containing atmosphere at a temperature of at least 300° C. causing a pyrolysis of adhesive material contained in the module fragments in form of a hydrocarbon based plastics material and the gaseous decomposition products that are generated during the pyrolysis are discharged, and, afterwards, the module fragments freed from the adhesive means are exposed to a chlorine-containing gas atmosphere at a temperature of more than 400° C. causing an etching process wherein the CdCl2 and TeCl4 that are generated in the etching process are made to condense and precipitate by cooling.
    Type: Application
    Filed: August 24, 2001
    Publication date: March 14, 2002
    Inventors: Manuel Dieguez, Dieter Bonnet, Rainer Gegenwart, Jutta Beier
  • Patent number: 6333268
    Abstract: Adherent matrix layers such as post-etch and other post-process residues are removed from a substrate by exposing them to a vapor phase solvent to allow penetration of the vapor phase solvent into the adherent matrix layers and condensing the vapor phase solvent into the adherent matrix layers and revaporized to promote fragmentation of the matrix and facilitate removal. Megasonic energy may be transmitted via a transmission member to the adherent matrix through the solvent condensed thereon to loosen fragments and particles. The substrate is typically rotated to improve contact between the megasonic energy transmission member and the condensed solvent and achieve more uniform cleaning. A co-solvent which is soluble in the vapor phase solvent may be added to enhance removal of specific adherent matrix materials.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: December 25, 2001
    Assignee: Novellus Systems, Inc.
    Inventors: Vladimir Starov, Shmuel Erez, Syed S. Basha, Arkadiy I. Shimanovich, Ravi Vellanki, Krishnan Shrinivasan, Karen A. Reinhardt, Aleksandr Kabansky
  • Publication number: 20010028922
    Abstract: A method for filling gaps in high aspect ratio patterned features on an integrated circuit using plasma CVD processes. A plasma is generated by an inert gas and process gases including silicon and oxygen components. The plasma causes the product gases to react and deposit onto the substrate and concurrently etch the deposited film. During an initial stage, the net deposition rate is kept low to improve filling of the high aspect ratio features, while during one or more later stages the net deposition rate is increased to provide a more conformal film at a higher throughput.
    Type: Application
    Filed: January 4, 2001
    Publication date: October 11, 2001
    Inventor: Gurtej S. Sandhu
  • Patent number: 6290864
    Abstract: The etching of a sacrificial silicon portion in a microstructure such as a microelectromechanical structure by the use of etchant gases that are noble gas fluorides or halogen fluorides is performed with greater selectivity toward the silicon portion relative to other portions of the microstructure by the addition of non-etchant gaseous additives to the etchant gas. An additional discovery is that non-etchant gaseous additives that have a molar averaged formula weight that is below that of molecular nitrogen offer significant advantages over gaseous additives of higher formula weights by causing completion of the etch in a shorter period of time while still achieving the same improvement in selectivity.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: September 18, 2001
    Assignee: Reflectivity, Inc.
    Inventors: Satyadev R. Patel, Gregory P. Schaadt, Douglas B. MacDonald
  • Patent number: RE38760
    Abstract: Oxides are etched with a halide-containing species and a low molecular weight organic molecule having a high vapor pressure at standard conditions, where etching is performed at preset wafer temperature in an enclosed chamber at a pressure such that all species present in the chamber, including water, are in the gas phase and condensation of species present on the etched surface is controlled. Thus all species involved remain in the gas phase even if trace water vapor appears in the process chamber. Preferably, etching is performed in a cluster dry tool apparatus.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: July 19, 2005
    Assignee: Penn State Research Foundation
    Inventors: Robert W. Grant, Jerzy Ruzyllo, Kevin Torek