Gas Phase Etching Of Substrate Patents (Class 216/58)
  • Patent number: 10872784
    Abstract: An etching gas mixture, a method of forming a pattern using the etching gas mixture, and a method of manufacturing an integrated circuit device using the etching gas mixture, the etching gas mixture including a C1-C3 perfluorinated alkyl hypofluorite; and a C1-C10 organosulfur compound that includes a C—S bond in the compound.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: December 22, 2020
    Assignees: SAMSUNG ELECTRONICS CO., LTD., Wonik Materials
    Inventors: Do-hoon Kim, Tae-hyung Kim, Jong-min Baek, Han-dock Song
  • Patent number: 10818506
    Abstract: An etching method of etching a silica-based residue containing a base component formed in an SiO2 film, includes selectively etching the silica-based residue by supplying an HF gas, an H2O gas or an alcohol gas to a target substrate having the SiO2 film, on which the silica-based residue is formed, and removing an etching residue caused by the selectively etching the silica-based residue, after the selectively etching the silica-based residue. The removing an etching residue includes a first process of supplying an H2O gas or an alcohol gas to the target substrate and a second process of heating the target substrate after the first process.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: October 27, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Noriyuki Kobayashi, Toshinori Debari
  • Patent number: 10672603
    Abstract: A system is described for removing a dielectric gel, which has been layered atop the electrical components of a failed electrical system, without further damaging the electrical components of the failed electrical system. The system includes a raster component configured to project a laser for vaporizing a dielectric layer of an electric component into a plasma plume located above the dielectric layer. The system further includes a first vacuum nozzle positioned on a first side of the raster component and configured to extract a first portion of the plasma plume while the plasma plume is located above the dielectric layer, and a second vacuum nozzle positioned on a second side of the raster component and configured to extract a second portion of the plasma plume while the plasma plume is located above the dielectric layer.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: June 2, 2020
    Assignee: Infineon Technologies AG
    Inventor: Gregory Anderson
  • Patent number: 10586710
    Abstract: Provided is a method of etching a silicon-containing film made of at least one of silicon oxide and silicon nitride. The etching method includes: (i) preparing a workpiece having a silicon-containing film and a mask provided on the silicon-containing film in a chamber body of a plasma processing apparatus, in which an opening is formed in the mask; and (ii) etching the silicon-containing film, in which plasma is produced in the chamber body from processing gas containing fluorine, hydrogen, and iodine in order to etch the silicon-containing film, and a temperature of the workpiece is set to a temperature of 0° C. or less.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: March 10, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Maju Tomura, Yoshihide Kihara, Masanobu Honda
  • Patent number: 10580669
    Abstract: After a discharge of a processing liquid is stopped, a position of a liquid surface within a nozzle can be observed. A substrate processing apparatus includes a substrate holding mechanism and the nozzle. The substrate holding mechanism is configured to hold a substrate. The nozzle is configured to supply the processing liquid to the substrate. The nozzle includes a pipe member and an observation window. The pipe member has a horizontal part and a downward part extended downwards from the horizontal part, and is configured to discharge the processing liquid from a tip end of the downward part. The observation window is provided at the horizontal part of the pipe member.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: March 3, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tsuyoshi Fukushima, Kazuhiro Aiura, Norihiro Ito
  • Patent number: 10559488
    Abstract: A two-level tape frame rinse assembly is configured for grasping the substrate so as to create a gap between the substrate and a backside support plate that allows the backside of the wafer to be rinsed and spun dry after rinsing.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 11, 2020
    Assignee: VEECO PRECISION SURFACE PROCESSING LLC
    Inventors: William Gilbert Breingan, John Taddei, James Swallow
  • Patent number: 10490415
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film on the first film. The method further includes simultaneously flowing a first gas with a second gas containing a metal element to form a first opening in the second film and forming a third film containing the metal element on a side surface of the first opening. The method further includes forming a second opening in the first film below the first opening using the second film as a mask.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: November 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsubasa Imamura, Atsushi Takahashi, Toshiyuki Sasaki
  • Patent number: 10483010
    Abstract: A system for reducing surface and embedded charge in a substrate includes a substrate support configured to support a substrate. A vacuum ultraviolet (VUV) assembly is arranged adjacent to the substrate and includes a housing and a VUV lamp that is connected to the housing and that generates and directs ultraviolet (UV) light at the substrate. A movement device is configured to move at least one of the VUV assembly and the substrate support during exposure of the substrate to the UV light to reduce surface and embedded charge in the substrate.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: November 19, 2019
    Assignee: LAM RESEARCH AG
    Inventors: Rafal Dylewicz, Reinhold Schwarzenbacher, Xia Man, Kenichi Sano, David Lou, Milan Pliska
  • Patent number: 10446453
    Abstract: A method is disclosed for monitoring and controlling a process of plasma-assisted surface modification of a layer formed on a substrate. The method includes flowing a surface modification gas into a plasma processing chamber of a plasma processing system, igniting a plasma in the plasma processing chamber to initiate a surface modification process for a layer formed on a substrate, and acquiring optical emission spectra from an optical emission spectroscopy system attached to the plasma processing chamber, during the surface modification process for the layer. For one embodiment, the method includes altering at least one parameter of the surface modification process based on the acquired optical emission spectra. For one embodiment, the acquired optical emission spectra can include an intensity of a spectral line, a slope of a spectral line, or both to enable endpoint control of the surface modification process. Additional methods and related systems are also disclosed.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: October 15, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Brian J. Coppa, Viswas Purohit, Seiichi Watanabe, Kenji Komatsu
  • Patent number: 10431458
    Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. In many embodiments, a mask shrink layer is deposited on a patterned mask layer to thereby narrow the openings in the mask layer. The mask shrink layer may be deposited through a vapor deposition process including, but not limited to, atomic layer deposition or chemical vapor deposition. The mask shrink layer can result in narrower, more vertically uniform etched features. In some embodiments, etching is completed in a single etch step. In some other embodiments, the etching may be done in stages, cycled with a deposition step designed to deposit a protective sidewall coating on the partially etched features. Metal-containing films are particularly suitable as mask shrink films and protective sidewall coatings.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: October 1, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyunjong Shim, Merrett Wong
  • Patent number: 10373840
    Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants and/or reaction mechanisms that result in substantially complete sidewall coating at relatively low temperatures without the use of plasma. In some cases the protective coating is deposited using molecular layer deposition techniques.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: August 6, 2019
    Assignee: Lam Research Corporation
    Inventors: Eric A. Hudson, Dennis M. Hausmann, Joseph Scott Briggs
  • Patent number: 10329192
    Abstract: A composition for primer layer coating of a water- and oil-repellent coating layer so as to enhance the durability of the water- and oil-repellent coating layer, comprises a mixture which comprises at least one of a silicon oxide (SiOx) and titanium (Ti) compound, an aluminum (Al) compound and a zirconium (Zr) compound. A preparation method may comprise: preparing a glass or polymer substrate; forming, on the substrate, a portion on which a fingerprint-resistant layer is to be deposited within the substrate by etching; depositing a primer layer consisting of the composition on the surface of the substrate including the portion where the water- and oil-repellent coating layer is deposited; forming the water- and oil-repellent coating layer on the deposited primer layer; and purging the substrate on which the water- and oil-repellent coating layer is formed. The method has excellent wear-resistance, salt water resistance, chemical resistance and cosmetics resistance.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: June 25, 2019
    Assignee: Gaema Tech. Co., Ltd.
    Inventors: Hun Rae Kim, Zee Young Lee
  • Patent number: 10281820
    Abstract: The present application relates to a block copolymer and uses thereof. The present application can provide a block copolymer—which exhibits an excellent self-assembling property and thus can be used effectively in a variety of applications—and uses thereof.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: May 7, 2019
    Assignee: LG Chem, Ltd.
    Inventors: Jung Keun Kim, Je Gwon Lee, Jeong Kyu Lee, Se Jin Ku, No Jin Park, Mi Sook Lee, Eun Young Choi, Sung Soo Yoon, Hyung Ju Ryu
  • Patent number: 10262835
    Abstract: A plasma processing equipment includes a vacuum processing chamber, an insulating material, a gas inlet, a high frequency induction antenna provided at an upper outside of the vacuum processing chamber, a magnetic field coil, a yoke for controlling distribution of a magnetic field in the vacuum processing chamber, a high frequency power supply for generating plasma and supplying a high frequency current to the antenna, and a power supply for supplying power to the magnetic field coil. The antenna is divided into n high frequency induction antenna elements are arranged in tandem on one circle so that a high frequency current delayed sequentially by ? (wavelength of high frequency power supply)/n flows clockwise through the antenna elements arranged in tandem via a delay unit, and a magnetic field is applied from the magnetic field coil to generate electron cyclotron resonance (ECR) phenomenon.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 16, 2019
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventor: Ryoji Nishio
  • Patent number: 10217646
    Abstract: Transition metal dry etch by atomic layer removal of oxide layers for device fabrication, and the resulting devices, are described. In an example, a method of etching a film includes reacting a surface layer of a transition metal species of a transition metal-containing film with a molecular oxidant species. The method also includes removing volatile fragments of the reacted molecular oxidant species to provide an oxidized surface layer of the transition metal species. The method also includes reacting the oxidized surface layer of the transition metal species with a molecular etchant. The method also includes removing the reacted oxidized surface layer of the transition metal species and the reacted molecular etchant by volatlilization.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Patricio E. Romero, John J. Plombon
  • Patent number: 10204805
    Abstract: The present disclosure relates to an apparatus for heating and supporting a substrate in a processing chamber. A substrate support assembly includes a heated plate having a substrate supporting surface on a front side and a cantilever arm extending from a backside of the heated plate. The heated plate is configured to support and heat a substrate on the substrate supporting surface. The cantilever arm has a first end attached to the heated plate near a central axis of the heated plate, and a second end extending radially outwards from the central axis.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: February 12, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Imad Yousif, Martin Jeffrey Salinas, Paul B. Reuter, Aniruddha Pal, Jared Ahmad Lee
  • Patent number: 10180247
    Abstract: According to aspects of the disclosed subject matter, a method of placing a solid state light source on a heat sink can include coating a surface of the heat sink with an anodized coating or an e-coating, for example. A portion of the coated surface can be treated via laser ablation for placing the solid state light source. Additionally, the laser ablation parameters can be adjusted to provide a predetermined roughness to the treated portion of the coated surface.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 15, 2019
    Assignee: Valeo North America, Inc.
    Inventors: Chase Rouse, Jonathan Blandin, Brian Guinn, Marc Duarte
  • Patent number: 10170771
    Abstract: The present invention provides a catalyst comprising a layer of metallic palladium implant¬ed with an inert gas ions, an electrochemical system containing thereof, a palladium-inert gas alloy stable in the normal conditions, use thereof and a fuel cell containing thereof.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: January 1, 2019
    Assignee: UNIWERSYTET WARSZAWSKI
    Inventors: Adam Lewera, Rafal Jurczakowski, Piotr Połczyński
  • Patent number: 10121646
    Abstract: In order to remove from a substrate having a concavo-convex pattern formed on a surface of the substrate, a solid material with which a concave portion of the concavo-convex pattern is filled and which is formed by evaporating a solvent in a sublimable substance solution containing a sublimable substance that sublimates at a temperature equal to or higher than a first temperature, and an impurity that evaporates at a temperature equal to or higher than a second temperature that is higher than the first temperature, the prevent invention provides a substrate processing apparatus and a substrate processing method which heat the substrate to a temperature equal to or higher than the second temperature.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 6, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Koji Kagawa, Hisashi Kawano, Meitoku Aibara, Yuki Yoshida
  • Patent number: 10068806
    Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: September 4, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David C. Pritchard, Tuhin Guha Neogi, Scott Luning, David Doman
  • Patent number: 10049817
    Abstract: The present disclosure provides advantageous composite films/coatings, and improved methods for fabricating such composite films/coatings. More particularly, the present disclosure provides improved methods for fabricating composite films by trapping at least a portion of a layered material (e.g., hexagonal boron nitride sheets/layers) at an interface of a phase separated system and then introducing the layered material to a polymer film. The present disclosure provides for the use of boron nitride layers to increase the properties (e.g., dielectric constant and breakdown voltage) of polymer films. The exemplary films can be produced by an advantageous climbing technique. Exemplary boron nitride films are composed of overlapping boron nitride sheets with a total thickness of about one nanometer, with the film then transferred onto a polymer film, thereby resulting in significant increases in both dielectric and breakdown properties of the polymer film.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: August 14, 2018
    Assignee: University of Connecticut
    Inventors: Douglas H. Adamson, Zhenhua Cui, Andrey V. Dobrynin
  • Patent number: 10008366
    Abstract: Embodiments of the present disclosure generally provide improved methods for processing substrates with improved process stability, increased mean wafers between clean, and/or improved within wafer uniformity. One embodiment provides a method for seasoning one or more chamber components in a process chamber. The method includes placing a dummy substrate in the process chamber, flowing a processing gas mixture to the process chamber to react with the dummy substrate and generate a byproduct on the dummy substrate, and annealing the dummy substrate to sublimate the byproduct while at least one purge conduit of the process chamber is closed.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: June 26, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Sang Won Kang, Nicholas Celeste, Dmitry Lubomirsky, Peter Hillman, Douglas Brenton Hayden, Dongqing Yang
  • Patent number: 10002772
    Abstract: A method is described for vapor phase etching of oxide material including at least one of hafnia (HfO2) and zirconia (ZrO2), in the absence of plasma exposure of the oxide material. The method involves contacting the oxide material with an etching medium including at least one of phosphorus chloride and tungsten chloride under conditions producing a removable fluid reaction product, and removing the removable fluid reaction product. The etching process may be controllably carried out by use of pressure swings, temperature swings, and/or modulation of partial pressure of Hf or Zr chloride in the reaction, e.g., to achieve precision etch removal in the manufacture of semiconductor devices such as 3D NAND, sub-20 nm DRAMs, and finFETs.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: June 19, 2018
    Assignee: Entegris, Inc.
    Inventor: Bryan C. Hendrix
  • Patent number: 9991179
    Abstract: Provided is a technique capable of obtaining a satisfactory yield for a semiconductor device with an air gap. The technique includes a method of manufacturing a semiconductor device, including: (a) receiving a thickness information of a wiring layer formed on a substrate including: a first interlayer insulation film; and the wiring layer disposed on the first interlayer insulation film, the wiring layer including: copper-containing films used as wiring; and an inter-wiring insulation film having trenches filled with the copper-containing films and insulating the copper-containing films; (b) placing the substrate on a substrate support installed in a process chamber; and (c) etching the wiring layer using an etching gas based on an etching control value corresponding to the thickness information of the wiring layer.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: June 5, 2018
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Naofumi Ohashi, Kazuyuki Toyoda, Satoshi Shimamoto, Toshiyuki Kikuchi
  • Patent number: 9947590
    Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: April 17, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David C. Pritchard, Tuhin Guha Neogi, Scott Luning, David Doman
  • Patent number: 9881806
    Abstract: A method of manufacturing a semiconductor device including a wafer using a plasma etching device which includes a chamber, a chuck provided in the chamber to dispose a wafer to be processed thereon, a focus ring disposed at a peripheral edge portion of the chuck, and a gas supplying mechanism configured to supply various types of gases depending a radial position of the wafer. The method includes: placing a wafer formed with an organic film on the chuck; introducing an etching gas which etches the organic film on the wafer from the process gas supplying mechanism to a central portion of the wafer; introducing an etching inhibiting factor gas having a property of reacting with the etching gas to the peripheral edge portion of the wafer from the gas supplying mechanism; and performing plasma etching on the wafer using the etching gas.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 30, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takayuki Katsunuma, Masanobu Honda, Kazuhiro Kubota, Hironobu Ichikawa
  • Patent number: 9828483
    Abstract: A microconduit network structure and methods for making the same. One aspect of the invention relates to a microconduit network structure, including: a solid or semi-solid matrix having at least one interconnected web of filaments formed within the matrix; and wherein at least one interconnected web of filaments having diameters of about 10 nm to about 1 mm.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: November 28, 2017
    Assignee: The United States of America as Represented by the Secretary of the Navy
    Inventors: Andrew J. Guenthner, David Michael Hess
  • Patent number: 9793085
    Abstract: A focused ion beam apparatus is equipped with a gas field ion source that can produce a focused ion beam for a long period of time by stably and continuously emitting ions from the gas field ion source having high luminance, along an optical axis of an ion-optical system for a long period of time. The gas field ion source has an emitter for emitting ions, the emitter having a sharpened end part made of iridium fixed to a cylinder-shaped base part made of dissimilar wire.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: October 17, 2017
    Assignee: HITACHI HIGH-TECH SCIENCE CORPORATION
    Inventors: Anto Yasaka, Tomokazu Kozakai, Osamu Matsuda, Yasuhiko Sugiyama, Kazuo Aita, Fumio Aramaki, Hiroshi Oba
  • Patent number: 9644268
    Abstract: A thermal bridge connecting first and second processing zones and a method for transferring a work piece from a first to a second processing zone by way of the thermal bridge are disclosed. A work piece, transportable from the first to the second processing zone on or above the thermal bridge, is maintained at a temperature between the temperatures of the processing zones. The thermal bridge member features a thermally conductive transport member for the work piece supported over an infrared transmissive member that is insulative to heat conduction and convection. The bridge insulative member extends between the first and second processing zones or between reactors. An infrared radiation beam source emits infrared radiation which passes through the bridge insulative member to the transport member, heating the member. In an alternate embodiment, the transport member may be heated directly. A liner member may be mounted above the bridge member to retain heat.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: May 9, 2017
    Assignee: ALTA DEVICES, INC.
    Inventors: Gregg Higashi, Khurshed Sorabji, Andreas Hegedus
  • Patent number: 9607856
    Abstract: Methods are described herein for selectively etching titanium nitride relative to dielectric films, which may include, for example, alternative metals and metal oxides lacking in titanium and/or silicon-containing films (e.g. silicon oxide, silicon carbon nitride and low-K dielectric films). The methods include a remote plasma etch formed from a chlorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium nitride. The plasma effluents react with exposed surfaces and selectively remove titanium nitride while very slowly removing the other exposed materials. The substrate processing region may also contain a plasma to facilitate breaking through any titanium oxide layer present on the titanium nitride. The plasma in the substrate processing region may be gently biased relative to the substrate to enhance removal rate of the titanium oxide layer.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: March 28, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Anchuan Wang, Nitin K. Ingle, Dmitry Lubomirsky
  • Patent number: 9530671
    Abstract: An etching method for etching an object to be processed in a processing chamber including a first electrode and a second electrode disposed facing the first electrode and configured to receive the object to be processed thereon is provided that includes steps of intermittently supplying first high frequency power to either the first electrode or the second electrode while supplying second high frequency power lower than the first high frequency power to the second electrode, supplying a process gas containing hydrogen bromide HBr and oxygen O2 into the processing chamber, and etching a poly silicon film deposited on the object to be processed into a mask pattern of a silicon-containing oxide film patterned by a spacer double patterning method by plasma generated from the process gas.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: December 27, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Yoichi Nakahara
  • Patent number: 9337056
    Abstract: A semiconductor device manufacturing method for etching a multilayer film using a mask is provided. The method includes (a) supplying a first gas containing hydrogen, hydrogen bromide, nitrogen trifluoride and at least one of hydrocarbon, fluorocarbon and fluorohydrocarbon into the processing chamber and exciting the first gas to etch the multilayer film from a top surface of the multilayer film to a predetermined position in a stacked direction of the multilayer film; and (b) supplying a second gas that does not substantially contain hydrogen bromide and contains hydrogen and nitrogen trifluoride and at least one of Thydrocarbon, fluorocarbon and fluorohydrocarbon into the processing chamber and exciting the second gas to etch the multilayer film from the predetermined position of the multilayer film to a top surface of the etching stop layer.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: May 10, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Rui Takahashi, Ryuuu Ishita, Kazuki Narishige
  • Patent number: 9269479
    Abstract: Cable foil tape having random or pseudo-random patterns or long pattern lengths of discontinuous metallic shapes and a method for manufacturing such patterned foil tape are provided. In some embodiments, a laser ablation system is used to selectively remove regions or paths in a metallic layer of a foil tape to produce random distributions of randomized shapes, or pseudo-random patterns or long pattern lengths of discontinuous shapes in the metal layer. In some embodiments, the foil tape is double-sided, having a metallic layer on each side of the foil tape, and the laser ablation system is capable of ablating nonconductive pathways into the metallic layer on both sides of the foil tape.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: February 23, 2016
    Assignee: Panduit Corp.
    Inventors: Royal O. Jenner, Timothy J. Houghton, II, Masud Bolouri-Saransar, Ronald A. Nordin
  • Patent number: 9269572
    Abstract: A method for manufacturing a silicon carbide semiconductor substrate is provided to offer a silicon carbide semiconductor substrate having a highly flat surface at low cost. The method includes: a step of preparing a silicon carbide substrate as a seed substrate; a step of performing vapor phase etching onto a main surface of the silicon carbide substrate; and a step of epitaxially growing silicon carbide on the main surface. A carbon-atom containing gas is supplied to silicon carbide substrate from a point of time in the step of performing the vapor phase etching.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: February 23, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Jun Genba
  • Patent number: 9263239
    Abstract: Verticality of a space formed in the multilayered film can be improved while suppressing an opening of a mask from being clogged. The multilayered film includes a first film and a second film that have different permittivities and are alternately stacked on top of each other. An etching method of etching the multilayered film includes preparing, within a processing vessel of a plasma processing apparatus, a processing target object having the multilayered film and a mask provided on the multilayered film; and etching the multilayered film by exciting a processing gas containing a hydrogen gas, a hydrofluorocarbon gas, a fluorine-containing gas, a hydrocarbon gas, a boron trichloride gas and a nitrogen gas within the processing vessel.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: February 16, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yusuke Saitoh, Ryuuu Ishita
  • Patent number: 9250514
    Abstract: An apparatus and methods utilized a DC or AC power to supply through a conductive substrate support pedestal to a conductive photomask substrate during a photomask substrate manufacturing process for EUV or other advanced lithography applications are provided. In one embodiment, an apparatus for processing a photomask includes a substrate support pedestal configured to receive a conductive photomask, wherein the conductive photomask is fabricated from a dielectric material substrate with a conductive coating, and at least a conductive path formed in the substrate support pedestal in contact with the photomask substrate configured to be conductive.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: February 2, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Banqiu Wu, Ajay Kumar
  • Patent number: 9238257
    Abstract: It is possible to efficiently remove deposited materials such as a conductive film or insulting film adhered to parts such as the inner wall of a processing chamber and a substrate supporting tool disposed in the processing chamber. There is provided a method of manufacturing a semiconductor device. The method comprises: loading a substrate into a processing chamber; forming a conductive film or an insulating film on the substrate by supplying a plurality of source gases into the processing chamber; unloading the substrate from the processing chamber; and modifying a conductive film or an insulating film adhered to the processing chamber by supplying a modifying gas into the processing chamber. After performing a cycle of the loading, the forming, the unloading, and the modifying processes a plurality of times, the modified conductive film or the modified insulating film adhered to the processing chamber is removed from the processing chamber by supplying a cleaning gas into the processing chamber.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: January 19, 2016
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Masanori Sakai, Yukinao Kaga, Takashi Yokogawa, Tatsuyuki Saito
  • Patent number: 9174422
    Abstract: A microconduit network structure and methods for making the same. One aspect of the invention relates to a microconduit network structure, including: a solid or semi-solid matrix having at least one interconnected web of filaments formed within the matrix; and wherein at least one interconnected web of filaments having diameters of about 10 nm to about 1 mm.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: November 3, 2015
    Assignee: The United States of America as Represented by the Secretary of the Navy
    Inventors: Andrew J. Guenthner, David M Hess
  • Patent number: 9177816
    Abstract: One embodiment of the deposit removal method includes: preparing a substrate having a pattern on which a deposit is deposited, the pattern being formed by etching; exposing the substrate to a first atmosphere containing hydrogen fluoride gas; exposing the substrate to oxygen plasma while heating after the step of exposing the substrate to the first atmosphere; and exposing the substrate to a second atmosphere containing hydrogen fluoride gas to remove the deposit on the substrate after the step of exposing the substrate to the oxygen plasma.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: November 3, 2015
    Assignees: TOKYO ELECTRON LIMITED, KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigeru Tahara, Eiichi Nishimura, Takanori Matsumoto
  • Patent number: 9128117
    Abstract: A method for sharpening a nanotip involving a laser-enhanced chemical etching is provided. The method includes immersing a nanotip in an etchant solution. The nanotip includes a base and an apex, the apex having a diameter smaller than a diameter of the base. The method also includes irradiating the nanotip with laser fluence to establish a temperature gradient in the nanotip along a direction from the apex to the base of the nanotip such that the apex and base are etched at different rates.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: September 8, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: ZhiHong Mai, Jeffrey C. Lam, Mohammed Khalid Bin Dawood, Tsu Hau Ng
  • Patent number: 9126229
    Abstract: A deposit removal method for removing deposits deposited on the surface of a pattern formed on a substrate by etching, includes an oxygen plasma treatment process for exposing the substrate to oxygen plasma while heating the substrate and a cycle treatment process for, after the oxygen plasma treatment process, repeating multiple cycles of a first period and a second period. In the first period, the substrate is exposed to a mixture of hydrogen fluoride gas and alcohol gas inside a processing chamber and the partial pressure of the alcohol gas is set to the first partial pressure. In the second period, the partial pressure of the alcohol gas is set to the second partial pressure lower than the first partial pressure by exhausting the inside of the processing chamber.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: September 8, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shigeru Tahara, Eiichi Nishimura, Hiroshi Tomita, Tokuhisa Ohiwa, Hisashi Okuchi, Mitsuhiro Omura
  • Patent number: 9082796
    Abstract: A processing device for processing stacked processed goods for the production of conducting, semiconducting, or insulating thin layers includes, in at least one embodiment, an evacuatable process chamber configured to receive a process gas. A tempering device keeps at least a partial region of a wall of the evacuatable process chamber at a predetermined first temperature during at least part of the processing. The first temperature is between a second temperature that is room temperature and a third temperature, generated in the evacuatable process chamber, that is above room temperature. A heated gas flow cycle flows through a gas guiding device in the evacuatable process chamber. The stacked processed goods are insertable through a lockable loading opening into the gas guiding device, and a gas inlet device feeds the process gas into the gas flow cycle. A process system may further include a cooling device and/or a channeling device.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: July 14, 2015
    Inventor: Volker Probst
  • Patent number: 9039909
    Abstract: There is provided a plasma etching method for forming a hole in a silicon oxide film formed on an etching stopper layer. The plasma etching method includes a main etching process for etching the silicon oxide film; and an etching process that is performed when at least a part of the etching stopper layer is exposed after the main etching process. The etching process includes a first etching process using a gaseous mixture of a C4F6 gas, an Ar gas and an O2 gas as the processing gas; and a second etching process using a gaseous mixture of a C4F8 gas, an Ar gas and an O2 gas or a gaseous mixture of a C3F8 gas, an Ar gas and an O2 gas as the processing gas. The first etching process and the second etching process are alternately performed plural times.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: May 26, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Nakagawa, Yuji Otsuka
  • Patent number: 9034199
    Abstract: A machined ceramic article having an initial surface defect density and an initial surface roughness is provided. The machined ceramic article is heated to a temperature range between about 1000° C. and about 1800° C. at a ramping rate of about 0.1° C. per minute to about 20° C. per minute. The machined ceramic article is heat-treated in air atmosphere. The machined ceramic article is heat treated at one or more temperatures within the temperature range for a duration of up to about 24 hours. The machined ceramic article is then cooled at the ramping rate, wherein after the heat treatment the machined ceramic article has a reduced surface defect density and a reduced surface roughness.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: May 19, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Ren-Guan Duan, Thorsten Lill, Jennifer Y. Sun, Benjamin Schwarz
  • Patent number: 9029264
    Abstract: Methods of depositing a tin-containing layer on a substrate are disclosed herein. In some embodiments, a method of depositing a tin-containing layer on a substrate may include flowing a tin source comprising a tin halide into a reaction volume; flowing a hydrogen plasma into the reaction volume; forming one or more tin hydrides within the reaction volume from the tin source and the hydrogen plasma; and depositing the tin-containing layer on a first surface of the substrate using the one or more tin hydrides.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 12, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Errol Antonio C. Sanchez, Yi-Chiau Huang
  • Patent number: 9023218
    Abstract: Methods of fabricating the fusible link are directed to processing a multi-layer clad foil having a first layer suitable for forming a fusible link and a second layer suitable for forming one or more welding tabs. In some embodiments, the first layer is an aluminum layer and the second layer is a nickel layer. A two-step etching process or a single step etching process is performed on the clad foil to form an etched clad foil having multiple tabs made of the second layer and connected to the current collector conductor pads and battery cell conductor pads, and one or more connections made of the first layer that form aluminum conductors. The aluminum conductors are shaped and sized to form aluminum fusible conductors during either the etching process or a subsequent stamping process. A single fusible link or an array of fusible links can be formed.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: May 5, 2015
    Assignee: SinoElectric Powertrain Corporation
    Inventors: Peng Zhou, Paul Tsao
  • Patent number: 9023222
    Abstract: According to one embodiment, a pattern forming method includes forming a first guide layer on a processed film, phase-separating a first self-assembly material with the use of the first guide layer to form a first self-assembly pattern including a first polymer portion and a second polymer portion, selectively removing the first polymer portion, forming a second guide layer with the use of the second polymer portion, and phase-separating a second self-assembly material with the use of the second guide layer to form a second self-assembly pattern including a third polymer portion and a fourth polymer portion.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ayako Kawanishi, Shinichi Ito, Hirokazu Kato, Shimon Maeda, Hideki Kanai
  • Patent number: 9023225
    Abstract: A pattern forming method includes forming a pattern forming material film on a substrate as an etching target film, the pattern forming material film having an exposing section that has porosity upon exposure and a non-exposing section, patterning and exposing the pattern forming material film for the exposing section to have the porosity, selectively infiltrating a filling material into voids of the exposing section to reinforce the exposing section, and removing the non-exposing section of the pattern forming material film by dry etching to form a predetermined pattern.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 5, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Kenichi Oyama, Hidetami Yaegashi
  • Publication number: 20150118625
    Abstract: Provided herein is a method, including a) transferring an initial pattern of an initial template to a substrate; b) performing block copolymer self-assembly over the substrate with a density multiplication factor k; c) creating a subsequent pattern in a subsequent template with the density multiplication factor k; and d) repeating steps a)-c) with the subsequent template as the initial template until a design specification for the subsequent pattern with respect to pattern density and pattern resolution is met.
    Type: Application
    Filed: January 2, 2015
    Publication date: April 30, 2015
    Inventors: XiaoMin Yang, Zhaoning Yu, Kim Yang Lee, Michael Feldbaum, Yautzong Hsu, Wei Hu, Shuaigang Xiao, Henry Yang, HongYing Wang, Rene Johannes Marinus van de Veerdonk, David Kuo
  • Patent number: 9017564
    Abstract: A plasma etching method performs plasma etching on a sample, which has laminated films containing a variable layer of a magnetic film, a barrier layer of an insulating material, and a fixed layer of a magnetic film, using a hard mask, which includes at least one of a Ta film and a TiN film. The plasma etching method includes a first step of etching the laminated films using N2 gas; and a second step of etching the laminated films after the first step using mixed gas of N2 gas and gas containing carbon elements.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: April 28, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Atsushi Yoshida, Naohiro Yamamoto, Makoto Suyama, Kentaro Yamada, Daisuke Fujita