By Electrical Means Or Of An Electrical Property Patents (Class 216/86)
  • Patent number: 11923580
    Abstract: Stainless steel for a fuel cell separator plate and a manufacturing method therefor are disclosed. The stainless steel for a fuel cell separator plate, according to one embodiment of the present invention, comprises: a stainless base material; and a passive film formed on the stainless base material, wherein a Cr/Fe atomic weight ratio in a 1 nm or less thickness region of the stainless base material, which is adjacent to an interface between the stainless and the passive film, is 0.45 or more. Therefore, by modifying the surface of the stainless steel for a fuel cell separator plate, a low interface contact resistance and a good corrosion resistance can be obtained, and a separate additional process such as precious metal coating can be removed, such that manufacturing costs are reduced and productivity can be improved.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: March 5, 2024
    Assignee: POSCO CO., LTD
    Inventors: Kwang Min Kim, Jong Hee Kim, Ki Hoon Jo, Bo Sung Seo
  • Patent number: 11037795
    Abstract: Techniques for planarization of dielectric topography that stop in dielectric are provided. In one aspect, a method for planarization includes: depositing a first dielectric onto a wafer having a surface topography with peaks and valleys; depositing a second, different dielectric onto the first dielectric; and polishing the second dielectric down to the first dielectric to form a planar surface at an interface between the first dielectric and the second dielectric. Optionally, a follow-up CMP or etch can be performed using a ˜1:1 selective polish or etch to completely remove the second dielectric and an equivalent amount of the first dielectric to form a planar surface devoid of the peaks and valleys in the first dielectric. A device structure formed by the present techniques is also provided.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Hari Prasad Amanapu, Cornelius Brown Peethala, Iqbal Rashid Saraf, Raghuveer Reddy Patlolla, Chih-Chao Yang
  • Patent number: 10468274
    Abstract: The substrate processing apparatus includes a processing chamber including an outer chamber configured to hold a processing liquid and an inner chamber capable of surrounding the substrate held by the substrate holder; a liquid delivery pipe having one end coupled to a bottom of the inner chamber and other end coupled to the outer chamber; a pump configured to suck the processing liquid from the inner chamber through the liquid delivery pipe and to deliver the processing liquid to the outer chamber through the liquid delivery pipe; and a guide cover having a through-hole in which the substrate holder can be inserted. The guide cover is located below an upper end of the outer chamber and above the inner chamber.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: November 5, 2019
    Assignee: EBARA CORPORATION
    Inventors: Keiichi Kurashina, Toshio Yokoyama
  • Patent number: 10256075
    Abstract: Techniques are disclosed for methods and apparatuses for delivering process gas for processing a substrate. In one embodiment, the method begins by injecting process gas into a processing chamber proximate an edge of a substrate disposed in the processing chamber from a first location. The method then continues by way of injecting the process gas into the processing chamber proximate the edge of the substrate disposed in the processing chamber from a second location while no gas is injected from the first location. Finally, the method finishes by way of processing the substrate in the presence of the processing gas injected from the first and second location.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: April 9, 2019
    Assignee: Applied Materials, Inc.
    Inventor: James Rogers
  • Patent number: 9812573
    Abstract: A method includes providing a semiconductor structure including a substrate, a gate structure over the substrate and a sidewall spacer adjacent the gate structure. The substrate includes a first semiconductor material. A substantially isotropic first etch process removing the first semiconductor material is performed. The first etch process forms an undercut below the sidewall spacer. An anisotropic second etch process removing the first semiconductor material is performed, wherein an etch rate in a thickness direction of the substrate is greater than an etch rate in a horizontal direction that is perpendicular to the thickness direction. A crystallographic third etch process removing the first semiconductor material is performed, wherein an etch rate in a first crystal direction is greater than an etch rate in a second crystal direction. The first, second and third etch processes form a source-side recess and a drain-side recess adjacent the gate structure.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: November 7, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Arkadiusz Malinowski, Chung Foong Tan, Nicolas Sassiat, Maciej Wiatr
  • Patent number: 9676075
    Abstract: Various particular embodiments include a method for controlling chemical mechanical polishing, including: polishing a semiconductor wafer in a chemical mechanical polishing (CMP) tool; measuring a resistance of a resistive pathway through the semiconductor wafer while the semiconductor wafer is undergoing polishing in the CMP tool; and terminating the polishing of the semiconductor wafer when the measured resistance reaches a target resistance.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: June 13, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Laertis Economikos, Elliott P. Rill
  • Patent number: 9227294
    Abstract: An apparatus for chemical mechanical polishing includes a wafer carrier, a first electrode, a rotatable pedestal, a second electrode, and an electric current detector. The first electrode is disposed at the wafer carrier. The rotatable pedestal is positioned opposite to the wafer carrier in order to perform a polishing operation with the wafer carrier accordingly. The second electrode is disposed at the rotatable pedestal and electrically coupled to the first electrode in order to form a circuit loop. The electric current detector is between the first electrode and the second electrode.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: January 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Liang Cheng, Yen-Yu Chen, Chang-Sheng Lee, Wei Zhang
  • Patent number: 9017563
    Abstract: Provided is a plating method of a circuit substrate comprising a conductive pattern in which a metal layer containing at least silver and copper is exposed on an outer surface. The plating method comprises: step (A) of treating the circuit substrate with a first liquid agent containing an oxidizing agent; step (B) of treating the circuit substrate after the step (A) with a second liquid agent which dissolves copper oxide, and thereby removing copper oxide from the conductive pattern's surface; step (C) of treating the circuit substrate after the step (B) with a third liquid agent whose rate of dissolving silver oxide (I) at 25° C. is 1000 times or more faster than its rate of dissolving copper (0) at 25° C., and thereby removing silver oxide from the conductive pattern's surface; and step (D) of performing electroless plating on the conductive pattern of the circuit substrate after the step (C).
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: April 28, 2015
    Assignee: Tokuyama Corporation
    Inventors: Emi Ushioda, Tetsuo Imai
  • Patent number: 8956977
    Abstract: The present invention provides a semiconductor device production method and a rinse used in the production method. The method includes: a sealing composition application process in which a semiconductor sealing layer is formed by applying, to at least a portion of a surface of a semiconductor substrate, a semiconductor sealing composition that includes a resin having a cationic functional group and a weight average molecular weight of from 2,000 to 600,000, wherein a content of sodium and a content of potassium are 10 mass ppb or less on an elemental basis, respectively; and, subsequently, a rinsing process in which the surface of the semiconductor substrate on which the semiconductor sealing layer has been formed is rinsed with a rinse having a pH at 25° C. of 6 or lower.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: February 17, 2015
    Assignee: Mitsu Chemicals, Inc.
    Inventors: Shoko Ono, Kazuo Kohmura, Hirofumi Tanaka
  • Patent number: 8920625
    Abstract: Provided is a particle that includes a first porous region and a second porous region that differs from the first porous region. Also provided is a particle that has a wet etched porous region and that does have a nucleation layer associated with wet etching. Methods of making porous particles are also provided.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: December 30, 2014
    Assignees: Board of Regents of the University of Texas System, The Ohio State University Research Foundation
    Inventors: Mauro Ferrari, Xuewu Liu, Ming-Cheng Cheng
  • Patent number: 8858817
    Abstract: A polishing apparatus and exception handling method thereof is disclosed, the exception handling method of polishing apparatus includes: sending an alarm signal when an alarm is generated because of an exception during polishing; and processing a wafer in the polishing apparatus with organic acid solution according to the received alarm signal. The method and apparatus prevent the metal material from corrosion which causes device failure, when there is an alarm generated because of an exception which stops the apparatus during polishing.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Li Jiang, Mingqi Li
  • Patent number: 8845914
    Abstract: The presence of a detectable entity within a detection volume of a microfabricated elastomeric structure is sensed through a change in the electrical or magnetic environment of the detection volume. In embodiments utilizing electronic detection, an electric field is applied to the detection volume and a change in impedance, current, or combined impedance and current due to the presence of the detectable entity is measured. In embodiments utilizing magnetic detection, the magnetic properties of a magnetized detected entity alter the magnetic field of the detection volume. This changed magnetic field induces a current which can reveal the detectable entity. The change in resistance of a magnetoresistive element may also reveal the passage of a magnetized detectable entity.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: September 30, 2014
    Assignee: Fluidigm Corporation
    Inventors: Hany Nassef, Geoffrey Richard Facer, Marc Unger
  • Patent number: 8828259
    Abstract: A method for automatically performing power matching using a mechanical RF match during substrate processing is provided. The method includes providing a plurality of parameters for the substrate processing wherein the plurality of parameters including at least a predefined number of learning cycles. The method also includes setting the mechanical RF match to operate in a mechanical tuning mode. The method further includes providing a first set of instructions to the substrate processing to ignore a predefined number of cycles of Rapid Alternating Process RAP steps. The method yet also includes operating the mechanical RF match in the mechanical tuning mode for the predefined number of learning cycles. The method yet further includes determining a set of optimal capacitor values. The method moreover includes providing a second set of instructions to a power generator to operate in a frequency tuning mode.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: September 9, 2014
    Assignee: Lam Research Corporation
    Inventor: Arthur H. Sato
  • Patent number: 8569174
    Abstract: Methods of determining a polishing endpoint are described using spectra obtained during a polishing sequence. In particular, techniques for using only desired spectra, faster searching methods and more robust rate determination methods are described.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: October 29, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Harry Q. Lee, Boguslaw A. Swedek, Dominic J. Benvegnu, Jeffrey Drue David
  • Patent number: 8440093
    Abstract: The presence of a detectable entity within a detection volume of a microfabricated elastomeric structure is sensed through a change in the electrical or magnetic environment of the detection volume. In embodiments utilizing electronic detection, an electric field is applied to the detection volume and a change in impedance, current, or combined impedance and current due to the presence of the detectable entity is measured. In embodiments utilizing magnetic detection, the magnetic properties of a magnetized detected entity alter the magnetic field of the detection volume. This changed magnetic field induces a current which can reveal the detectable entity. The change in resistance of a magnetoresistive element may also reveal the passage of a magnetized detectable entity.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: May 14, 2013
    Assignee: Fuidigm Corporation
    Inventors: Hany Nassef, Geoff Facer, Marc Unger
  • Patent number: 8419962
    Abstract: A method of the present invention comprises: preparing the first substrate comprising a surface with a first recess and a second recess of which a bottom comprises a first electrode; immersing the first substrate into a electrolyte solution; inserting a second electrode into the electrolyte solution; injecting a bubble into the electrolyte solution with applying a voltage between the first and the second electrodes to dispose the bubble onto only the first recess; dispersing the first microstructure into the electrolyte solution to dispose it onto the first recess; injecting the bubble into the electrolyte solution to dispose the bubble onto the second recess; and dispersing the second microstructure into the electrolyte solution to dispose it onto the second recess.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: April 16, 2013
    Assignee: Panasonic Corporation
    Inventor: Tohru Nakagawa
  • Patent number: 8383003
    Abstract: Described herein are polishing apparatus, polishing formulations, and polymeric substrates for use in polishing surfaces, and related methods. The apparatus, formulations, substrates, and methods may each be used in applications involving the polishing of metal and/or metal-containing surfaces such as semiconductor wafers. The apparatus, formulations, polymeric substrates, and related methods described herein may be used without abrasives, and in some instances, without mechanical friction of a pad surface against the surface to be polished. Therefore, defects on a polished surface due to such mechanical polishing processes may be reduced.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: February 26, 2013
    Assignee: NexPlanar Corporation
    Inventor: Sudhanshu Misra
  • Publication number: 20130008871
    Abstract: A method for automatically performing power matching using a mechanical RF match during substrate processing is provided. The method includes providing a plurality of parameters for the substrate processing wherein the plurality of parameters including at least a predefined number of learning cycles. The method also includes setting the mechanical RF match to operate in a mechanical tuning mode. The method further includes providing a first set of instructions to the substrate processing to ignore a predefined number of cycles of Rapid Alternating Process RAP steps. The method yet also includes operating the mechanical RF match in the mechanical tuning mode for the predefined number of learning cycles. The method yet further includes determining a set of optimal capacitor values. The method moreover includes providing a second set of instructions to a power generator to operate in a frequency tuning mode.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 10, 2013
    Inventor: Arthur H. Sato
  • Publication number: 20130001198
    Abstract: An electroplating apparatus including a reference electrode to control the potential during an electro-deposition process. The electroplating apparatus may include a bath containing a plating electrolyte and an anode present in a first portion of the bath containing the plating electrolyte. A cathode is present in a second portion of the bath containing the plating electrolyte. A reference electrode is present at a perimeter of the cathode. The electroplating apparatus also includes a control system to bias the cathode and the anode to provide a potential. A measuring system is provided in electrical communication with the reference electrode to measure the potential of the cathode. Methods of using the above described electroplating apparatus are also provided. Structures and method for electroless deposition are also provided.
    Type: Application
    Filed: September 10, 2012
    Publication date: January 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Harry Cox, Hariklia Deligianni, George J. Scott
  • Publication number: 20120043301
    Abstract: An electroplating apparatus including a reference electrode to control the potential during an electro-deposition process. The electroplating apparatus may include a bath containing a plating electrolyte and an anode present in a first portion of the bath containing the plating electrolyte. A cathode is present in a second portion of the bath containing the plating electrolyte. A reference electrode is present at a perimeter of the cathode. The electroplating apparatus also includes a control system to bias the cathode and the anode to provide a potential. A measuring system is provided in electrical communication with the reference electrode to measure the potential of the cathode. Methods of using the above described electroplating apparatus are also provided. Structures and method for electroless deposition are also provided.
    Type: Application
    Filed: August 19, 2010
    Publication date: February 23, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Harry Cox, Hariklia Deligianni, George J. Scott
  • Patent number: 7901588
    Abstract: An etching process is employed to selectively pattern the top magnetic film layer, the tunnel barrier, and the pinned bottom magnetic layer of a magnetic thin film structure. The pinned bottom magnetic film layer has an antiferromagnetic layer or a Ru spacer formed thereunder. The etching process employs various etching steps that selectively remove various layers of the magnetic thin film structure stopping on the antiferromagnetic layer or the Ru spacer. The progress of this etching process can be monitored by measuring the electrochemical potential difference of a part or wafer containing a magnetic structure with respect to a reference electrode simultaneously with the selective etching process.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Eugene J. O'Sullivan, Daniel Worledge
  • Patent number: 7892442
    Abstract: A method of manufacturing a thin-film magnetic head works a part to be worked to a target length by carrying out an etching process on an object to be worked using an etching apparatus.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: February 22, 2011
    Assignee: TDK Corporation
    Inventors: Hiroo Sawada, Jun Shouji, Mitsuhiro Kitao, Eiji Yamada
  • Patent number: 7887713
    Abstract: A method includes forming a first electrode and a second electrode on a base body. The Method also includes chemically etching at least a portion of the base body to adjust a resistance of the base body measured between the first electrode and the second electrodes to a predetermined value.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: February 15, 2011
    Assignee: EPCOS AG
    Inventor: Christian Hesse
  • Patent number: 7808253
    Abstract: It is an object to provide a test method of a process, an electric characteristic, and a mechanical characteristic of a structure body in a micromachine without contact. A structure body including a first conductive layer, a second conductive layer provided in parallel to the first conductive layer, and a sacrifice layer or a space provided between the first conductive layer and the second conductive layer is provided; an antenna connected to the structure body is provided; electric power is supplied to the structure body wirelessly through the antenna; and an electromagnetic wave generated from the antenna is detected as a characteristic of the structure body.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: October 5, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mayumi Yamaguchi, Konami Izumi, Fuminori Tateishi
  • Publication number: 20100029080
    Abstract: Aqueous cerium oxide dispersion Aqueous cerium oxide dispersion, containing 5 to 60% by weight cerium oxide. It can be used to polish SiO2 in the semiconductor industry.
    Type: Application
    Filed: March 8, 2006
    Publication date: February 4, 2010
    Inventors: Michael Kröll, Stefan Heberer, Stipan Katusic, Michael Krämer, Wolfgand Lortz
  • Patent number: 7625495
    Abstract: Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of planarizing a microelectronic substrate assembly in accordance with the invention includes pressing a substrate assembly against a planarizing surface of a polishing pad at a pad/substrate interface defined by a surface area of the substrate assembly contacting the planarizing surface. The method continues by moving the substrate assembly and/or the polishing pad with respect to the other to rub at least one of the substrate assembly and the planarizing surface against the other at a relative velocity. As the substrate assembly and polishing pad rub against each other, a parameter indicative of drag force between the substrate assembly and the polishing pad is measured or sensed at periodic intervals.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: December 1, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Jim Hofmann, Gundu M. Sabde, Stephen J. Kramer, Scott E. Moore
  • Patent number: 7622052
    Abstract: Methods are provided for chemical mechanical planarization of a layer and for determining the endpoint of a CMP operation. In accordance with one embodiment the method for determining an endpoint comprises making a plurality of eddy current thickness measurement of the layer being planarized, each of the plurality of measurements spaced apart by a predetermined length of time. A difference is calculated between sequential ones of the plurality of eddy current measurements, and a predetermined minimum threshold for the difference is set. The endpoint is defined as a calculated difference less than the predetermined minimum threshold.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: November 24, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Justin Quarantello, Thomas Laursen, Karl Kasprzyk, Rob Stoya
  • Publication number: 20090179008
    Abstract: A substrate treating apparatus for treating substrates with a treating solution having a mixture of a chemical and a diluent.
    Type: Application
    Filed: March 11, 2009
    Publication date: July 16, 2009
    Inventor: Hiroaki Takahashi
  • Patent number: 7371686
    Abstract: A method and an apparatus for polishing a semiconductor wafer are provided. An initial thickness of the semiconductor wafer is actually measured to obtain a measured initial thickness value. First and second inter-positions are then set or determined with reference to the measured initial thickness value. The first and second inter-positions are predetermined taking into account any variation in the initial thickness of the semiconductor wafer. A polishing process is carried out under control to a motion of a polishing pad toward a stage, on which the semiconductor pad is held.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: May 13, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kentarou Arai
  • Patent number: 7165560
    Abstract: In order to reliably remove, by wet etching, a compound containing a metal and silicon, e.g., a silicate (101a) containing hafnium metal, the silicate (101a) is oxidized and then the oxidized silicate (101a) is wet-etched.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: January 23, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Shinji Fujii
  • Patent number: 7011762
    Abstract: One aspect of the present invention relates to a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. Another aspect of the present relates to a system and method for monitoring a subtractive metallization process in real time in order to effectuate an immediate response in the on-going process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: March 14, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher F. Lyons, Ramkumar Subramanian, Steven C. Avanzino
  • Patent number: 6995091
    Abstract: The invention relates to a process for chemically mechanically polishing and grinding wafers. The CMP slurry that is used for grinding is analyzed using slurry atomic absorption spectroscopy. This allows rapid and sensitive analysis of the slurry constituents, in particular of interfering ions. The process can be automated and makes it possible to process wafers with a constant quality. Furthermore, rapid fault analysis or optimization of the process parameters used during the grinding is possible.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: February 7, 2006
    Assignee: Infineon Technologies AG
    Inventor: Germar Schneider
  • Patent number: 6952014
    Abstract: A Focused Ion Beam (FIB) milling end-point detection system uses a constant current power supply to energize an Integrated Circuit (IC) that is to be modified. The FIB is cycled over a conductive trace that is to be accessed during the milling process. The input power, or voltage to the IC is monitored during the milling process. The end-point can be detected when the FIB reaches the conductive trace. The FIB can inject charge onto the conductive trace when the FIB reaches the level of the conductive trace. An active device coupled to the conductive trace can amplify the charge injected by the FIB. The active device can operate as a current amplifier. The change in IC current can result in an amplified change in device input voltage. The end-point can be detected by monitoring the change in input voltage from the constant current power supply.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: October 4, 2005
    Assignee: Qualcomm Inc
    Inventor: Alan Glen Street
  • Patent number: 6951624
    Abstract: A system for processing a wafer is provided. The system includes a chemical mechanical planarization (CMP) tool. The CMP tool includes a wafer carrier defined within a housing. A carrier film is affixed to the bottom surface and supports a wafer. A sensor embedded in the wafer carrier. The sensor is configured to induce an eddy current in the wafer to determine a proximity and a thickness of the wafer. A sensor array external to the CMP tool is included. The sensor array is in communication with the sensor embedded in the wafer carrier and substantially eliminates a distance sensitivity. The sensor array provides an initial thickness of the wafer to allow for a calibration to be performed on the sensor embedded in the wafer carrier. The calibration offsets variables causing inaccuracies in the determination of the thickness of the wafer during CMP operation. A method and an apparatus are also provided.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: October 4, 2005
    Assignee: Lam Research Corporation
    Inventors: Yehiel Gotkis, Rodney Kistler, Aleksander Owczarz, David Hemker, Nicolas J. Bright
  • Patent number: 6858538
    Abstract: Methods and devices for mechanical and/or chemical-mechanical polarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of plagiarizing a micro electronic substrate assembly in accordance with the invention includes pressing a substrate assembly against a plagiarizing surface of a polishing pad at a pad/substrate interface defined by a surface area of the substrate assembly contacting the plagiarizing surface. The method continues by moving the substrate assembly and/or the polishing pad with respect to the other to rub at least one of the substrate assembly and the plagiarizing surface against the other at a relative velocity. As the substrate assembly and polishing pad rub against each other, a parameter indicative of drag force between the substrate assembly and the polishing pad is measured or sensed at periodic intervals.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: February 22, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Jim Hofmann, Gundu M. Sabde, Stephen J. Kramer, Scott E. Moore
  • Patent number: 6843927
    Abstract: Techniques for detecting endpoints during semiconductor dry-etching processes are described. The dry-etching process of the present invention involves using a combination of a reactive material and a charged particle beam, such as an electron beam. In another embodiment, a photon beam is used to facilitate the etching process. The endpoint detection techniques involve monitoring the emission levels of secondary electrons and backscatter electrons together with the current within the sample. Depending upon the weight given to each of these parameters, an endpoint is identified when the values of these parameters change more than a certain percentage, relative to an initial value for these values.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: January 18, 2005
    Assignee: KLA-Tencor Technologies Corporation
    Inventor: Mehran Naser-Ghodsi
  • Publication number: 20040173575
    Abstract: Micro devices are formed in situ in a high density in a substrate comprising a masked silicon layer over a stop layer of a silicon compound, by anisotropically etching the desired feature in the silicon layer, overetching to form a notch at the silicon-stop layer interface, depositing a protective fluorocarbon polymer layer on the sidewalls and bottom of the etched silicon layer, and isotropically etching to separate the etched feature from the stop layer. This method avoids the problems of stiction common in other methods of forming micro devices.
    Type: Application
    Filed: March 5, 2003
    Publication date: September 9, 2004
    Inventors: Ajay Kumar, Anisul H. Khan, Sanjay M. Thekdi, Sharma V. Pamarthy
  • Patent number: 6750152
    Abstract: A semiconductor wafer is etched to create an array of MEMS devices and at the same time, test sites having geometry which represent critical geometry of the MEMS devices. Probe contacts are provided in the test sites to permit measurement of resistance and capacitance between test site geometry as a way of determining the effectiveness of the etch. One test site comprises a ladder of semiconductor structures separated by gaps of graded width. Another test site comprises finger structures formed over a cavity and the probe contacts are located so as to detect inter-finger capacitance and resistance (or continuity) as well as intra-finger resistance.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: June 15, 2004
    Assignee: Delphi Technologies, Inc.
    Inventors: John Carl Christenson, Steven Edward Staller, John Emmett Freeman, Troy Allan Chase, Robert Lawrence Healton
  • Publication number: 20040079729
    Abstract: A process for etching a metal layer. First, a semiconducting substrate having a metal layer and an anti-reflective layer thereon is provided. Next, the surface of the anti-reflective layer is treated with a weak base aqueous solution. Next, a photoresist layer is formed on the treated anti-reflective layer and then patterned. Next, the treated anti-reflective layer and metal layer are etched using the photoresist pattern as a mask. Finally, the photoresist pattern and anti-reflective layer are removed. The present invention prevents undercut and collapse of photoresist pattern, thus obtaining an accurate metal layer pattern.
    Type: Application
    Filed: February 27, 2003
    Publication date: April 29, 2004
    Applicant: Nanya Technology Corporation
    Inventors: Yi-Nan Chen, Wen-Bin Wu, Teng-Yen Huang, Chun-Cheng Liao, Yuan-Hsun Wu, Hung Wen Lin
  • Patent number: 6727107
    Abstract: A method of testing the processing of a wafer on a CMP apparatus includes processing a control wafer with the CMP apparatus with a predetermined control consumable combination under a predetermined set of control conditions and generating a control data set which describes the processing of the control wafer with the CMP apparatus, the control data set being based upon the control conditions and a removable rate of the control wafer. The method further includes processing a test wafer with a CMP apparatus with a test consumable combination substantially the same as the control consumable combination under a set of test conditions substantially the same as the set of control conditions. The method further includes generating a test data set which describes the processing of the test wafer with the CMP apparatus.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: April 27, 2004
    Assignee: LSI Logic Corporation
    Inventors: Samuel V. Dunton, Ron Nagahara, Pepito C. Galvez
  • Patent number: 6720266
    Abstract: Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of planarizing a microelectronic substrate assembly in accordance with the invention includes pressing a substrate assembly against a planarizing surface of a polishing pad at a pad/substrate interface defined by a surface area of the substrate assembly contacting the planarizing surface. The method continues by moving the substrate assembly and/or the polishing pad with respect to the other to rub at least one of the substrate assembly and the planarizing surface against the other at a relative velocity. As the substrate assembly and polishing pad rub against each other, a parameter indicative of drag force between the substrate assembly and the polishing pad is measured or sensed at periodic intervals.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: April 13, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Jim Hofmann, Gundu M. Sabde, Stephen J. Kramer, Scott E. Moore
  • Patent number: 6699791
    Abstract: Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of planarizing a microelectronic substrate assembly in accordance with the invention includes pressing a substrate assembly against a planarizing surface of a polishing pad at a pad/substrate interface defined by a surface area of the substrate assembly contacting the planarizing surface. The method continues by moving the substrate assembly and/or the polishing pad with respect to the other to rub at least one of the substrate assembly and the planarizing surface against the other at a relative velocity. As the substrate assembly and polishing pad rub against each other, a parameter indicative of drag force between the substrate assembly and the polishing pad is measured or sensed at periodic intervals.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: March 2, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Jim Hofmann, Gundu M. Sabde, Stephen J. Kramer, Scott E. Moore
  • Patent number: 6666980
    Abstract: A method for manufacturing a resistor function in an electric conductor on the surface of a carrier, preferably a conductor on printed circuit boards, substrates and chips. By etching using an anisotropic etching technique, the conductor is provided with at least one portion which has a smaller cross-sectional area than the conductor surrounding the portion, the length and width of the portion being such that a predetermined resistance is obtained in the conductor. A resistor according to the invention is on both sides connected to a conductor on a carrier, such as a printed circuit board, a substrate or a chip. The resistor comprises a conductor portion positioned on the carrier and having a significantly smaller cross-sectional area than the conductor on both sides of the resistor.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: December 23, 2003
    Assignee: Obducat AB
    Inventor: Bo Wikstrom
  • Publication number: 20030217990
    Abstract: Improved endpoint detection is obtained for wet etch and/or other chemical processes involving in situ measurement of bath impedance. The endpoint detection uses a measurement apparatus having a measurement circuit with a capacitor designed to alter the phase angle of the circuit. The capacitor is preferably a variable capacitor which is used to set the initial phase angle of the measurement circuit to about zero. The methods using the improved detection enable etch to be more precisely controlled even under conditions where noise would otherwise adversely impact determination of the endpoint.
    Type: Application
    Filed: May 24, 2002
    Publication date: November 27, 2003
    Applicant: International Business Machines Corporation
    Inventors: Leping Li, Steven G. Barbee
  • Publication number: 20030196757
    Abstract: A method and apparatus for operating a matching network within a plasma enhanced semiconductor wafer processing system that uses pulsed power to facilitate plasma processing.
    Type: Application
    Filed: May 14, 2002
    Publication date: October 23, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Valentin Todorow, John Holland, Nicolas Gani
  • Publication number: 20030168431
    Abstract: A series of etchant compositions for silver alloy is disclosed. The etchant composition for silver alloy comprises 1 to 60 weight part(s) of hydrogen peroxide; 1 to 60 weight part(s) of sulfuric acid, nitric acid, or organic acid; and 5 to 90 weight part(s) of water Similar etchant composition for silver alloy is. also disclosed, which comprises. 1 to 60 weight part(s) of ammonium compound; 1 to 60 weight part(s) of hydrogen peroxide; and 0 to 96 weight part(s) of water. The etchant composition for silver alloy of the present invention can: etch silver alloy containing more than 80% of silver with a controlled etching rate selectively and effectively. Moreover, the method for using the foresaid etchant composition for silver alloy to form a patterned silver alloy is also disclosed therewith.
    Type: Application
    Filed: February 25, 2003
    Publication date: September 11, 2003
    Applicant: RITdisplay Corporation
    Inventors: Hsu Fong Lee, Hsin Tzu Yao, Chung Che Chou, Ming Shih Chung, Tien Sheng Yeh, Chao Chin Wu
  • Patent number: 6599759
    Abstract: A method for detecting end-point in a plasma etching process by monitoring plasma impedance changes on a time scale is disclosed. In the method, a plasma etching process is first conducted in a process chamber, while changes in a parameter of plasma impedance in the chamber occurring during the etching process is recorded in a curve on a time scale. An end-point of the plasma etching process is then defined for the etching of a specific material layer at a point where the direction of a slope of the curve changes.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: July 29, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Jen-Yuan Yang, Tsai-Yi Chen, Wen-Bin Lin
  • Patent number: 6585909
    Abstract: An oxide for use in a bolometer with an oxide thin-film formed is manufactured on an insulating substrate. Metal organic compound is dissolved in solvent to form solution during manufacturing the oxide thin-film. The solution is applied on the insulating substrate, and the applied solution is dried. A bond between carbon and oxygen is cut and decomposed by irradiating a laser ray with wavelength of 400 nm or less. A generated oxide is crystallized.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: July 1, 2003
    Assignees: National Institute of Advanced Industrial Science & Technology, NEC Corporation
    Inventors: Tetsuo Tsuchiya, Susumu Mizuta, Toshiya Kumagai, Tsutomu Yoshitake, Yuichi Shimakawa, Yoshimi Kubo
  • Publication number: 20030116536
    Abstract: A method for treating the surface of a stainless steel product for a fuel cell containing, in wt %, 0.15% or less of C, 17 to 36% of Cr, 0.005 to 3.5% of B, which comprises the first step of forming in advance a passive film with an oxidizing acid on the surface of the stainless steel product, the second step of allowing an aqueous acid solution to corrode the passive film, to thereby project one or more of a M23C6 type carbide, a M23(C, B)6 type borocarbide and M2B type boride, which are inclusions having good electroconductivity, the third step of forming a passive coating film with an oxidizing acid on the surface of the steel product except that of the inclusion above projected, and the fourth step of washing with water and drying.
    Type: Application
    Filed: November 8, 2002
    Publication date: June 26, 2003
    Inventors: Teruyuki Ohtani, Makoto Tsuji, Masao Utsunomiya
  • Patent number: 6562254
    Abstract: A method of reducing the thickness t of a layer of material on a substrate when the substrate is exposed to an etchant for a span of time sufficient to reduce t to a value to, at which point exposure to the etchant is interrupted, includes the thickness to being determined using monitoring means which, at any given instant, allow determination of the depth &Dgr;t of material which has been etched away. The method further includes the monitoring means being embodied as a resonant crystal whose resonant frequency f at any given instant is a function of the mass m of the crystal at that instant. The crystal is coated with a layer of reference material of thickness d, which material can be etched using the same etchant as for the material on the substrate. The crystal is exposed to the etchant simultaneously with the substrate, thus causing m to decrease as reference material is etched away, a decrease Am in m corresponding to a decrease &Dgr;d in d, in turn corresponding to a decrease &Dgr;t in t.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: May 13, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Dirk M. Knotter, Antonius A. M. Van De Vorst