Substrate Is Multilayered Patents (Class 216/95)
  • Patent number: 7172708
    Abstract: A thin-film device is fabricated by forming a protective layer and a thin-film device layer one by one on a first substrate and bonding a second substrate on the thin-film device layer via a first adhesive layer or a coating layer and first adhesive layer, removing the first substrate at least in a part thereof by etching with a chemical solution, bonding the protective layer, which covers the thin-film device layer on a side of the first substrate, to a third substrate via a second adhesive layer, and removing the second substrate. The protective layer is formed of at least two layers having resistance to the chemical solution used upon removal of the first substrate.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: February 6, 2007
    Assignee: Sony Corporation
    Inventors: Tomoatsu Kinoshita, Akihiko Asano
  • Patent number: 7153445
    Abstract: The invention is directed to a method and composition for providing roughened copper surfaces suitable for subsequent multilayer lamination. A smooth copper surface is contacted with an adhesion promoting composition under conditions effective to provide a roughened copper surface, the adhesion promoting composition consisting essentially of an oxidizer, a pH adjuster, a topography modifier, and a uniformity enhancer. A coating promoter may be used in place of the uniformity enhancer or in addition to the uniformity enhancer. The adhesion promoting composition does not require a surfactant. The process may further comprise the step of contacting the uniform roughened copper surface with a post-dip, wherein the post-dip comprises an azole or silane compound or a combination of said azole and said silane. The post-dip may further comprise, alone or in combination, a titanate, zirconate, and an aluminate. The pH adjuster is preferably sulfuric acid and the oxidizer is preferably hydrogen peroxide.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: December 26, 2006
    Assignee: Electrochemicals Inc.
    Inventors: Roger Bernards, Hector Gonzalez, Al Kucera, Mike Schanhaar
  • Patent number: 7144479
    Abstract: A method whereby a water permeable press fabric is given greater dewatering and drainage capacity by providing voids which are reservoirs of minimum pressure available to accept water.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: December 5, 2006
    Assignee: Albany International Corp.
    Inventors: Trent W. Davis, James G. Donovan
  • Patent number: 7098143
    Abstract: An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting from CMP or in failure analysis for uniform removal of a metal layer (218) without damaging the vias, contact, or underlying structures.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: August 29, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Darwin Rusli
  • Patent number: 7057810
    Abstract: A film for a screen has a light transmitting substrate and a plurality of structures disposed on the substrate. An optical material at least partially fills cavities between the structures. A method of forming a film includes providing a light transmitting substrate having a plurality of structures disposed thereon and at least partially filling the cavities therebetween with an optical material.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: June 6, 2006
    Assignee: 3M Innovative Properties Company
    Inventors: Patrick A. Thomas, John C. Nelson, Scott M. Tapio, Michael L. Graetz, Amy J. Gates, Peter M. Olofson, Robert L. Brott, Robert S. Moshrefzadeh
  • Patent number: 7030033
    Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 in which a thin first conductive film 11 and a thick second conductive film 12 have been laminated via a third conductive film 13 is used.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: April 18, 2006
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamoto
  • Patent number: 7022251
    Abstract: Disclosed is a method for forming a conductor on a dielectric. The method commences with the deposition of a conductive thickfilm on the dielectric, followed by a “subsintering” of the conductive thickfilm. Either before or after the subsintering, the conductive thickfilm is patterned to define at least one conductor. After subsintering, the conductive thickfilm is etched to expose the conductor(s), and the conductor(s) are then fired. A brief chemical etch may be used after the final firing step if improved wire-bondability is required.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: April 4, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: John F. Casey, Lewis R. Dove, Ling Liu, James R. Drehle, R. Frederick Rau, Jr., Rosemary O. Johnson
  • Patent number: 7018549
    Abstract: A method is described for fabricating multiple nanowires of uniform length from a single precursor nucleation particle. The method includes growing a first nanowire segment from a nanoparticle and growing a second nanowire segment between the first nanowire segment and the nanoparticle. The first nanowire segment and the second nanowire segment have a different solubility.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: March 28, 2006
    Assignee: Intel Corporation
    Inventors: Matthew V. Metz, Scott A. Hareland, Robert S. Chau
  • Patent number: 7014784
    Abstract: In one embodiment, a plurality of thickfilm dielectric layers are printed on a substrate, with each successive layer being printed over a previous layer, and with each layer having sloped walls. After printing a first subset of the plurality of thickfilm dielectric layers, a first conductive thickfilm is printed over at least the walls of the first subset of dielectric layers. Then, after printing a second subset of the plurality of thickfilm dielectric layers, a second conductive thickfilm is printed over the second subset of dielectric layers (with the first and second conductive thickfilms being electrically coupled).
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: March 21, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: Lewis R. Dove, John F. Casey
  • Patent number: 7005078
    Abstract: The fluid-flow device (100) of the invention comprises a stack (30) covered by a closure wafer (20), said stack (30) comprising a support wafer (36), a layer of insulating material (34), and a silicon layer (32). The closure wafer (20) and/or said silicon layer (32) are machined so as to define a cavity (38) between said closure wafer (20) and said silicon layer (32), said support wafer (36) has at least one duct (102) passing right through it, said layer of insulating material (34) presenting at least one zone (35) that is entirely free of material placed at least in line with said duct (102) so as to co-operate with said cavity (38) to define a moving member (40) in said silicon layer (32), the moving member being suitable under the pressure of liquid in said cavity (38) for reversibly moving towards said support wafer (36) until contact is made between said moving member (40) and said support wafer (36).
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: February 28, 2006
    Assignee: Debiotech SA
    Inventors: Harald T. Van Lintel, Didier Maillefer, Stephan Gamper
  • Patent number: 6994884
    Abstract: A method of fabricating a support electrode for a solid oxide fuel cell includes (a) providing a solid support electrode having an upper surface, the solid electrode comprising an electronically non-conductive material and an electronically conductive material; (b) applying a mask over the upper surface to create a desired unmasked pattern on the top surface; (c) removing the desired amount of material(s) from the unmasked pattern to a predetermined depth of the support electrode; and (d) removing the mask.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: February 7, 2006
    Assignee: General Electric Company
    Inventors: Jie Guan, Dacong Weng, Vishal Agarwal, Xiwang Qi
  • Patent number: 6991944
    Abstract: This invention relates to a process for treatment of a multi-layer wafer with materials having differential thermal characteristics, the process comprising a high temperature heat treatment step that can generate secondary defects, characterised in that this process includes a wafer surface preparation step before the high temperature heat treatment step.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: January 31, 2006
    Assignees: S.O.I.Tec Silicon on Insulation Technologies S.A., Commissariat à l'Energie Atomique (CEA)
    Inventors: Olivier Rayssac, Beryl Blondeau, Hubert Moriceau, Christelle Lagahe-Blanchard, Franck Fournel
  • Patent number: 6984436
    Abstract: In homogeneous materials, etching characteristics depend on properties inherent in these materials regardless of whether they are isotropic or anisotropic, and there have been limitations in realizing various desired shapes. A subject for the invention is to provide a gradient material which eliminates these limitations. A gradient material is provided in which the rate of etching with a specific chemical substance changes continuously or by steps from the outermost surface to an inner part thereof. This gradient material is made of a main material which contains an additive capable of changing the etching rate of the main material so that the concentration of the additive changes continuously or by steps. Especially when a glass material containing SiO2 as the main component is used as the main material and fluorine is used as the additive, then a gradient material in which the rate of etching with an aqueous solution of hydrofluoric acid changes in the depth direction can be obtained.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: January 10, 2006
    Assignees: National Institute of Advanced Industrial Science and Technology, Nippon Sheet Glass Co., Ltd.
    Inventors: Junji Nishii, Tadashi Koyama, Jun Yamaguchi
  • Patent number: 6949470
    Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 formed by laminating a first conductive film 11 and a second conductive film 12 is covered with a photoresist layer PR having opening portions 13 with inclined surfaces 13S, a conductive wiring layer 14 is formed in the opening portions by electrolytic plating to form inverted inclined surfaces 14R, and then, when covering the same with the sealing resin layer 21, an anchoring effect is produced by making the sealing resin layer 21 bite into the inverted inclined surfaces 14R so as to strengthen bonding of the sealing resin layer 21 with the conductive wiring layer 14.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: September 27, 2005
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamoto
  • Patent number: 6932916
    Abstract: A method for etching trenches having different depths on a semiconductor substrate includes providing a mask with first and second openings. The first and second openings are located where corresponding first and second trenches are to be etched. A slow-etch region, made of a slow-etch material, is provided above the substrate at a location corresponding to the second opening. When exposed to a selected etchant, the slow-etch material is etched at a rate less than the rate at which the semiconductor substrate is etched when exposed to the selected etchant.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: August 23, 2005
    Assignee: Infineon Technologies AG
    Inventors: Dirk Manger, Hans-Peter Moll, Till Schloesser
  • Patent number: 6905618
    Abstract: Diffractive optical elements and methods of making the same are described. In one aspect, a diffractive optical element is made by forming a multilayer structure comprising multiple amorphous silicon phase shift layers having respective thicknesses selected so that the diffractive optical element is operable to phase shift infrared light within an operative wavelength range. The amorphous silicon phase shift layers are separated by respective silicon dioxide etch stop layers having respective thicknesses of about 5 nm or less. Layers of the multilayer structure are serially masked and etched to form a multi-step optical structure. In another aspect, a diffractive optical element is made by forming a multilayer structure comprising multiple etch layers separated by respective etch stop layers selectively etchable with respect to the etch layers. One or more of the etch and etch stop layers are substantially opaque to light within an operative wavelength range.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: June 14, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: James Albert Matthews, Wayne H. Grubbs
  • Patent number: 6902869
    Abstract: A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: June 7, 2005
    Assignee: International Business Machines Corporation
    Inventors: Bernd Karl-Heinz Appelt, James Russell Bupp, Donald Seton Farquhar, Ross William Keesler, Michael Joseph Klodowski, Andrew Michael Seman, Gary Lee Schild
  • Patent number: 6899775
    Abstract: This invention relates to the printing of a substrate having a pre-printed “print pattern” with a “design layer” of ink where there is differential adhesion within and without the print pattern. The print pattern is receptive to an ink, and the design layer ink forms a durable image material with good bond to the print pattern, but the ink does not form a durable image material on the portions of the substrate outside the print pattern. The design layer ink is a UV-curable ink, and the print pattern may have a higher surface energy than the portions of the substrate outside the print pattern.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: May 31, 2005
    Assignee: Contra Vision Ltd.
    Inventors: George Roland Hill, Chris David Parry
  • Patent number: 6818139
    Abstract: In a method for forming a micro-pattern on a substrate (200), polymer material having a solvent is coated on the substrate, thereby forming a polymer film on the substrate. Then, a mold (204) having a predetermined shape is compressed into the polymer film (202) on the substrate by employing a predetermined compression technique to entail a plastic deformation of the polymer film, thereby patterning the polymer film. This compression procedure is performed at a room temperature, e.g., of about 10 to about 30° C. In the present invention, before the mold (204) is pressed into the polymer film (202), a free volume in the polymer film is previously increased so that a pressure applied on the polymer material needed to plastically deform the polymer film is reduced. Thereafter, etching is performed on the substrate through the use of the patterned polymer film as an etching mask, thereby forming a micro-pattern on the substrate.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: November 16, 2004
    Assignee: Minuta Technology Co., Ltd.
    Inventors: Hong Hie Lee, Dahl Young Khang
  • Patent number: 6811714
    Abstract: A method of manufacturing a micromachined component includes using a first liquid to etch a first layer (140) located underneath a second layer (150), exposing the second layer to a second liquid that is inorganic and miscible in carbon dioxide, and supercritical drying the micromachined component with carbon dioxide.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: November 2, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan F. Gorrell, Gordana S. Nielsen
  • Patent number: 6808746
    Abstract: This invention relates to a process for the preparation of a substrate-free aligned nanotube film, comprising: (a) synthesizing a layer of aligned carbon nanotubes on a quartz glass substrate by pyrolysis of a carbon-containing material, in the presence of a suitable catalyst for nanotube formation; and (b) etching the quartz glass substrate at the nanotube/substrate interface to release the layer of aligned nanotubes from the substrate. The invention also provides a process for the preparation of a multilayer carbon nanotube film comprising depositing a substrate-free carbon nanotube film onto another nanotube film. Further, the invention provides a process for the preparation of a “hetero-structured” multilayer carbon nanotube film which includes one or more carbon nanotube layers together with layers of other materials, such as metal, semiconductor and polymer.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: October 26, 2004
    Assignee: Commonwealth Scientific and Industrial Research Organisation Campell
    Inventors: Liming Dai, Shaoming Huang
  • Patent number: 6787051
    Abstract: A method of manufacturing a micro-electromechanical fluid ejecting device includes the step of forming a plurality of nozzle chambers on a wafer substrate. Sacrificial layers are deposited on the wafer substrate. A plurality of fluid ejecting mechanisms is formed on the sacrificial layers to be operatively positioned with respect to the nozzle chambers. The sacrificial layers are etched to free the fluid ejecting mechanisms. The fluid ejecting mechanisms are formed so that they are capable of ejecting fluid through both of a pair of fluid ejection ports defined in a roof of each nozzle chamber on one cycle of operation of the fluid ejecting mechanism.
    Type: Grant
    Filed: November 23, 2002
    Date of Patent: September 7, 2004
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 6787056
    Abstract: A planarization method using anisotropic etching can be applied to planarize an insulating layer with an uneven surface on a substrate. H2SO4, H3PO4, HF and H2O are mixed to form an etching solution. The substrate is placed into the etching solution to make the etching solution pass the surface of the insulating layer at a flow rate to etch the insulating layer. After a period of etching time, the insulating layer with a more planar surface can be obtained.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: September 7, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Wen-Bin Tsai, Ching-Yu Chang, Chun-Pei Wu, Huei-Huang Chen, Samuel C. Pan
  • Patent number: 6749760
    Abstract: The invention relates to a ball-limiting metallurgy (BLM) etching system and process. The BLM stack is provided for an electrical device that contains an aluminum layer disposed upon a metal first layer. A metal upper layer is disposed above the metal second layer, and an alternative metal third layer is disposed between the metal second layer and the metal upper layer. The etching system and process utilizes an etching solution that includes a nitrogen-containing heterocyclic compound, an ammonium hydroxide compound, an oxidizer, and a metal halide compound. Etching conditions prevent any metallization that is dissolved from redepositing, thus avoiding lowered yields.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: June 15, 2004
    Assignee: Intel Corporation
    Inventors: Donald Danielson, Tzeun-luh Huang, Dawn L. Scovell, Keith Willis
  • Patent number: 6740248
    Abstract: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a second dielectric layer overlying a first dielectric layer, contacting the substrate at a first temperature with a first acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with a second acid solution exhibiting a positive etch selectivity at the second temperature. The first and second dielectric layers exhibit different etch rates in the first and second acid solutions. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175° C. and the second temperature may be about 155° C.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: May 25, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Don L. Yates
  • Patent number: 6733597
    Abstract: A method is provided for cleaning a dual damascene structure. A first metal layer, a cap layer, and a dielectric layer are formed on a substrate in sequence. Then a dual damascene opening is formed in the dielectric layer and the cap layer exposing the first metal layer. Next, a post-etching cleaning step is carried out to clean the dual damascene opening using a fluorine-based solvent. Then, an argon gas plasma is sputtered to clean the dual damascene opening before a second metal layer fills in the dual damascene opening.
    Type: Grant
    Filed: April 24, 2001
    Date of Patent: May 11, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Ning Wu, Sun-Chieh Chien
  • Patent number: 6712985
    Abstract: A method and apparatus for the manufacture of thin film magnetic transducers using a compliant pad or mat or surface in a lapping process is disclosed. The lapping process is applied to heads to eliminate both ductile element connections between the MR and shields and poletip and shield protrusion. A lapping media is dispensed onto an interface surface of a compliant pad. Then, the interface surface is engaged to the surface of a head outside a region comprising transducers defining a head gap. The pad is then moved over the head in a direction parallel to the head gap while using a head rail to guide the pad. The soft, compliant pad conforms to the head rail to ensure parallel movement. The pad is typically not stopped at the elements, but rather moves from one end of the head to the other to prevent bridging and damage that might occur during start/stop on the delicate elements.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: March 30, 2004
    Assignee: Hitachi Global Storage Technologies
    Inventor: Robert Glenn Biskeborn
  • Patent number: 6692580
    Abstract: A method of cleaning a dual damascene structure. A first metal layer, a cap layer, and a dielectric layer are formed on a substrate in sequence. Then a dual damascene opening is formed in the dielectric layer and the cap layer, exposing the first metal layer. Then, a post-etching cleaning step is carried out to clean the dual damascene opening, and there are two types of cleaning methods. The first method uses a fluorine-based solvent to clean the dual damascene opening. An alternative cleaning method uses a hydrogen peroxide based solvent at a high temperature, followed by a hydrofluoric acid solvent cleaning step. Then, an argon gas plasma is sputtered to clean the dual damascene opening before a second metal layer fills in the dual damascene opening.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: February 17, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Ning Wu, Sun-Chieh Chien
  • Patent number: 6649078
    Abstract: Method and system of forming microfluidic capillaries in a variety of substrate materials. A first layer of a material such as silicon dioxide is applied to a channel etched in substrate. A second, sacrificial layer of a material such as a polymer is deposited on the first layer. A third layer which may be of the same material as the first layer is placed on the second layer. The sacrificial layer is removed to form a smooth walled capillary in the substrate.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: November 18, 2003
    Assignee: The Regents of the University of California
    Inventor: Conrad M. Yu
  • Publication number: 20030178389
    Abstract: A method of forming via hole metal layers, including the steps of forming via holes in a Si layer by etching an SOI substrate having a SiO2 layer and the Si layer formed on a Si substrate in order of precedence, the via holes being extended to the SiO2 layer, and forming the via hole metal layers in the via holes.
    Type: Application
    Filed: February 26, 2003
    Publication date: September 25, 2003
    Inventor: Mitsuhiro Yuasa
  • Publication number: 20030146190
    Abstract: A planarization method using anisotropic etching can be applied to planarize an insulating layer with an uneven surface on a substrate. H2SO4, H3PO4, HF and H2O are mixed to form an etching solution. The substrate is placed into the etching solution to make the etching solution pass the surface of the insulating layer at a flow rate to etch the insulating layer. After a period of etching time, the insulating layer with a more planar surface can be obtained.
    Type: Application
    Filed: February 7, 2002
    Publication date: August 7, 2003
    Inventors: Wen-Bin Tsai, Ching-Yu Chang, Chun-Pei Wu, Huei-Huang Chen, Samuel C. Pan
  • Patent number: 6579565
    Abstract: A multilayered circuit board is produced by: a. laminating a copper foil conductor layer and a nickel foil or nickel plating etch-stopping layer by simultaneously press-bonding the nickel and copper layer to form a multilayered clad sheet; b. selectively etching the multilayered clad sheet; c. forming an insulating layer and an outer conductor layer on the surface of the clad sheet; d. patterning the outer conductor layer; and e. electrically connecting the internal conductor layer and the outer conductor layer by interposing a columnar conductor formed in the base by etching.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: June 17, 2003
    Assignee: Toyo Kohan Co., Ltd.
    Inventors: Kinji Saijo, Shinji Ohsawa, Kazuo Yoshida
  • Patent number: 6547973
    Abstract: A method for fabricating a suspended structure including a layer of membrane material over a substrate. The suspended structure overlies a cavity in the substrate. The method starts by generating a sacrificial layer comprising a first material that can withstand temperatures typically encountered in subsequent conventional semiconductor processing steps. In the preferred embodiment of the present invention, the bond between sacrificial layer and the underlying substrate must be capable of withstanding temperatures greater than the Si—Al eutectic point. A layer of membrane material is then deposited over the sacrificial layer. The membrane material comprises a second material different from the first material. An opening is introduced in the layer of membrane material thereby exposing the sacrificial layer. A first etchant is applied to the sacrificial layer through the opening until the sacrificial layer is removed leaving a portion of the cavity.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: April 15, 2003
    Assignee: Agilent Technologies, Inc.
    Inventor: Leslie A. Field
  • Patent number: 6521136
    Abstract: Method of making a three-dimensional photonic band-gap crystal, in which a three-dimensional structure is built by successively forming a plurality of superimposed layers of photosensitive chalcogenide and creating a predetermined grating on each of them. A layer of photoresist is superimposed on each chalcogenide layer. The chalcogenide glasses are chosen among those that are photosensitive, have a high refractive index, a high ratio of high etching speed to low etching speed of at least 10. The refractive index of the glasses may be higher than 2.5. The ratio of high etching speed to low etching speed of the glasses may be at least 10.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: February 18, 2003
    Assignee: State of Isreal, Atomic Energy Commision, Soraq Nuclear Research Center
    Inventors: Bruno Gad Sfez, Zvi Kotler
  • Patent number: 6514422
    Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch which produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multilayer work piece having different layers formed of the same material, or it may be a single layer of material. The process can be used to manufacture a base structure for a conical cathode emitter tip.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: February 4, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Karen Huang, Christophe Pierrat
  • Publication number: 20030010746
    Abstract: A method for using an organic dielectric as a sacrificial layer for forming suspended or otherwise spaced structures. The use of an organic dielectric has a number of advantages, including allowing use of an organic solvent or etch to remove the sacrificial layer. Organic solvents only remove organic materials, and thus do not affect or otherwise damage non-organic layers such as metal layers. This may reduce or eliminate the need for the rinsing and drying steps often associated with the use of acidic etchants such as Hydrofluoric Acid.
    Type: Application
    Filed: July 10, 2001
    Publication date: January 16, 2003
    Inventors: David Gutierrez, Vincent K. Luciani, Mary C. Burgess
  • Publication number: 20030006213
    Abstract: A method and apparatus for the manufacture of thin film magnetic transducers using a compliant pad or mat or surface in a lapping process is disclosed. The lapping process is applied to heads to eliminate both ductile element connections between the MR and shields and poletip and shield protrusion. A lapping media is dispensed onto an interface surface of a compliant pad. Then, the interface surface is engaged to the surface of a head outside a region comprising transducers defining a head gap. The pad is then moved over the head in a direction parallel to the head gap while using a head rail to guide the pad. The soft, compliant pad conforms to the head rail to ensure parallel movement. The pad is typically not stopped at the elements, but rather moves from one end of the head to the other to prevent bridging and damage that might occur during start/stop on the delicate elements.
    Type: Application
    Filed: July 3, 2001
    Publication date: January 9, 2003
    Applicant: International Business Machines Corporation
    Inventor: Robert Glenn Biskeborn
  • Patent number: 6500354
    Abstract: An inkjet printer head actuator including a vibrating plate having a flat plate shape, a chamber plate coupled to the vibrating plate, the chamber plate having chamber walls defining a plurality of uniformly spaced chambers each having a horizontal cross-sectional area decreasing gradually, as it extends one end thereof arranged toward the vibrating plate to the other end thereof arranged away from the vibrating plate, each of the chamber walls having a horizontal cross-sectional area increasing gradually as it extends one end thereof arranged toward the vibrating plate to the other end thereof arranged away from the vibrating plate, and a plurality of drive means attached to a surface of the vibrating plate opposite to the chamber plate at regions corresponding to the chambers, respectively.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: December 31, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Don Lee, Jae Woo Joung
  • Patent number: 6500352
    Abstract: An electrode plate is formed by a substrate and a plurality of patterned electrodes formed on the substrate. Each patterned electrode has a laminate structure including a first layer of nickel metal formed on the substrate and a second layer of copper formed thereon. The electrode plate may be prepared by a process including a step of etching such a multi-layer metal electrode-forming film formed on a substrate by spraying an etchant downwardly and uniformly onto the substrate while rotating the substrate at a rotation speed sufficient to allow quick liberation of the etchant from the substrate. The metal electrodes can be formed with good adhesion onto the substrate and with good width and thickness accuracy. By incorporating the electrode plate as a pair of substrates sandwiching a liquid crystal, a liquid crystal device free from transmission delay and rounding of voltage waveforms can be provided.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: December 31, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshiaki Yoshikawa, Makoto Kameyama, Junri Ishikura
  • Patent number: 6497827
    Abstract: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a second dielectric layer overlying a first dielectric layer, contacting the substrate at a first temperature with a first acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with a second acid solution exhibiting a positive etch selectivity at the second temperature. The first and second dielectric layers exhibit different etch rates in the first and second acid solutions. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175° C. and the second temperature may be about 155° C.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: December 24, 2002
    Assignee: Micron Technology Inc.
    Inventors: Li Li, Don L. Yates
  • Publication number: 20020170883
    Abstract: A method of use for a reusable monitor wafer, having multiple crystal original pits (COP) on its surface, used for monitoring and measuring particle amounts in a chemical vapor deposition (CVD) process. First, a silicon oxide layer is formed on the surface of a monitor wafer. A first cleaning process and a thin film deposition process, forming a thin film layer on a surface of the silicon oxide layer, are then performed, respectively. Thereafter, a particle measurement process is performed to measure particle amounts on the surface of the thin film layer. After removing the thin film layer and the silicon oxide layer on the monitor wafer, respectively, a second cleaning process is performed.
    Type: Application
    Filed: May 17, 2001
    Publication date: November 21, 2002
    Inventor: Ching-Yu Chang
  • Publication number: 20020160561
    Abstract: In a method of fabricating a microstructure for microfluidics applications, a first layer of etchable material is formed on a suitable substrate. A mechanically stable support layer is formed over the etchable material. A mask is applied over the support to expose at least one opening in the mask. An anistropic etch is then performed through the opening to create a bore extending through the support layer to said layer of etchable material. After performing an isotropic etch through the bore to form a microchannel in the etchable material extending under the support layer, a further layer is deposited over the support layer until overhanging portions meet and thereby close the microchannel formed under the opening.
    Type: Application
    Filed: April 27, 2001
    Publication date: October 31, 2002
    Inventors: Luc Ouellet, Heather Tyler
  • Patent number: 6468439
    Abstract: A process for the etching of multiple layers of at least two different metals comprisies: forming a resist pattern over a first layer of metal, said resist pattern having a pattern of openings therein, applying a first etch solution onto said resist pattern so that at least some etch solution contacts exposed areas of the first layer of metal, etching away the majority of the depth of the first metal in exposed areas of metal in the first layer of metal, applying a second etch solution onto the resist pattern the second etch solution having a rate of etch towards the first metal as compared to the first etch solution that is at least 20% less than the millimeter/minute rate of etch of the first etch solution at the same etch solution temperature, removing the second etch solution from said resist pattern after at least the first metal layer has been etched sufficiently to expose areas of a second metal layer underlying the first metal layer by forming an etched first metal layer, and applying a third etch so
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: October 22, 2002
    Assignee: BMC Industries, Inc.
    Inventors: Donald A. Whitehurst, Paul D. Wyatt, Charles Ring, Michael J. Dufresne, Jose F. Brenes, Bruce A. Finger, Dave R. Zeipelt
  • Patent number: 6444083
    Abstract: A corrosion resistant component of semiconductor processing equipment such as a plasma chamber includes a metal surface such as aluminum or aluminum alloy, stainless steel, or refractory metal coated with a phosphorus nickel plating and an outer ceramic coating such as alumina, silicon carbide, silicon nitride, boron carbide or aluminum nitride. The phosphorus nickel plating can be deposited by electroless plating and the ceramic coating can be deposited by thermal spraying. To promote adhesion of the ceramic coating, the phosphorus nickel plating can be subjected to a surface roughening treatment prior to depositing the ceramic coating.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: September 3, 2002
    Assignee: Lam Research Corporation
    Inventors: Robert Steger, Chris Chang
  • Patent number: 6436300
    Abstract: A method of manufacturing electronic components includes disposing a top metal layer (502) comprised of solder over a bottom metal layer (201, 202) comprised of titanium or tungsten, and selectively etching the bottom metal layer (201, 202) over the top metal layer (502) with an etchant mixture (601) comprised of an etchant, an additive to control the temperature of the etchant mixture (601), and another additive to reduce the redeposition of the top layer (502).
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: August 20, 2002
    Assignee: Motorola, Inc.
    Inventors: Eric J. Woolsey, Douglas G. Mitchell, George F. Carney, Francis J. Carney, Jr., Cary B. Powell
  • Patent number: 6426012
    Abstract: A three-part etching process is employed to selectively pattern exposed magnetic film layers of a magnetic thin film structure. The magnetic structure to be etched includes at least one bottom magnetic film layer and at least one top film layer which are separated by a tunnel barrier layer. The three-part etching process employs various etching steps that selective removing various layers of the magnetic thin film structure stopping on the tunnel barrier layer. The first etching step selective removes any surface oxide that may be present in the passivating layer that is formed on the top magnetic thin film layer, the second etching step selectively removes portions of the passivating layer and the third etching step selectively removes a portion of the exposed magnetic film layer of the structure stopping on the tunnel barrier layer.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: July 30, 2002
    Assignee: International Business Machines Corporation
    Inventors: Eugene John O'Sullivan, Alejandro Gabriel Schrott
  • Patent number: 6420099
    Abstract: A method for patterning an aluminum-containing layer. A tungsten-containing layer is provided over an aluminum-containing layer. The tungsten-containing layer is patterned to form an opening therein, so that the opening exposes an underlying portion of the aluminum-containing layer. The patterned tungsten-containing layer is exposed to an etch having a substantially higher etch rate of the aluminum-containing layer than of the tungsten-containing layer to remove the exposed portion of the aluminum-containing layer.
    Type: Grant
    Filed: August 2, 1999
    Date of Patent: July 16, 2002
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Martin Gutsche, Satish D. Athavale
  • Patent number: 6413436
    Abstract: In a process for treating a workpiece such as a semiconductor wafer, a processing fluid is selectively applied or excluded from an outer peripheral margin of at least one of the front or back sides of the workpiece. Exclusion and/or application of the processing fluid occurs by applying one or more processing fluids to the workpiece while the workpiece and a reactor holding the workpiece are spinning. The flow rate of the processing fluids, fluid pressure, and/or spin rate are used to control the extent to which the processing fluid is selectively applied or excluded from the outer peripheral margin.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: July 2, 2002
    Assignee: Semitool, Inc.
    Inventors: Brian Aegerter, Curt T. Dundas, Michael Jolley, Tom L. Ritzdorf, Steven L. Peace, Gary L. Curtis, Raymon F. Thompson
  • Patent number: 6406639
    Abstract: A method of partially forming oxide layers on a surface of a glass substrate by forming an oxide layer on the surface of the substrate, partially contacting the surface of the oxide layer formed on the substrate with a paste comprising an inorganic compound different from the oxide, organic solvents and silicon powder to partially dissolving the oxide layer with the paste, and removing the dissolved components of the layer together with the paste, by which the oxide layers are partially formed on the surface of the substrate efficiently and surely.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: June 18, 2002
    Assignee: Nippon Sheet Glass Co., Ltd.
    Inventors: Koichi Sakaguchi, Osamu Ishii, Yasunori Shiraishi
  • Patent number: RE39413
    Abstract: The present invention is a semiconductor wafer that enhances polish-stop endpointing in chemical-mechanical planarization processes. The semiconductor wafer has a substrate with a device feature formed on the substrate, a stratum of low friction material positioned over the substrate, and an upper layer deposited on the low friction material stratum. The low friction stratum has a polish-stop surface positioned at a level substantially proximate to a desired endpoint of the chemical-mechanical planarization process. The upper layer, which is made from either a conductive material or an insulative material, has a higher polishing rate than that of the low friction stratum. In operation, the low friction stratum resists chemical-mechanical planarization with either hard or soft polishing pads to stop the planarization process at the desired endpoint.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: November 28, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Guy F. Hudson, Renee Zahorik, Russell C. Zahorik