Abstract: A non-ported expanding gate valve and method of use, including an expanding gate assembly and a slotted guide, is fixedly positioned on the valve body and slidably coupled with a gate assembly. The guide has slots of varying widths that are used with a pivoting rocker arm coupled with the gate assembly to adjust the thickness of the gate assembly at the proper timing. The guides perform multiple functions, including: centralizing a rocker arm during opening between seats; collapsing the gate assembly when opening; allowing and controlling expansion when closing; guiding lateral movement during operation of the gate assembly between opposing guides on the sides of a flow passageway; guiding axial movement during operation of the gate assembly between opposing guide side flanges; retaining seats in position when the valve is open; and/or stiffening the guide in a lateral direction to control movement of the gate assembly.

Abstract: The invention is a dual spreading link mechanism for application with gate valves. The invention also extends to gate valves employing the inventive dual spreading link. In one application to pendulum gate valves, a valve carriage assembly moves in a pendular manner within a gate valve housing and operates to seal off the flow channel of the housing. The valve carriage assembly is comprised of a valve plate having a valve seat face for engaging with the housing in a sealing manner, a tensioning member which along with a plurality of clip springs provides a contracting force to the valve carriage assembly, and an actuating member which moves laterally within the carriage assembly to alternately spread and contract the assembly. The actuating member is stacked between the valve plate and tensioning member and the actuating member is coupled to the valve plate and tensioning member by a plurality of oblong rotatable links which comprise the dual spreading link.

Abstract: A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.