Abstract: An embodiment of a magnetic-field sensor includes a magnetic-field sensor arrangement and a magnetic body which has, for example, a non-convex cross-sectional area with regard to a cross-sectional plane running through the magnetic body, the magnetic body having an inhomogeneous magnetization.

Abstract: A power electronics module and a method of producing a power electronics module. The power electronics module includes multiple of power electronic semiconductor chips incorporated in a housing and attached to a substrate, and a heat transfer structure attached to the substrate and having a bottom surface which forms an outer surface of the module and which is adapted to receive a surface of a cooling device, wherein the heat transfer structure includes a compressible base plate.

Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

Abstract: A memory cell of a magnetic random access memory includes multiple layers disposed between a first metal layer and a second metal layer. At least one of the multiple layers include one selected from the group consisting of an iridium layer, a bilayer structure of an iridium layer and an iridium oxide layer, an iridium-titanium nitride layer, a bilayer structure of an iridium layer and a tantalum layer, and a binary alloy layer of iridium and tantalum.

Abstract: A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor, the memory peripherals transistor is overlaying the second transistor or is underneath the first transistor, where the second memory cell overlays the first memory cell at a distance of less than 200 nm, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.

Abstract: A device may include a lead frame, where the lead frame includes a central portion, and a side pad, the side pad being laterally disposed with respect to the central portion. The device may further include a thyristor device, the thyristor device comprising a semiconductor die and further comprising a gate, wherein the thyristor device is disposed on a first side of the lead frame on the central portion. The device may also include a positive temperature coefficient (PTC) device electrically coupled to the gate of the thyristor device, wherein the PTC device is disposed on the side pad on the first side of the lead frame; and a thermal coupler having a first end connected to the thyristor device and a second end attached to the PTC device.

Abstract: Methods of manufacturing are disclosed for an inductor that includes a magnetic core lying in a core plane. The magnetic core includes a vertical laminated structure with respect to the core plane of alternating ferromagnetic vertical layers and insulator vertical layers. An easy axis of magnetization can be permanently or semi-permanently fixed in the ferromagnetic vertical layers along a first axis orthogonal to the core plane. A hard axis of magnetization can be permanently or semi-permanently induced in the ferromagnetic vertical layers, the hard axis of magnetization lying in a plane that is orthogonal to the first axis.

Abstract: An embodiment of a magnetic-field sensor includes a magnetic-field sensor arrangement and a magnetic body which has, for example, a non-convex cross-sectional area with regard to a cross-sectional plane running through the magnetic body, the magnetic body having an inhomogeneous magnetization.

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer between the first and second magnetic layers. The second magnetic layer includes a first main surface on the nonmagnetic layer side and a second main surface opposite to the first main surface, and includes a first region on the first main surface side and a second region on the second main surface side, and an intermediate region between the first and second regions and containing a predetermined nonmagnetic element. A concentration of the predetermined nonmagnetic element in the intermediate region is higher than that in the first and second regions. The second magnetic layer contains a magnetic element from the first to second main surfaces.

Abstract: Switches for electromagnetic radiation, including radiofrequency switches and optical switches, are provided. Also provided are methods of using the switches. The switches incorporate layers of high quality VO2 that are composed of a plurality of connected crystalline VO2 domains having the same crystal structure and orientation.

Abstract: Multiple intertwined inductor coils combine to form one or more transformer devices of a semiconductor device. The intertwined inductor coils are formed of only two metallization layers and vias coupling the layers. The inductor coils are vertically oriented and include a magnetic axis parallel to the substrate surface. A plurality of metal wires are provided on both a first device level and a second device level. Each of the metal wires on the first device level is coupled to two wires on the second device level and forms a first inductor coil. The two metal wires on the second device level that form part of the first inductor coil, are separated by a third wire that is coupled to two different first device level metal wires and forms part of a different second inductor coil intertwined with the first inductor coil.

Abstract: A magnetoresistive memory device that stores data in the reference portion of spin-torque memory cells provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. Techniques for storing data in the reference portions of memory cells are presented, along with techniques for recovering data stored in the reference portions of memory cells.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A bottom electrode layer is provided on a substrate. A seed layer is deposited on the bottom electrode layer. The seed layer and bottom electrode layer are patterned. A dielectric layer is deposited over the patterned seed layer and bottom electrode layer and planarized wherein the seed layer is exposed. Thereafter, a stack of MTJ layers is deposited on the patterned seed layer comprising a pinned layer, a tunnel barrier layer, and a free layer. The MTJ stack is then patterned to form a MTJ device. Because the seed layer was patterned before the MTJ patterning step, the exposure of the device to etching plasma gases is shortened and thus, etch damage is minimized.

Abstract: An intrinsically safe voltage clamping device includes a regulated rail, a ground rail, and a shunt regulator assembly. The shunt regulator assembly is coupled to both the regulated rail and the ground rail and includes one or more regulating components. The shunt regulator assembly is configured to clamp a voltage applied across the regulated rail and the ground rail to a safety clamp voltage value. The intrinsically safe voltage clamping device also includes a power-sensing component configured to cause one or more limiting components to reduce a power dissipated in the respective regulating components without raising the clamp voltage.

Abstract: The present disclosure provides a memory device structure including a wafer substrate, a magnetic tunnel junction (MTJ) formed by a first magnetic layer, a second magnetic layer, and a thin non-magnetic layer stacked along a first direction perpendicular to an upper surface of the wafer substrate above which the MTJ is formed, the non-magnetic layer being interposed between the first magnetic layer and the second magnetic layer, a first contact electrically coupled to the first magnetic layer, and a second contact electrically coupled to the second magnetic layer.

Abstract: A proximity switch assembly and method for detecting activation of a proximity switch assembly is provided. The assembly includes a plurality of proximity switches each having a proximity sensor providing a sense activation field and control circuitry processing the activation field of each proximity switch to sense activation. A pliable material overlays the proximity sensors. A depression is formed in a substrate between the pliable material and the sensor. A groove may extend into the substrate between adjacent proximity switches. The pliable material may further include an elevated portion.

Abstract: A current detector senses current flowing through a conductor, such as a conductive trace of a circuit board, without being placed in series with the conductor. A first magnetically conductive partial ring is located above the conductor, and a second magnetically conductive partial ring is located below the conductor. Ends of one of the partial rings may be inserted through holes of the circuit board to either side of the conductive trace. The partial rings, upon being contactively aligned with one another, form a magnetically conductive complete ring around the conductor. A Hall effect sensor disposed within one of the partial rings outputs a signal corresponding to the current flowing through the conductor.

Abstract: A nonvolatile semiconductor memory device is provided with a magnetoresistive effect element formed on a substrate, and an insulating film formed above the substrate to cover the magnetoresistive effect element. The insulating film is formed of a silicon nitride, and has a portion of a higher nitrogen concentration than a surface portion thereof.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A thermally assisted switching MRAM element including a magnetic tunnel junction including a reference layer having a reference magnetization; a storage layer having a storage magnetization; a tunnel barrier layer included between the storage layer and the reference layer; and a storage antiferromagnetic layer exchange-coupling the storage layer such as to pin the storage magnetization at a low temperature threshold and to free it at a high temperature threshold. The antiferromagnetic layer includes: at least one first antiferromagnetic layer having a first storage blocking temperature, and at least one second antiferromagnetic layer having a second storage blocking temperature; wherein the first storage blocking temperature is below 200° C. and the second storage blocking temperature is above 250° C. The MRAM element combines better data retention compared with known MRAM elements with low writing mode operating temperature.

Abstract: A nonvolatile magnetic memory device using a magnetic tunneling junction (MTJ) uses as a data storage unit an MTJ including a pinned magnetic layer, a nonmagnetic insulating layer, and a free magnetic layer which are sequentially stacked. The free magnetic layer includes at least one soft magnetic amorphous alloy layer in which zirconium (Zr) is added to a soft magnetic material formed of cobalt (Co) or a Co-based alloy.

Abstract: A MTJ for a spintronic device that is a domain wall motion device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A pressure sensor device is assembled by forming cavities on a surface of a metal sheet and then forming an electrically conductive pattern having traces and bumps over the cavities. An insulating layer is formed on top of the pattern and then processed to form exposed areas and die attach areas on the surface of the metal sheet. The exposed areas are plated with a conductive metal and then electrically connected to respective ones of the bumps. A gel is dispensed on the die attach areas and sensor dies are attached to respective die attach areas. One or more additional semiconductor dies are attached to the insulating layer and bond pads of these dies are electrically connected to the exposed plated areas. A molding compound is dispensed such that it covers the sensor die and the additional dies. The metal sheet is removed to expose outer surfaces of the bumps.

Abstract: A magnetic tunnel junction device includes a first electrode having a curved top surface, a magnetic tunnel junction layer formed along the top surface of the first electrode, and a second electrode formed on the magnetic tunnel junction layer.

Abstract: The object of the present invention is to provide a method of fabricating a thermoelectric material and a thermoelectric material fabricated thereby. According to the present invention, since carbon nanotubes with no surface treatment are dispersed in the alloy, electrical resistivity decreases and electrical conductivity increases in comparison to surface-treated carbon nanotubes and an amount of thermal conductivity decreased is the same as that in the case of using surface-treated carbon nanotubes, and thus, a ZT value, a thermoelectric figure of merit, is improved. A separate reducing agent is not used and an organic solvent having reducing powder is used to improve economic factors related to material costs and process steps, and carbon nanotubes may be dispersed in the thermoelectric material without mechanical milling.

Abstract: A micro-electromechanical system (MEMS) device can include a substrate and a first beam suspended relative to a substrate surface. The first beam can include a first portion and a second portion that are separated by an isolation joint made of an insulative material. The first and second portions can each include a first semiconductor and a first dielectric layer. The MEMS device can also include a second beam suspended relative to the substrate surface. The second beam can include a second semiconductor and a second dielectric layer to promote curvature of the second beam. The MEMS device can also include a third beam suspended relative to the substrate surface. The third beam consists essentially of a first material. The second beam is configured to move relative to the third beam in response to an acceleration along an axis perpendicular to the surface of the substrate.

Abstract: Magnetic tunnel junction transistor devices and methods for operating and forming magnetic tunnel junction transistor devices. In one aspect, a magnetic tunnel junction transistor device includes a first source/drain electrode, a second source/drain electrode, a gate electrode, and a magnetic tunnel junction disposed between the gate electrode and the second source/drain electrode. The magnetic tunnel junction includes a magnetic free layer that extends along a length of the gate electrode toward the first source/drain electrode such that an end portion of the magnetic free layer is disposed between the gate electrode and the first source/drain electrode. The magnetic tunnel junction transistor device switches a magnetization orientation of the magnetic free layer by application of a gate voltage to the gate electrode, thereby changing a resistance between the first and second source/drain electrodes through the magnetic free layer.

Abstract: According to one embodiment, a die package is provided comprising a first die structure with a first plurality of switching elements wherein controlled current input terminals of the first plurality of switching elements are electrically coupled by a common contact region and wherein controlled current output terminals of the first plurality of switching elements are insulated from each other; a second die structure with a second plurality of switching elements wherein controlled current output terminals of the second plurality of switching elements are coupled by a common contact region and wherein controlled current input terminals of the second plurality of switching elements are insulated from each other; and wherein, for each of the first plurality of switching elements, the output terminal of the switching element is coupled with the input terminal of at least one switching element of the second plurality of switching elements.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.

Abstract: A nonvolatile magnetic memory device having a magnetoresistance-effect element includes: (A) a laminated structure having a recording layer in which an axis of easy magnetization is oriented in a perpendicular direction; (B) a first wiring line electrically connected to a lower part of the laminated structure; and (C) a second wiring line electrically connected to an upper part of the laminated structure, wherein a high Young's modulus region having a Young's modulus of a higher value than that of a Young's modulus of a material forming the recording layer is provided close to a side surface of the laminated structure.

Abstract: Embodiments of a thin-film heterostructure thermoelectric material and methods of fabrication thereof are disclosed. In general, the thermoelectric material is formed in a Group IIa and IV-VI materials system. The thermoelectric material includes an epitaxial heterostructure and exhibits high heat pumping and figure-of-merit performance in terms of Seebeck coefficient, electrical conductivity, and thermal conductivity over broad temperature ranges through appropriate engineering and judicious optimization of the epitaxial heterostructure.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. A CoFeB layer may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.

Abstract: Method for encapsulating an electronic arrangement against permeates wherein a pressure-sensitive adhesive mass based on butylene block copolymers is applied to and around the areas of the electronic arrangement to be encapsulated.

Abstract: Atomic layer deposition is enhanced using plasma. Plasma begins prior to flowing a second precursor into a chamber. The second precursor reacts with a first precursor to deposit a layer on a substrate. The layer may include at least one element from each of the first and second precursors. The layer may be TaN, and the precursors may be TaF5 and NH3. The plasma may begin during purge gas flow between a pulse of the first precursor and a pulse of the second precursor. Thermal energy assists the reaction of the precursors to deposit the layer on the substrate. The thermal energy may be greater than generally accepted for ALD (e.g., more than 300 degrees Celsius).

Abstract: A micro-electromechanical system (MEMS) device includes a substrate, a first beam, a second beam, and a third beam. The first beam includes first and second portions separated by an isolation joint. The first and second portions each comprise a semiconductor and a first dielectric layer. An electrically conductive trace is mechanically coupled to the first beam and electrically coupled to the second portion's semiconductor but not the first portion's semiconductor. The second beam includes a second dielectric layer. The profile of each of the first second, and third beams has been formed by a dry etch. A cavity separates a surface of the substrate from the first, second, and third beams. The cavity has been formed by a dry etch. A side wall of each of the first, second, and third beams has substantially no dielectric layer disposed thereon, and the dielectric layer has been removed by a vapor-phase etch.

Abstract: A piezoresistive pressure sensor is provided, which can prevent the occurrence of ESD breakdown due to the nearness of interconnection layers of a resistive element according to miniaturization thereof. The piezoresistive pressure sensor is so configured that respective semiconductor resistive layers on both sides of an arrangement are formed to be relatively longer than an adjacent semiconductor resistive layer, and thus a corner portion of a semiconductor connection layer that extends from the respective semiconductor resistive layers on both sides of the arrangement and a corner portion of the semiconductor interconnection layer that is nearest to the corner portion of the semiconductor connection layer, between which the ESD breakdown occurs easily, can be separated from each other.

Abstract: A magnetoresistive random access memory includes first and second magnetoresistive effect element. A shape of the first magnetoresistive effect element has a first length in a first direction and a second length in a second direction. The second length is equal to or greater than the first length. A ratio of the second length to the first length is a first value. The second magnetoresistive effect element is used to determine a resistance state of the first magnetoresistive effect element. A shape of the second magnetoresistive effect element has a third length in a third direction and a fourth length in a fourth direction. The fourth length is equal to or greater than the third length. A ratio of the fourth length to the third length is a second value which is greater than the first value.

Abstract: A magnetoresistive element includes a stacked structure including a fixed layer having a fixed direction of magnetization, a recording layer having a variable direction of magnetization, and a nonmagnetic layer sandwiched between the fixed layer and the recording layer, a first protective film covering a circumferential surface of the stacked structure, and made of silicon nitride, and a second protective film covering a circumferential surface of the first protective film, and made of silicon nitride. A hydrogen content in the first protective film is not more than 4 at %, and a hydrogen content in the second protective film is not less than 6 at %.

Abstract: The MIS field-effect transistor includes: a substrate; a nitride semiconductor multilayer structure portion formed on the substrate, including a first group III-V nitride semiconductor layer of a first conductivity type, a second group III-V nitride semiconductor layer of a second conductivity type stacked thereon and a third group III-V nitride semiconductor layer of the first conductivity type stacked thereon; a gate insulating film formed on a wall surface formed over the first, second and third group III-V nitride semiconductor layers to extend over these first, second and third group III-V nitride semiconductor layers; a gate electrode made of a conductive material formed as being opposed to the second group III-V nitride semiconductor layer via the gate insulating film; a drawn portion electrically connected to the first group III-V nitride semiconductor layer and drawn from the nitride semiconductor multilayer structure portion in a direction parallel to the substrate; a drain electrode formed in conta

Abstract: A sensor module has a carrier substrate having a bottom side and a top side, a sensor chip arranged on the top side of the carrier substrate and having a pressure-sensitive active area, a signal-processing chip arranged on the top side of the carrier substrate next to the sensor chip and being connected to the sensor chip in an electrically conducting manner, a continuous casting material covering the top side of the carrier substrate and the signal-processing chip and being in mechanical contact with both, the casting material having a recess which is arranged such that the casting material does not cover at least a part of the active area of the sensor chip.

Abstract: A method and apparatus is provided for use in an integrated circuit or printed circuit board for reducing or minimizing interference. An inductance is formed using two or more inductors coupled together and configured such that current flows through the inductors in different directions, thus at least partially canceling magnetic fields. When designing a circuit, the configuration of the inductors, as well as the relative positions of portions of the circuit, can be tweaked to provide optimal interference or noise control.

Abstract: A single-photon detector is disclosed that provides reduced afterpulsing without some of the disadvantages for doing so in the prior art. An embodiment of the present invention provides a stimulus pulse to the active area of an avalanche photodetector to stimulate charges that are trapped in energy trap states to detrap. In some embodiments of the present invention, the stimulus pulse is a thermal pulse.

Abstract: A cross-point switch and cross-point switch fabric utilizing phase change material, and method of operating the same. The cross-point switch includes a phase change cross-point circuit containing a plurality of terminal nodes connected to a central node. The connections between the terminal nodes and the central nodes are regulated by phase change switches comprised of a phase change material. The phase change switches being controlled by heating elements capable of melting or crystallizing the phase change material in the phase change switch. The heating elements are operated by a separate heating circuit. Each individual heating element is regulated by an individual transistor.

Abstract: A magnetic memory device includes a magnetoresistive element and a first wiring layer. The magnetoresistive element includes a fixed layer, a recording layer, and a non-magnetic layer interposed therebetween. The first wiring layer extends in a first direction and generates a magnetic field for recording data in the magnetoresistive element. The recording layer includes a base portion extending in a second direction rotated from the first direction by an angle falling within a range of more than 0° to not more than 20°, and first and second projections projecting from the first and second sides of the base portion in a third direction perpendicular to the second direction. The third and fourth sides of the base portion are inclined with respect to the third direction in the same rotational direction as a rotational direction in which the second direction is rotated.

Abstract: A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.

Abstract: A ferromagnetic thin-film based digital memory cell with a memory film of an anisotropic ferromagnetic material and with a source layer positioned on one side thereof so that a majority of conduction electrons passing therefrom have a selected spin orientation to be capable of reorienting the magnetization of the film. A disruption layer is positioned on the other side of the memory film so that conduction electrons spins passing therefrom are substantially random in orientation. The magnitude of currents needed to operate the cell can be reduced using coincident thermal pulses to raise the cell temperature.