Abstract: An electric field read/write head, a method of manufacturing the same, and a data read/write device including the electric field read/write head are provided. The data read/write device includes an electric field read/write head which reads and writes data to and from a recording medium. The electric field read/write head includes a semiconductor substrate, a resistance region, source and drain regions, and a write electrode. The semiconductor substrate includes a first surface and a second surface with adjoining edges. The resistance region is formed to extend from a central portion at one end of the first surface to the second surface. The source region and the drain region are formed at either side of the resistance region and are separated from the first surface. The write electrode is formed on the resistance region with an insulating layer interposed between the write electrode and the resistance region.

Abstract: A circuit including: at least one radio frequency microstrip conductor; and, a least one vanadium oxide region electrically coupled to the at least one radio frequency microstrip conductor; wherein, the at least one vanadium oxide region is substantially conductive in a first temperature range, and substantially non-conductive in a second temperature range.

Abstract: A single-photon detector is disclosed that provides reduced afterpulsing without some of the disadvantages for doing so in the prior art. An embodiment of the present invention provides a stimulus pulse to the active area of an avalanche photodetector to stimulate charges that are trapped in energy trap states to detrap. In some embodiments of the present invention, the stimulus pulse is a thermal pulse.

Abstract: A separated MEMS thermal actuator is disclosed which is largely insensitive to creep in the cantilevered beams of the thermal actuator. In the separated MEMS thermal actuator, a inlaid cantilevered drive beam formed in the same plane, but separated from a passive beam by a small gap. Because the inlaid cantilevered drive beam and the passive beam are not directly coupled, any changes in the quiescent position of the inlaid cantilevered drive beam may not be transmitted to the passive beam, if the magnitude of the changes are less than the size of the gap.

Abstract: An integrated circuit package may include a substrate and an integrated circuit. The substrate may include at least one region, and a first magnetic material associated with the at least one region. The integrated circuit may have a second magnetic material associated therewith. The second magnetic material may be attracted to the first magnetic material to coupled the integrated circuit to the at least one region of the substrate. The IC package may be utilized in an RFID tag of an RFID system. An associated method for assembling an integrated circuit to a substrate is also provided.

Abstract: A circuit including: at least one conductor; a least one vanadium oxide region electrically coupled to the at least one conductor; and, at least one thermionic cooler thermally coupled to the vanadium oxide region; wherein, the thermionic cooler is suitable for transitioning the at least one vanadium oxide region from a first temperature range where the at least one vanadium oxide region is substantially conductive to a second temperature range where the at least one vanadium oxide region is substantially non-conductive.

Abstract: According to some embodiments, a conducting layer is formed on a first wafer. An insulating layer is formed on a second wafer. The insulating layer includes a cavity and a conducting area may be formed in the second wafer proximate to the cavity. The side of the conducting layer opposite the first wafer is bonded to the side of the insulating layer opposite the second wafer. At least some of the first wafer is then removed, without removing at least some of the conducting layer, to form a conducting diaphragm that is substantially parallel to the second wafer. In this way, an amount of capacitance between the diaphragm and the conducting area may be measured to determine an amount of pressure being applied to the diaphragm.

Abstract: According to some embodiments, a conducting layer is formed on a first wafer. An insulating layer is formed on a second wafer. The insulating layer includes a cavity and a conducting area may be formed in the second wafer proximate to the cavity. The side of the conducting layer opposite the first wafer is bonded to the side of the insulating layer opposite the second wafer. At least some of the first wafer is then removed, without removing at least some of the conducting layer, to form a conducting diaphragm that is substantially parallel to the second wafer. In this way, an amount of capacitance between the diaphragm and the conducting area may be measured to determine an amount of pressure being applied to the diaphragm.

Abstract: A spintronics element comprises two ferromagnetic layers without a non-magnetic interlayer between them. The two ferromagnetic layers may be independently switched by various means such as but not limited to applying one or more external magnetic fields, and/or employing current induced switching, and/or applying optical spin-pumping.

Abstract: A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.

Abstract: An integrated sensor has a magnetic field sensing element and first and second relatively high magnetically permeable members forming a gap, wherein the magnetic field element is disposed within the gap. The magnetically permeable members provide an increase in the flux experienced by the magnetic field sensing element in response to a magnetic field. The integrated sensor can be used as a current sensor, a proximity detector, or a magnetic field sensor.

Abstract: The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed write conductor, the write conductor itself formed within a trench of an insulating layer. The present invention protects the MTJ from the voltages created by the write conductor by isolating the write conductor and enabling the reduction of current necessary to write a bit of information.

Abstract: A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.

Abstract: An electronic component includes a semiconductor chip with a chip topside, an integrated circuit, and a chip backside. The chip backside includes a magnetic layer. The electronic component further includes a chip carrier with a magnetic layer on its carrier topside. At least one of the two magnetic layers is permanently magnetic such that the semiconductor chip is magnetically fixed on the chip carrier.

Abstract: A Hall sensor on a semiconductor substrate includes a Hall plate in the semiconductor substrate, where the Hall plate includes a first zone having a first conduction type. The semiconductor substrate also include a second zone having a second conduction type. A space-charge zone in the semiconductor substrate separates the first zone and the second zone, first contacts supply a control current to the first zone, and second contacts supply a compensation current to the second zone.

Abstract: A field-effect transistor used as a sensor for measuring a gas or ion concentration utilizes a surface structure such as rings along with surface profiling, for example elevations of the rings and depressions therebetween, to decrease the surface conductivity between a guard ring and the FET, to thereby increase the concentration rise per unit time of a gas signal and increase the time for a potential on a channel region of the FET to approximate the potential on a guard ring. The rings, which may be arranged around the FET structure, may be defined by a surface material different from the remaining surface material and thus having different surface conductivities. The surface profiling, together with the rings, can be utilized to increase an amount of time that may describe the equalization of the channel region potential to the guard ring potential. The elevations may have a surface conductivity different from, for example smaller than, that of the depressions.

Abstract: Methods for directing an optical beam and for making an apparatus for directing an optical beam are described. One such method may include applying a first force to a plate to move the plate from a first angular orientation to a second angular orientation wherein the plate contacts a stop in the second angular orientation. A reflective portion of the plate is stopped from rotating beyond the second angular orientation. A second force can be applied between the plate and the stop to hold the plate against the stop in a plane substantially parallel to a substantially planar surface of the stop. An apparatus for directing an optical beam may be made by coupling an array of plates to a base assembly wherein each plate is movable between a first angular orientation and a second angular orientation.

Abstract: A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7?X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1?XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

Abstract: A magnetic random access memory with lower switching field is provided. The memory includes a first antiferromagnetic layer, a pinned layer formed on the first antiferromagnetic layer, a tunnel barrier layer formed on the pinned layer, a ferromagnetic free layer formed on the tunnel barrier layer, and a multi-layered metal layer. The multi-layered metal layer is formed by at least one metal layer, where the direction of the anisotropy axis of the antiferromagnetic layer and the ferromagnetic layer and that of the ferromagnetic free layer are arranged orthogonally. The provided memory has the advantage of lowering the switching field of the ferromagnetic layer, and further lowering the writing current.

Abstract: An etchant including C2HxFy, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six, etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture. The invention also includes semiconductor devices that include structures that have been patterned with an etchant of the present invention or in accordance with the method of the present invention. Specifically, the present invention includes semiconductor devices including doped silicon oxide structures with substantially vertical sidewalls and adjacent undoped silicon oxide or silicon nitride structures exposed adjacent the sidewall.

Abstract: A thermoelectric cooling and heating device including a substrate, a plurality of thermoelectric elements arranged on one side of the substrate and configured to perform at least one of selective heating and cooling such that each thermoelectric element includes a thermoelectric material, a Peltier contact contacting the thermoelectric material and forming under electrical current flow at least one of a heated junction and a cooled junction, and electrodes configured to provide current through the thermoelectric material and the Peltier contact. As such, the thermoelectric cooling and heating device selectively biases the thermoelectric elements to provide on one side of the thermolectric device a grid of localized heated or cooled junctions.

Abstract: A method of forming a magneto-resistive memory element includes forming a groove in a layer of insulating material. A liner is formed conformably within the groove and the groove is filled with copper and then planarized. The electrically conductive material is provided an upper surface that is recessed relative to the upper surface of the layer of insulating material. A cap, which can be conductive (e.g., Ta) or resistive (e.g., TiAIN), is disposed over the electrically conductive material and within the groove. A surface of the cap that faces away from the electrically conductive material, is formed with an elevation substantially equal to that of the edge of the liner, or the cap can extend over the liner edge. At least one layer of magneto-resistive material is disposed over a portion of the cap. Advantageously, the cap can protect the copper line from harmful etch processes required for etching a MRAM stack, while keeping the structure planar after CMP.

Abstract: An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential. Such an embodiment also includes a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potential.

Abstract: An optical device includes a semiconductor substrate having an opening, a support member disposed on the substrate, and a movable portion disposed on the opening of the substrate. The movable portion is supported by the support member so that the movable portion is movable. The device has a large scanning angle. Further, the device can scan widely at any frequency.

Abstract: A semiconductor component, in particular a micromechanical pressure sensor based on silicon, having a base layer, an at least largely self-supporting diaphragm and an overlayer situated on the diaphragm, the diaphragm and the base layer, at least from place to place, delimiting a void. Furthermore, at least from place to place, above the diaphragm a conducting region is provided in the overlayer which is electrically poorly conductive as compared to the conducting region, to which the surface of the diaphragm that faces the overlayer is able to be electrically contacted.

Abstract: A method for contacting an electrically conductive electrode overlying a first dielectric material of a structure is provided. The method includes forming a mask layer overlying the electrically conductive electrode and patterning the mask layer to form an exposed electrically conductive electrode material. At least a portion of the exposed electrically conductive electrode material is removed while an electrically conductive veil is formed adjacent the mask layer. A metal contact layer is formed such that said metal contact layer contacts the electrically conductive veil.

Abstract: A semiconductor device including a semiconductive body having formed therein an active region and a termination feature which includes spaced field rings disposed around the active region and diffusion rings of the same conductivity type as, but different conductivity than the semiconductive body formed between each pair of field rings.

Abstract: Tensile or compressive stress may be added in one or more selected locations to the biaxial residual stress existing in the channel of a semiconductor device, such as a MOSFET. The periphery of the active area containing the channel is modified by following layout procedures that result in forming outward protrusions of or inward depressions in the periphery of the active area and its surrounding shallow trench isolation during generally otherwise conventional fabrication of the device.

Abstract: An exemplary nonvolatile memory array comprises a substrate and a plurality of memory cells formed on the substrate, each of the memory cells being addressable via at least first and second conductors during operations. An exemplary memory cell in the exemplary memory array includes a ferromagnetic annular data layer having an opening, the opening enabling the second conductor to electrically contact the first conductor, an intermediate layer on at least a portion of the annular data layer, and a soft reference layer on at least a portion of the intermediate layer.

Abstract: The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed write conductor, the write conductor itself formed within a trench of an insulating layer. The present invention protects the MTJ from the voltages created by the write conductor by isolating the write conductor and enabling the reduction of current necessary to write a bit of information.

Abstract: A magnetic sensor device formed using SOI CMOS techniques includes a substrate, a silicon oxide layer and in some cases a plurality of gated regions. A first terminal is located between two innermost gated regions and supplies a supply voltage. A second and a third terminal, each of which is located between two adjacent gated regions other than the two innermost gated regions, output positive and negative Hall voltages. By appropriately controlling a bias voltage to the gated regions, small changes in a magnetic field induces larger currents in channel regions under the gated regions, which, in turn, results in detectable Hall voltages.

Abstract: A method for making a solid-state imaging device that can form a first P-type well region deep in a substrate without being affected by the heat applied during an epitaxial growth process is disclosed. The method includes a first step of preparing a substrate composite comprising an first substrate and a second substrate on the first substrate, a second step of implanting impurity ions from the surface of the second substrate at an energy exceeding 3 MeV so as to form a barrier layer, and a third step of forming a photosensor in the second substrate.

Abstract: An electronic packaging structure and method of forming thereof wherein the structure is constituted of a modular arrangement which reduces stresses generated in a chip, underfill, and ball grid array connection with a flexible substrate in the form of an organic material, which stresses may result in potential delamination due to thermally-induced warpage between the components of the modular arrangement.

Abstract: A ferromagnetic thin-film based digital memory cell with a memory film of an anisotropic ferromagnetic material and with a source layer positioned on one side thereof so that a majority of conduction electrons passing therefrom have a selected spin orientation to be capable of reorienting the magnetization of the film. A disruption layer is positioned on the other side of the memory film so that conduction electrons spins passing therefrom are substantially random in orientation. The magnitude of currents needed to operate the cell can be reduced using coincident thermal pulses to raise the cell temperature.

Abstract: A structure and method for creating a contact between a conductive layer and a pad for dissipating electrostatic charges comprising the steps of, forming a pad and a composite insulating layer between and over conductive plates on a substrate, wherein the insulating layer isolates and protects the conductive plates and pad from damage, the insulating layer comprising a dielectric region underlying a conductive layer. A passivation layer is formed over at least a portion of the conductive layer and a photoresist is patterned over at least a portion of the passivation. An opening is etched through the passivation and the insulating layers, wherein the photoresist and the conductive layer serve as masks. Finally, a conductive material is deposited in the opening to form an electrical contact between the pad and the conductive layer.

Abstract: A hybridized Lead-Salt infrared radiation detector includes a focal plane having a substrate and a sensitized, delineated Lead-Salt layer upon the substrate, the delineations forming a plurality of sections in a two-dimensional array. The detector also includes electrical contacts for each of the sections and a common grid between the sections. The detector further includes a layer of conductive barrier material on each electrical contact, a layer of passivating material on each section, and a layer of fusible conductive material on each layer of conductive barrier material.

Abstract: A semiconductor laser diode module in which a laser diode and an optical fiber are optically coupled with each other efficiently irrespective of an ambient temperature change within the laser diode module. The laser diode module includes a laser diode, an optical system including an optical fiber and a lens portion, a base configured to support the laser diode and at least a portion of the optical system, and a bottom plate configured to support the laser diode, the optical system, and the base. The optical system is configured to receive and transmit a beam emitted from the laser diode through the lens portion to the optical fiber along an optical axis. The base includes a structural support member configured to prevent warping of the base, where the structural support member extends along the base in a direction generally parallel to the optical axis.

Abstract: A cladded conductive interconnect for programming a magnetoresistive memory device which includes a conductive material with a length, a first barrier conductive material positioned on the conductive material, and a multi-layer cladding region positioned along the length of the conductive material wherein the multi-layer cladding region includes N ferromagnetic layers, where N is a whole number greater than or equal to two, and wherein the multi-layer cladding region further includes at least one spacer layer, wherein the spacer layer can include a metal, an insulator, or an exchange interaction material, and wherein the spacer layer is sandwiched therebetween each adjacent ferromagnetic layer.

Abstract: A high gain phototransistor uses lateral and vertical transistor structures and a triple base. The base regions of two vertical structures are in the bulk of a semiconductor substrate while the base of a single lateral structure is adjacent a light receiving phototransistor surface. Minority carrier generation extends from the base region of the lateral transistor to the base regions of the vertical transistors and is present in the vertical regions within a diffusion length of the optically generated carriers of the lateral base. The bases of all three transistor structures are electrically connected. The collector electrodes of one of the vertical structures and the lateral structure are electrically connected, while the emitter electrodes of the other of the vertical structures and the lateral structures are electrically connected. Finally, the remaining vertical collector and emitter electrodes are electrically connected via a buried layer adjacent the phototransistor wafer substrate.

Abstract: Provided a pressure-contact type semiconductor device including: a plurality of semiconductor chips; a heat buffer plate provided on one surface side of the plural semiconductor chips; and a metal electrode plate provided on the heat buffer plate on a side opposite the plural semiconductor chips, a surface thereof at any position not facing the plural semiconductor chips on the heat buffer plate side having a region which alleviates elastic deformation of the heat buffer plate. Also provided is a pressure-contact type semiconductor device including: a plurality of semiconductor chips; a heat buffer plate provided on one surface side of the plural semiconductor chips; and a metal electrode plate provided on the heat buffer plate on a side opposite the plural semiconductor chips, a peripheral shape thereof extending beyond and thus being larger than a peripheral shape of the heat buffer plate.

Abstract: A magnetic random access memory (MRAM) array includes a plurality of magnetic tunnel junction (MTJ) memory cells and a plurality of non-electronic switching elements, each MTJ memory cell and an associated switching element being in electrical series connection and located between the bit and word lines of the array. The switching element is a layer of vanadium dioxide, a material that exhibits a first order phase transition at a transition temperature of approximately 65° C. from a low-temperature monoclinic (semiconducting) to a high-temperature tetragonal (metallic) crystalline structure. This phase transition is accompanied by a change in electrical resistance from high resistance at room temperature to low resistance above the transition temperature. To read a memory cell, the vanadium dioxide switching element associated with that cell is heated to lower the resistance of the switching element to allow sense current to pass through the cell, thereby enabling the memory state of the cell to be read.

Abstract: Metal wiring segments, which are located at peripheral positions of a diaphragm, are formed on a main surface of a thick portion of a semiconductor substrate. A ratio S/d is larger than 100, where an area of the diaphragm is S &mgr;m2 and a thickness thereof is d &mgr;m. Further, a total area of the metal wiring segments arranged on first sides of the substrate is larger than total area of the metal wiring segments arranged on second sides of the substrate, where the first sides indicate the sides in parallel with <110> crystalline axis and the second sides indicate the sides in parallel with <100> crystalline axis.

Abstract: A magnetic random access memory (MRAM) with a low write current, characterized in that an improved MRAM structure is composed of a plurality of conductive metal pillars disposed on both sides of a magnetic tunnel junction (MTJ) cell functioning as a memory cell. The conductive metal pillars generate a superposed magnetic field so as to reduce the write current into the MTJ cell, thereby reducing the power consumption during the operation of an MRAM. The metal pillars are formed by employing a modified mask so that a plurality of plugs are formed by via etching and metal deposition. Moreover, at least one turn of conductive metal coil is disposed near the memory cell. The enhanced magnetic field thus generated results in a lowered write current as well as reduced power consumption.

Abstract: A magnetic memory device comprises magneto-resistance elements each including a cylindrical fixed magnetization layer, an insulating film which covers an external surface of the fixed magnetization layer, and a free magnetization layer which faces the fixed magnetization layer through the insulating film and covers a surface of the insulating film, wherein a magnetization direction of the fixed magnetization layer is parallel to a central axis direction of the cylinder.

Abstract: A thermoelectric module is constituted by a pair of substrates having electrodes, which are arranged opposite to each other with a prescribed space therebetween, in which a prescribed number of thermoelectric elements are arranged in such a way that a p-type and an n-type are alternately arranged, so that the thermoelectric elements are connected in series or in parallel together with the electrodes. Herein, one substrate is a heat absorption side, and other substrate is a heat radiation side. In addition, a current density in a current transmission area of the heat-absorption-side electrode is set to 50 A/mm2 or less, and a height of the thermoelectric element is set to 0.7 mm or less. Furthermore, a temperature-controlled semiconductor module can be realized by combining a thermoelectric module with a semiconductor component such as a semiconductor laser.

Abstract: A semiconductor torsional micro-electromechanical (MEM) switch is described having a conductive movable control electrode; an insulated semiconductor torsion beam attached to the movable control electrode, the insulated torsion beam and the movable control electrode being parallel to each other; and a movable contact attached to the insulated torsion beam, wherein the combination of the insulated torsion beam and the control electrode is perpendicular to the movable contact. The torsional MEM switch is characterized by having its control electrodes substantially perpendicular to the switching electrodes. The MEM switch may also include multiple controls to activate the device to form a single-pole, single-throw switch or a multiple-pole, multiple-throw switch. The method of fabricating the torsional MEM switch is fully compatible with the CMOS manufacturing process.

Abstract: A description is given of a switching device (1) comprising a transparent substrate (3), a switching film (5) comprising a hydride of scandium and magnesium, covered with a palladium layer (7). By exchange of hydrogen, the switching film can be reversibly switched from a transparent state to a mirror-like state with zero transmission via an intermediate black absorbing state. The conversion between both states is reversible, and this phenomenon can be used, for example, in an optical switching element or sun roof.

Abstract: A semiconductor component, in particular a micromechanical pressure sensor based on silicon, having a base layer, an at least largely self-supporting diaphragm and an overlayer situated on the diaphragm, the diaphragm and the base layer, at least from place to place, delimiting a void. Furthermore, at least from place to place, above the diaphragm a conducting region is provided in the overlayer which is electrically poorly conductive as compared to the conducting region, to which the surface of the diaphragm that faces the overlayer is able to be electrically contacted.

Abstract: A multi-layer device with a lid, a core, and a base. The lid has a first terminal and a second terminal, and an inner surface with a first insulator. The core has a first surface bonded to the first insulator and a second surface bonded to a second insulator, and includes a pillar electrically connected to the second terminal. The base has an inner surface bonded to the second insulator and a portion being electrically connected to the pillar. The first terminal of the lid and the base are adapted for electrically connecting to an interior electrical unit positioned within the core so that there are conductive paths from the electrical unit to the first and second terminals. The lid can include a third terminal in electrical contact with a portion of the core, and the portion of the core can be adapted for electrically connecting to the electrical unit.

Abstract: A semiconductor device with an inductance element reduces eddy current in a conductive element and secures required inductance. The semiconductor device includes a semiconductor chip and the inductance element of flat structure formed on a surface of the semiconductor chip. The semiconductor chip is fixed to the conductive element, to form a package. The element has a magnetic material to face the semiconductor chip.