Abstract: An electrostatic discharge protection device for protecting a mixed voltage integrated circuit against damage is provided which includes at least on pair of NMOS transistors connected in a cascode configuration. Each NMOS transistor pair includes a first transistor, having a drain region coupled to and I/O stage of the mixed voltage integrated circuit, and a gate region coupled to the mixed voltage integrated circuit's low power supply. The second NMOS transistor of the pair is merged into the same active area as the first transistor and has a gate region and a source region coupled to the ground plane of the mixed voltage integrated circuit. The source region of the first transistor and the drain region of the second transistor are constructed of a shared NMOS diffusion region.

Abstract: A bistable SCR-like switch (41) protects a signal line (65) of an SOI integrated circuit (40) against damage from ESD events. The bistable SCR-like switch (41) is provided by a first and a second transistors (42 and 44) which are formed upon the insulator layer (46) of the SOI circuit (40) and are separated from one another by an insulating region (60). Interconnections (62 and 64) extend between the two transistors (42 and 44) to connect a P region (62) of a first transistor (42) to a P region (54) of the second transistor (44) and an N region (50) of the first transistor (42) to an N region (58) of the second transistor (44). The transistors (42 and 44) may be either bipolar transistors or enhancement type MOSFET transistors. For bipolar transistors, the base of an NPN transistor (42) is connected to the collector of a PNP transistor (44) and the base of the PNP transistor (44) is connected to the collector of the NPN transistor (42).

Abstract: The present invention relates to a bidirectional breakover component including a lightly-doped N-type substrate, an upper P-type region extending over practically the entire upper surface of the component except its circumference, a lower P-type uniform layer on the lower surface side of the component, substantially complementary N-type regions respectively formed in the upper region and in the lower layer, a peripheral P-type well, an overdoped P-type region at the upper surface of the well, and lightly-doped N-type regions between the circumference of the upper region and the well.

Abstract: A segmented SCR ESD protection circuit for discharging an external electrostatic stress on a semiconductor integrated circuit is formed over a semiconductor substrate. The protection circuit includes an SCR device and a number of resistors. The SCR device is separated into a plurality of SCR segments for suppressing the occurrence of the secondary breakdown. Each of the resistors is connected to one of the SCR segments. The resistors can be in the form of parasitic resistances of the SCR device or in the form of additional electronic components formed on the semiconductor substrate.

Abstract: An SCR circuit formed on a semiconductor substrate includes a well region, a first diffusion region and a second diffusion region in the well region, and a third diffusion region in the substrate. The SCR circuit also includes a capacitor connected between the first diffusion region and the third diffusion region. The junction region between the well region and the diffusion region is forward biased when an electrostatic force is applied to the SCR circuit, thereby triggering the SCR circuit to discharge the electrostatic force.

Abstract: The invention provides a Bipolar structure such as a silicon controlled rectifier (SCR) that exhibits advantageously low triggering and holding voltages for use in high speed (e.g., 900 MHz->2 GHz) submicron ESD protection circuits for Bipolar/BiCMOS circuits. The Bipolar structure features a low shunt capacitance and a low series resistance on the input and output pins, allowing for the construction of ESD protection circuits having small silicon area and little to no impedance added in the signal path. In a preferred aspect of the invention, the SCR is assembled in the N-well of the Bipolar/BiCMOS device, as opposed to the P-substrate, as is customary in the prior art. A preferred aspect of the invention utilizes a Zener diode in combination with a resistor to control BSCR operation through the PNP transistor.

Abstract: A gateless thyristor or a gateless triac with shorting holes having a sharp switching threshold and a high current value I.sub.H includes, a first area having a first density of shorting holes and a second area having a second density of shorting holes lower than the first density.

Abstract: An Input/Output (I/O) circuit (11) for an integrated circuit including Electrostatic Discharge Protection (ESD) circuitry is disclosed. A Silicon Controlled Rectifier SCR (30) is triggered by a transistor (36) which is scaled to an output transistor (24) of the I/O circuit (11) to shunt an ESD event. The SCR (30) couples between a pad (12) and a power supply line V.sub.SS. The transistor (36) is disabled. The triggering mechanism is voltage breakdown of the transistor (36) due to an ESD event. The SCR protection mechanism is process independent since the triggering mechanism is formed similarly to the output transistor (24) and thus breaks-down similarly. Zener diodes (26-29) are coupled to gates of the I/O circuit (11) and between the power supply lines. A phosphorous doping less than 5.0 E18 per cubic centimeter is used to form the cathode of zener diodes (26-29).

Abstract: In a device for the protection of integrated circuits against electrostatic discharges, the protection structure comprises a thyristor with an N+ region connected to the ground, a P- substrate, a deep N- well forming a gate region, and a P+ region connected to an external connection pad to be protected. The gate region is connected by a low-value resistor (with a maximum value of a few ohms) to the pad. This resistor increases the current for which the thyristor gets triggered and eliminates certain risks of the destruction of the circuit.

Abstract: A semiconductor device is fabricated which has reduced power dissipation when the device is turned on and runs cooler in surge suppressor applications. This result is achieved by fabricating a device where the breakdown action takes place preferentially under cathode region. The lower power dissipated during the turn-on action enables the device to operate in environmental conditions from -20.degree. C. to 65.degree. C.

Abstract: A protection circuit (40) providing positive and negative stress protection. A lateral PIN (58) assists in the triggering of a silicon-controlled rectifier (60) for positive stress protection. A vertical PNP (62) provides negative stress protection. A Schottky diode 64 may be used for biasing a n-well (44) to prevent latchup.

Abstract: In a breakover type surge protection device utilizing punch-through that comprises a second semiconductor region forming a first pn junction with a first semiconductor region, a third semiconductor region forming a second pn junction with the second semiconductor region and a fourth semiconductor region forming a third pn junction with the first semiconductor region at a place apart from the second semiconductor region, the second semiconductor region is constituted of a punch-through suppression region portion disposed to cover the corners of the third semiconductor region and a punch-through generation region portion disposed at a place where its thickness can be made uniform. Fabricating surge protection devices according to this configuration reduces variation among their breakover currents and hold currents and increases their surge absorption capacity.

Abstract: A thyristor type surge protector having a breakdown voltage V.sub.BO approximately equal to a surge clamping voltage V.sub.CL includes a P-type first semiconductor layer, an N-type second semiconductor layer provided in one surface of the first semiconductor layer, a P-type third semiconductor layer provided in the second semiconductor layer so as to provide at least one first exposed region of the second semiconductor layer, and an N-type fourth semiconductor layer formed in the other surface of the first semiconductor layer so as to provide at least one exposed region of said first semiconductor layer, a first electrode provided over the third semiconductor layer and of the first exposed region, and a second electrode provided over the fourth semiconductor layer and second exposed region.

Abstract: A gateless thyristor or a gateless triac with shorting holes having a sharp switching threshold and a high current value I.sub.H includes, a first area having a first density of shorting holes and a second area having a second density of shorting holes lower than the first density.

Abstract: A thyristor type surge suppressor includes a P-type semiconductor substrate, an N-type first semiconductor layer provided in one surface of the semiconductor substrate, an N-type second semiconductor layer provided in the other surface of the semiconductor substrate, a P-type third semiconductor layer formed in the N-type first semiconductor layer so as to provide a plurality of first exposed regions of the N-type first semiconductor layer, a P-type fourth first semiconductor layer formed in the N-type second semiconductor layer so as to provide a plurality of second exposed regions of the N-type second semiconductor layer, a first electrode provided over the P-type third semiconductor layer and the of N-type first exposed regions, and a second electrode provided over the P-type fourth semiconductor layer and the N-type second exposed regions.

Abstract: The semiconductor protection device has a p.sup.+ -n.sup.- -p-n.sup.+ layer construction, and an n type impurity diffusion region is selectively formed in a surface portion of the pn junction. This n type impurity diffusion region is formed in a linear planar portion where substantially no electric field concentration is generated when a reverse voltage is applied to the pn junction formed between the n.sup.- type semiconductor region and the p type semiconductor region. Further, an electrode is provided in ohmic contact with both of the p type semiconductor region and the n.sup.+ type semiconductor region. This electrode is selectively made in contact with the p type semiconductor region at a position remote from the n type impurity diffusion region and adjacent to a curved planar portion of the pn junction where the electric field concentration tends to occur when a reverse voltage is applied to the pn junction formed between the n.sup.- type semiconductor region and the p type semiconductor region.

Abstract: Disclosed is a piezoelectric type gaslighter equipped with a thumb-latch for preventing an inadvertent fire which may be caused, for instance, when a child plays with a gaslighter. A gaslighter according to the present invention includes an intermediate casing and a piezoelectric unit having a movable operating part. The intermediate casing has a cross slot opening with a thumb-latch slidably fitted therein whereas the movable operating part has a longitudinal slot groove. The piezoelectric unit is properly inserted in the intermediate casing so that the longitudinal slot groove of the movable operating part intersects the cross slot opening of the casing. With this arrangement when the thumb-latch is displaced to the crossing at which the longitudinal slot groove intersects the cross slot opening, the movable operating part can move to strike the piezoelectric element for producing a small flame. Otherwise, the movable operating part is latched.