Having Only Two Terminals And No Control Electrode (gate), E.g., Shockley Diode Patents (Class 257/109)
  • Patent number: 10236378
    Abstract: An integrated electronic device having a semiconductor body including: a first electrode region having a first type of conductivity; and a second electrode region having a second type of conductivity, which forms a junction with the first electrode region. The integrated electronic device further includes a nanostructured semiconductor region, which extends in one of the first and second electrode regions.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: March 19, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Marco Sambi, Fabrizio Fausto Renzo Toia, Marco Marchesi, Marco Morelli, Riccardo Depetro, Giuseppe Barillaro, Lucanos Marsilio Strambini
  • Patent number: 10229972
    Abstract: A semiconductor layer of a first conductivity type has a plurality of impurity concentration peaks that are differently positioned in a first direction extending from a first surface to a second surface, and an integrated concentration obtained by integrating an impurity concentration value in the first direction from (i) the first surface that is a junction interface between the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type to (ii) a boundary between a first impurity concentration peak of the plurality of impurity concentration peaks that is the closest to the first surface and a second impurity concentration peak of the plurality of impurity concentration peaks that is the second closest to the first surface is equal to or lower than a critical integrated concentration.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 12, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tetsutaro Imagawa
  • Patent number: 10211257
    Abstract: A memory cell includes a substrate layer, with a plurality of silicided semiconductor fins stacked on the substrate layer and spaced apart from one another. A first metal liner layer is stacked on the plurality of silicided semiconductor fins and on the substrate layer. A plurality of first contact pillars are stacked on the first metal liner layer adjacent a different respective one of the plurality of silicided semiconductor fins. A configurable resistance structure covers portions of the first metal liner layer that are stacked on the substrate layer and portions of the first metal liner layer that are stacked on each of the plurality of silicided semiconductor fins. A metal fill layer is stacked on the configurable resistance structure. A plurality of second contact pillars is stacked on the metal fill layer adjacent a space between a different pair of adjacent silicided semiconductor fins of the plurality thereof.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Qing Liu, John Hongguang Zhang
  • Patent number: 10176986
    Abstract: A semiconductor device is disclosed in which proton implantation is performed a plurality of times to form a plurality of n-type buffer layers in an n-type drift layer at different depths from a rear surface of a substrate. The depth of the n-type buffer layer, which is provided at the deepest position from the rear surface of the substrate, from the rear surface of the substrate is more than 15 ?m. The temperature of a heat treatment which is performed in order to change a proton into a donor and to recover a crystal defect after the proton implantation is equal to or higher than 400° C. In a carrier concentration distribution of the n-type buffer layer, a width from the peak position of carrier concentration to an anode is more than a width from the peak position to a cathode.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: January 8, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichi Onozawa
  • Patent number: 10177009
    Abstract: A semiconductor device includes: an SiC substrate having a first surface and a second surface; a first conductivity type SiC layer disposed on the first surface side of the SiC substrate, and including a low level density region having Z1/2 level density of 1×1011 cm?3 or less measured by deep level transient spectroscopy (DLTS); a second conductivity type SiC region disposed on a surface of the SiC layer; a first electrode disposed on the SiC region; and a second electrode disposed on the second surface side of the SiC substrate.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: January 8, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Tatsuo Shimizu, Takashi Shinohe
  • Patent number: 10121926
    Abstract: A method for detecting W-band and terahertz radiations is disclosed. The method provides a graphene-Si Schottky diode that includes a graphene monolayer having an Ohmic contact with a source electrode supported on a top surface of a doped silicon substrate by an insulating layer, and extends over an edge of the source electrode and contacts the top surface, in a manner forming a Schottky junction. The method stores reference current-voltage (I-V) characteristics of the Schottky junction in a reverse biased mode, then measures I-V characteristics of the Schottky junction in the reverse biased mode, and detects W-band and terahertz radiation by comparing the measured I-V characteristics of the Schottky junction to the stored reference I-V characteristics.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: November 6, 2018
    Assignees: Shahid Rajaee Teacher Training University
    Inventors: Mina Amirmazlaghani, Farshid Raissi
  • Patent number: 10014288
    Abstract: A semiconductor device includes a semiconductor substrate. A first semiconductor region is over a portion of the semiconductor substrate to a first depth. A second semiconductor region is in the first semiconductor region. A third semiconductor region is in the first semiconductor region. A fourth semiconductor region is outside the first semiconductor region. A fifth semiconductor region is outside the first semiconductor region to a fifth depth, the fifth semiconductor region being adjacent the fourth semiconductor region. A sixth semiconductor region is below the fifth semiconductor region and to a sixth depth. The sixth depth is equal to the first depth. A first electrode is connected to the third semiconductor region. A second electrode is connected to the fourth and fifth semiconductor regions. The fifth semiconductor region is configured to cause an increase in a current during a cathode to anode positive bias operation between the first and second electrodes.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: July 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chih Chiang, Tung-Yang Lin, Ruey-Hsin Liu, Ming-Ta Lei
  • Patent number: 9812566
    Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device that may include an oxide region that comprises a bottom surface; a drain that is positioned between a left drift region and a right drift region and below the bottom surface; wherein the oxide region further comprises a first sloped surface and a second sloped surface; wherein a first angle between the first sloped surface and the bottom surface does not exceed twenty degrees; and wherein a second angle between the second sloped surface and the bottom surface of the oxide region does not exceed twenty degrees.
    Type: Grant
    Filed: July 3, 2016
    Date of Patent: November 7, 2017
    Assignee: TOWER SEMICONDUCTORS LTD.
    Inventors: Sagy Levy, Sharon Levin, David Mistele
  • Patent number: 9601639
    Abstract: A p-type anode layer (2) is provided on an upper surface of an n-type drift layer (1). An n-type cathode layer (3) is provided on a lower surface of the n?-type drift layer (1). An n-type buffer layer (4) is provided between the n?-type drift layer (1) and the n-type cathode layer (3). A peak impurity concentration in the n-type buffer layer (4) is higher than that in the n?-type drift layer (1) and lower than that in the n-type cathode layer (3). A gradient of carrier concentration at a connection between the n?-type drift layer (1) and the n-type buffer layer (4) is 20 to 2000 cm?4.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: March 21, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Fumihito Masuoka, Katsumi Nakamura, Akito Nishii
  • Patent number: 9543428
    Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: January 10, 2017
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Naohiro Suzuki, Masahiro Sugimoto, Hidefumi Takaya, Akitaka Soeno, Jun Morimoto, Narumasa Soejima, Yukihiko Watanabe
  • Patent number: 9524971
    Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: December 20, 2016
    Inventors: Srinivasa R. Banna, Michael A. van Buskirk, Timothy Thurgate
  • Patent number: 9496344
    Abstract: In a JBS diode using a wide band gap semiconductor, the wide band gap semiconductor has a large built-in voltage, which sometimes causes difficulties for the pn diode portion to turn on, resulting in a problem that resistance to surge currents is not sufficiently ensured. In order to solve this problem, in the wide-band-gap JBS diode, a pn junction of the pn diode is formed away from the Schottky electrode, and well regions are formed so as to have a width narrowed at a portion away from the Schottky electrode.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: November 15, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rina Tanaka, Akihiko Furukawa, Masayuki Imaizumi, Yuji Abe
  • Patent number: 9473137
    Abstract: A non-volatile Boolean logic operation circuit, including: two input ends; an output end; a first resistive switching element M1, the first resistive switching element M including a positive electrode and a negative electrode; and a second resistive switching element M2, the second resistive switching element M2 including a positive electrode and a negative electrode. The negative electrode of the first resistive switching element M1 operates as a first input end of the logic operation circuit. The negative electrode of the second resistive switching element M2 operates as a second input end of the logic operation circuit. The positive electrode of the second resistive switching element M2 is connected to the positive electrode of the first resistive switching element M1, and a connected end thereof operates as the output end of the logic operation circuit.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: October 18, 2016
    Assignee: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Xiangshui Miao, Yaxiong Zhou, Yi Li, Huajun Sun
  • Patent number: 9423580
    Abstract: An ESD protection device for an electro-optical device may include an optical waveguide segment being in semiconductor material and including a central zone of a first conductivity type, and first and second wings of a second conductivity type different from the first conductivity type and being integral with the central zone. The ESD protection device may include a first conduction terminal on the first wing for defining a first protection terminal, a second conduction terminal on the second wing for defining a second protection terminal, and a resistive contact structure of the first conductivity type having a transverse arm integral with the central zone, and an end in ohmic contact with the first conduction terminal, the resistive contact structure being electrically insulated from the first wing.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: August 23, 2016
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Jean-Robert Manouvrier, Estelle Batail
  • Patent number: 9391189
    Abstract: A lateral semiconductor device and/or design including a space-charge generating layer and a set of electrodes located on an opposite side of a device channel as contacts to the device channel is provided. The space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the contacts to the device channel.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: July 12, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Mikhail Gaevski, Michael Shur, Remigijus Gaska
  • Patent number: 9337423
    Abstract: An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: May 10, 2016
    Assignee: Nantero Inc.
    Inventors: Eliodor G. Ghenciu, Thomas Rueckes, Thierry Yao, J. Thomas Kocab
  • Patent number: 9263515
    Abstract: A semiconductor chip has an n+-doped substrate, above which an n-doped epilayer having trenches is introduced, the trenches being filled with p-doped semiconductor material and in each case having a highly p-doped region at their top side, such that an alternating arrangement of n-doped regions having a first width and p-doped regions having a second width is present. A first metal layer functioning as an anode is provided on the front side of the chip and forms a Schottky contact with the n-doped epilayer and forms an ohmic contact with the highly p-doped regions. A second metal layer which represents an ohmic contact and functioning as a cathode is formed on the rear side of the semiconductor chip. A dielectric layer is provided between each n-doped region and an adjacent p-doped region.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: February 16, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventors: Ning Qu, Alfred Goerlach
  • Patent number: 9257353
    Abstract: Integrated circuits that include bi-directional protection diode structures are disclosed. In one example, an integrated circuit includes a test circuit portion for testing the functionality of the integrated circuit during or after fabrication of the integrated circuit. The test circuit portion includes first, second, and third diode structures and a resistor structure. The first and third diode structures are in parallel with one another and in series with the resistor, and the resistor and the first and third diode structures are in series with the second diode structure. The first and third diode structures are configured for current flow in a first direction and the second diode structure is configured for current flow in a second direction that is opposite the first direction.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: February 9, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Ricardo Pablo Mikalo, Uwe Dersch
  • Patent number: 9041143
    Abstract: The semiconductor device includes a first semiconductor layer of the first conductive type, a second semiconductor layer having the cubic crystalline structure formed on the first semiconductor layer, an electrode formed on the second semiconductor layer, and a reactive region formed between the second semiconductor layer and the electrode. The second semiconductor layer includes an upper surface that is tilted from the (100) plane. The reactive region includes at least one element constituting the second semiconductor layer, at least one element constituting the electrode, and forming a protuberance extending toward the second semiconductor layer.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukie Nishikawa, Nobuhiro Takahashi, Hironobu Shibata
  • Patent number: 9006746
    Abstract: A Schottky barrier diode and a method of manufacturing the diode are provided. The diode includes an n? type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate and a plurality of p+ regions disposed within the n? type epitaxial layer. An n+ type epitaxial layer is disposed on the n? type epitaxial layer, a Schottky electrode is disposed on the n+ type epitaxial layer, and an ohmic electrode is disposed on a second surface of the n+ type silicon carbide substrate. The n+ type epitaxial layer includes a plurality of pillar parts disposed on the n? type epitaxial layer and a plurality of openings disposed between the pillar parts and that expose the p+ regions. Each of the pillar parts includes substantially straight parts that contact the n? type epitaxial layer and substantially curved parts that extend from the substantially straight parts.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: April 14, 2015
    Assignee: Hyundai Motor Company
    Inventors: Youngkyun Jung, Dae Hwan Chun, Kyoung-Kook Hong, Jong Seok Lee, Junghee Park
  • Patent number: 9006863
    Abstract: A diode string voltage adapter includes diodes formed in a substrate of a first conductive type. Each diode includes a deep well region of a second conductive type formed in the substrate. A first well region of the first conductive type formed on the deep well region. A first heavily doped region of the first conductive type formed on the first well region. A second heavily doped region of the second conductive type formed on the first well region. The diodes are serially coupled to each other. A first heavily doped region of a beginning diode is coupled to a first voltage. A second heavily doped region of each diode is coupled to a first heavily doped region of a next diode. A second heavily doped region of an ending diode provides a second voltage. The deep well region is configured to be electrically floated.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Peng Hsieh, Jaw-Juinn Horng
  • Patent number: 9000479
    Abstract: According to one embodiment, a semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes a first second conductivity type region, and a second second conductivity type region. The first second conductivity type region is provided between the first trenches. The second second conductivity type region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiko Kitagawa
  • Publication number: 20150084092
    Abstract: An overvoltage protection component may be in a SOI layer, a portion of the SOI layer forming the core of an optical waveguide. This component may be made of semiconductor regions of different doping types and/or levels, at least one of these regions corresponding to at least a portion of the waveguide core.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 26, 2015
    Inventor: Pascal FONTENEAU
  • Patent number: 8969142
    Abstract: An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: March 3, 2015
    Assignee: Nantero Inc.
    Inventors: Eliodor G. Ghenciu, Thomas Rueckes, Thierry Yao, J. Thomas Kocab
  • Patent number: 8923666
    Abstract: Embodiments of the present invention provide an electrically controlled optical fuse. The optical fuse is activated electronically instead of by the light source itself. An applied voltage causes the fuse temperature to rise, which induces a transformation of a phase changing material from transparent to opaque. A gettering layer absorbs excess atoms released during the transformation.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Raghavasimhan Sreenivasan
  • Publication number: 20140346559
    Abstract: In a first embodiment, an ultra-fast breakover diode has a turn on time TON that is less than 0.3 microseconds, where the forward breakover voltage is greater than +400 volts and varies less than one percent per ten degrees Celsius change. In a second embodiment, a breakover diode has a reverse breakdown voltage that is greater, in absolute magnitude, than the forward breakover voltage, where the forward breakover voltage is greater than +400 volts. In a third embodiment, a string of series-connected breakover diode dice is provided, along with a resistor string, in a packaged circuit. The packaged circuit acts like a single breakover diode having a large forward breakover voltage and a comparably large reverse breakdown voltage, even though the packaged circuit includes no discrete high voltage reverse breakdown diode. The packaged circuit is usable to supply a triggering current to a thyristor in a voltage protection circuit.
    Type: Application
    Filed: August 5, 2014
    Publication date: November 27, 2014
    Inventor: Subhas Chandra Bose Jayappa Veeramma
  • Patent number: 8841697
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a first trench and a second trench in an n-type substrate surface, the first trenches being spaced apart from each other, the second trench surrounding the first trenches, the second trench being wider than the first trench. The method also includes forming a gate oxide film on the inner surfaces of the first and second trenches, and depositing an electrically conductive material to the thickness a half or more as large as the first trench width. The method further includes removing the electrically conductive material using the gate oxide film as a stopper layer, forming an insulator film thicker than the gate oxide film, and polishing the insulator film by CMP for exposing the n-type substrate and the electrically conductive material in the first trench.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: September 23, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Tomonori Mizushima
  • Patent number: 8841696
    Abstract: An SCR includes a first doped region of a first type having a first doping concentration. A first well of the first type and a first well of a second type are disposed in upper areas of the first doped region of the first type such that the first well of the second type is laterally spaced from the first well of the first type by a non-zero distance. A second doped region of the first type has a second doping concentration that is greater than the first doping concentration and is disposed in the first well of the second type to form an anode of the SCR. A first doped region of the second type is disposed in the first well of the first type and forms a cathode of the SCR.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jam-Wem Lee, Yi-Feng Chang
  • Patent number: 8835975
    Abstract: In a first embodiment, an ultra-fast breakover diode has a turn on time TON that is less than 0.3 microseconds, where the forward breakover voltage is greater than +400 volts and varies less than one percent per ten degrees Celsius change. In a second embodiment, a breakover diode has a reverse breakdown voltage that is greater, in absolute magnitude, than the forward breakover voltage, where the forward breakover voltage is greater than +400 volts. In a third embodiment, a string of series-connected breakover diode dice is provided, along with a resistor string, in a packaged circuit. The packaged circuit acts like a single breakover diode having a large forward breakover voltage and a comparably large reverse breakdown voltage, even though the packaged circuit includes no discrete high voltage reverse breakdown diode. The packaged circuit is usable to supply a triggering current to a thyristor in a voltage protection circuit.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: September 16, 2014
    Assignee: IXYS Corporation
    Inventor: Subhas Chandra Bose Jayappa Veeramma
  • Patent number: 8836072
    Abstract: A semiconductor system is described, which includes a trench junction barrier Schottky diode having an integrated p-n type diode as a clamping element, which is suitable for use in motor vehicle generator system, in particular as a Zener diode having a breakdown voltage of approximately 20V. In this case, the TJBS is a combination of a Schottky diode and a p-n type diode. Where the breakdown voltages are concerned, the breakdown voltage of the p-n type diode is lower than the breakdown voltage of Schottky diode. The semiconductor system may therefore be operated using high currents at breakdown.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: September 16, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Ning Qu, Alfred Goerlach
  • Patent number: 8829565
    Abstract: An electrostatic discharge protection device is provided. The electrostatic discharge protection device can include a semiconductor substrate having a first well and a second well, a silicon controller rectifier (SCR) device, and first and second impurity areas disposed on the first and second wells to form a PN junction. The SCR can have a PNPN structure or an NPNP structure, and the PN junction structure and the SCR device can be alternately disposed when the substrate is viewed from above.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 9, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Jae Hyun Yoo, Jong Min Kim
  • Patent number: 8816388
    Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; and a diode forming area adjacent to a forming area of the field effect transistor, wherein the diode forming area is insulated from the forming area of the field effect transistor on the semiconductor substrate, the diode forming area includes an anode electrode and a cathode electrode arranged side by side in a multi-finger shape, and the anode electrode and the cathode electrode are formed in a direction different from directions of a gate electrode, a source electrode, and a drain electrode of the field effect transistor arranged side by side in a multi-finger shape.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu Takada
  • Publication number: 20140231864
    Abstract: An electrostatic discharge protection device is provided. The electrostatic discharge protection device can include a semiconductor substrate having a first well and a second well, a silicon controller rectifier (SCR) device, and first and second impurity areas disposed on the first and second wells to form a PN junction. The SCR can have a PNPN structure or an NPNP structure, and the PN junction structure and the SCR device can be alternately disposed when the substrate is viewed from above.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 21, 2014
    Applicant: DONGBU HITEK CO., LTD.
    Inventors: Jae Hyun YOO, Jong Min KIM
  • Patent number: 8809902
    Abstract: A power semiconductor diode is provided. The power semiconductor diode includes a semiconductor substrate having a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a drift region of the first conductivity type arranged between the first emitter region and the second emitter region. The drift region forms a pn-junction with the second emitter region. A first emitter metallization is in contact with the first emitter region. The first emitter region includes a first doping region of the first conductivity type and a second doping region of the first conductivity type. The first doping region forms an ohmic contact with the first emitter metallization, and the second doping region forms a non-ohmic contact with the first emitter metallization. A second emitter metallization is in contact with the second emitter region.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: August 19, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Holger Huesken, Anton Mauder, Hans-Joachim Schulze, Wolfgang Roesner
  • Patent number: 8796828
    Abstract: A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: August 5, 2014
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Piyush Savalia, Craig Mitchell
  • Patent number: 8796729
    Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: August 5, 2014
    Assignee: Analog Devices, Inc.
    Inventors: David J Clarke, Javier Alejandro Salcedo, Brian B Moane, Juan Luo, Seamus Murnane, Kieran K Heffernan, John Twomey, Stephen Denis Heffernan, Gavin Patrick Cosgrave
  • Patent number: 8779464
    Abstract: A structure for starting a semiconductor component including a porous silicon layer in the upper surface of a semiconductor substrate. This porous silicon layer is contacted, on its upper surface side, by a metallization and, on its lower surface side, by a heavily-doped semiconductor region.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: July 15, 2014
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Samuel Menard
  • Publication number: 20140167100
    Abstract: A semiconductor device including: an FET; a MOSFET having a drain thereof connected with a source of the FET; a resistor having one end thereof connected with a gate of the FET and having the other end thereof connected with a source of the MOSFET; and a diode having an anode thereof connected with the gate of the FET and having a cathode thereof connected with the source of the MOSFET.
    Type: Application
    Filed: February 24, 2014
    Publication date: June 19, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Yuhji ICHIKAWA
  • Publication number: 20140167099
    Abstract: An integrated circuit includes a protected circuit. The integrated circuit further includes a silicon controlled rectifier including a sequence of a first p-type region, a second n-type region, a third p-type region and a fourth n-type region. The first n-type region is electrically coupled to the protected circuit. The integrated circuit further includes a first pn junction diode including a first semiconductor zone and one of the group including the second n-type region and the third p-type region as a second semiconductor zone. A conductivity type of the first semiconductor zone is opposite to the conductivity type of the second semiconductor zone. The integrated circuit further includes a first trigger circuit electrically coupled to the first semiconductor zone.
    Type: Application
    Filed: March 9, 2012
    Publication date: June 19, 2014
    Applicant: QPX GmbH
    Inventor: Markus Paul Josef Mergens
  • Publication number: 20140159102
    Abstract: A high holding voltage (HV) electrostatic discharge (ESD) protection circuit comprises a silicon controlled rectifier (SCR) device and compensation regions located within the length between the anode and cathode (LAC) of the SCR device which increase the holding voltage of the SCR device. The compensation regions may introduce negative feedback mechanisms into the SCR device which may influence the loop gain of the SCR and cause it to reach regenerative feedback at a higher holding voltage.
    Type: Application
    Filed: February 14, 2014
    Publication date: June 12, 2014
    Applicant: SOFICS BVBA
    Inventors: Sven Van Wijmeersch, Olivier Marichal
  • Patent number: 8742450
    Abstract: A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: June 3, 2014
    Assignee: International Rectifier Corporation
    Inventor: Robert Beach
  • Publication number: 20140131763
    Abstract: A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode.
    Type: Application
    Filed: January 17, 2014
    Publication date: May 15, 2014
    Applicant: STMicroelectronics N.V.
    Inventors: Alexei Ankoudinov, Vladimir Rodov
  • Patent number: 8716745
    Abstract: A diode is defined on a die. The diode includes a substrate of P conductivity having an upper surface and a lower surface, the substrate having first and second ends corresponding to first and second edges of the die. An anode contacts the lower surface of the substrate. A layer of N conductivity is provided on the upper surface of the substrate, the layer having an upper surface and a lower surface. A doped region of N conductivity is formed at an upper portion of the layer. A cathode contacts the doped region. A passivation layer is provided on the upper surface of the layer and proximate to the cathode.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: May 6, 2014
    Assignee: IXYS Corporation
    Inventor: Subhas Chandra Bose Jayappa Veeramma
  • Patent number: 8710542
    Abstract: A semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes first and second regions. The first region is provided between the first trenches. The second region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer. The second region has less second conductivity type impurities than the first region.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Tosiba
    Inventor: Mitsuhiko Kitagawa
  • Patent number: 8704270
    Abstract: A Shockley diode including: a vertical stack of first to fourth layers of alternated conductivity types between first and second electrodes; a recess formed in the fourth layer and extending vertically to penetrate into the second layer; a first region of same conductivity type as the second layer but of greater doping level, extending at the bottom of the recess in the second layer; and a second region of same conductivity type as the third layer but of greater doping level, extending along the lateral walls of the recess and connecting the first region to the fourth layer.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: April 22, 2014
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Samuel Menard, Yannick Hague
  • Patent number: 8664690
    Abstract: A bi-directional triode thyristor (TRIAC) device for high voltage electrostatic discharge (ESD) protection may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates and one or more P+ doped plates. The portion of the N-type well region that is interposed between the two P-type well regions may comprise one or more P-type portions, such as a P+ doped plate or a P-type implant.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: March 4, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Shuo-Lun Tu, Wing-Chor Chan, Shyi-Yuan Wu
  • Patent number: 8604515
    Abstract: A bidirectional protection component formed in a semiconductor substrate of a first conductivity type including a first implanted area of the first conductivity type, an epitaxial layer of the second conductivity type on the substrate and the first implanted area, a second area of the first conductivity type on the external side of the epitaxial layer, in front of the first area, and implanted with the same dose as the first area, a first metallization covering the entire lower surface of the substrate, and a second metallization covering the second area.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: December 10, 2013
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Benjamin Morillon
  • Patent number: 8586424
    Abstract: An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: November 19, 2013
    Assignee: Nantero Inc.
    Inventors: Eliodor G. Ghenciu, Thomas Rueckes, Thierry Yao, Thomas Kocab
  • Patent number: 8575647
    Abstract: A mesa-type bidirectional Shockley diode including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; a region of the first conductivity type in each of the layers of the second conductivity type; a buried region of the first conductivity type under each of said regions of the first conductivity type, each buried region being complementary in projection with the other; and a groove arranged in the vicinity of the periphery of the component on each of its surfaces, the component portion external to the groove comprising, under the external portion of the upper and lower regions of the second conductivity type, regions of the first conductivity type of same doping profile as said buried regions.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: November 5, 2013
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Yannick Hague, Samuel Menard
  • Publication number: 20130285112
    Abstract: An SCR includes a first doped region of a first type having a first doping concentration. A first well of the first type and a first well of a second type are disposed in upper areas of the first doped region of the first type such that the first well of the second type is laterally spaced from the first well of the first type by a non-zero distance. A second doped region of the first type has a second doping concentration that is greater than the first doping concentration and is disposed in the first well of the second type to form an anode of the SCR. A first doped region of the second type is disposed in the first well of the first type and forms a cathode of the SCR.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jam-Wem LEE, Yi-Feng CHANG