Abstract: Disclosed is a method of coupling light into a power semiconductor device having a semiconductor structure with two or more layers. The power semiconductor device has multiple cells of functionally identical units linked by multiple interconnects. In each device unit, a patterned electrode layer is disposed on the surface of the semiconductor structure. The method includes illuminating the power semiconductor device by directing a light from a light source through the patterned electrode layer to form an enhanced light coupling with the semiconductor structure. The patterned electrode layer is configured to have a micron scaled grid pattern having multiple metal grids and aperture openings that is based on a distributed resistance model having two characteristic current decay lengths.

Abstract: A system and method utilizing thyristor-based Photo-Conductive Semiconductor Switches (PCSS) for short pulse switching in high power microwave and/or broadband electromagnetic pulse generation is disclosed. The PCSS consists of thyristor-type NPNP structure having multiple emitter regions enclosed by the base region and multiple emitter shorts to divert leakage currents for voltage holding. The PCSS also includes an optical aperture comprised of patterned metallic grids for light illumination and current collection. The device structure is so constructed that there is only one single bevel around the peripheral. The thyristor-based PCSS have dual polarities of voltage blocking and have better efficiency for light requirement to operate at longer pulse duration compared to diode-based and bulk-semiconductor-based PCSS.

Abstract: A solid-state image pickup device includes a plurality of pixels, each of the pixels including a photoelectric conversion portion, a charge holding portion, a floating diffusion, and a transfer portion. The pixel also includes a beneath-holding-portion isolation layer and a pixel isolation layer. An end portion on a photoelectric conversion portion side of the pixel isolation layer is away from the photoelectric conversion portion compared to an end portion on a photoelectric conversion portion side of the beneath-holding-portion isolation layer, and an N-type semiconductor region constituting part of the photoelectric conversion portion is disposed under at least part of the beneath-holding-portion isolation layer.

Abstract: Between a back surface electrode and an electrode, a first thyristor is formed of fifth and seventh semiconductor regions, a substrate region, first and second semiconductor regions and a third semiconductor region, and a second thyristor is formed of the second and first semiconductor regions, the substrate region, the seventh and fifth semiconductor regions and a sixth semiconductor region. Depths from the surface of the semiconductor substrate to bottom surfaces of the third and fourth semiconductor regions are 20 ?m or more. The second semiconductor region with a high impurity concentration is enclosed by the first semiconductor region with a low impurity concentration, and a difference between a depth from the surface of the semiconductor substrate to the bottom of the second semiconductor region and a depth from the surface of the semiconductor substrate to the bottom of the first semiconductor region is less than 10 ?m.

Abstract: A thyristor includes a base region, a pair of first doping regions, at least one second doping region, at least one third doping region, and a pair of metal layers. The first doping regions are formed in two opposite sides of the base region and touch the base region. The second doping region is formed between the base region and one of the first doping regions. The second doping region touches the base region and the first doping region. The third doping region is formed in one of the first doping regions and touches the first doping region. The type of the first doping region is different from the types of the second doping region, the third doping region, and the base region. The metal layers touch the first doping regions respectively. The first doping regions and the third doping region are located between the metal layers.

Abstract: Various embodiments provide materials and methods for integrating exemplary heterostructure field-effect transistor (HFET) driver circuit or thyristor driver circuit with LED structures to reduce or eliminate resistance and/or inductance associated with their conventional connections.

Abstract: A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.

Abstract: Preferred embodiments of the invention include a thyristor core that is single biased by a source, such as a power source (or a portion thereof) that is being switched through the thyristors. An optically activated transistor that is preferably a minority carrier device is in series with the thyristor core. The thyristor core has an optically activated gate. The turn-off of the thyristor can be accelerated by the turn-on (conduction state) of a gate switch, which ensures a unity gain turn-off of the core thyristor.

Abstract: A light-emitting chip includes plural light-emitting thyristors having a first anode terminal, a first cathode terminal, and a first gate terminal, plural setting thyristors having a second anode terminal, a second cathode terminal, and a second gate terminal and setting the absolute value of a threshold voltage of each light-emitting thyristor to be smaller than that in an OFF state, plural transmission thyristors having a third anode terminal, a third cathode terminal, and a third gate terminal and setting the absolute value of a threshold voltage of each setting thyristor to be smaller than that in an OFF state, plural first connecting resistors connecting the first gate terminals and the second gate terminals, plural second connecting resistors connecting the second gate terminals and the third gate terminals, and plural third connecting resistors connecting the first gate terminals to a power supply line supplied with a source potential.

Abstract: An integrated circuit (IC) having a microelectromechanical system (MEMS) device buried therein is provided. The integrated circuit includes a substrate, a metal-oxide semiconductor (MOS) device, a metal interconnect, and the MEMS device. The substrate has a logic circuit region and a MEMS region. The MOS device is located on the logic circuit region of the substrate. The metal interconnect, formed by a plurality of levels of wires and a plurality of vias, is located above the substrate to connect the MOS device. The MEMS device is located on the MEMS region, and includes a sandwich membrane located between any two neighboring levels of wires in the metal interconnect and connected to the metal interconnect.

Abstract: A memory cell includes a thyristor having a plurality of alternately doped, vertically superposed semiconductor regions; a vertically oriented access transistor having an access gate; and a control gate operatively laterally adjacent one of the alternately doped, vertically superposed semiconductor regions. The control gate is spaced laterally of the access gate. Other embodiments are disclosed, including methods of forming memory cells and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor.

Abstract: A photodiode element includes a first layer of a first diffusion type and a second layer. The second layer defines a charge-collecting area. The charge-collecting area includes an active region of a second diffusion type and an inactive region. The active region surrounds the inactive region. The photodiode element also includes an intrinsic semiconductor layer between the first layer and the second layer.

Abstract: A thyristor device includes a semiconductor body and a conductive anode. The semiconductor body has a plurality of doped layers forming a plurality of dopant junctions and includes an optical thyristor, a first amplifying thyristor, and a switching thyristor. The conductive anode is disposed on a first side of the semiconductor body. The optical thyristor is configured to receive incident radiation to generate a first electric current, and the first amplifying thyristor is configured to increase the first electric current from the optical thyristor to at least a threshold current. The switching thyristor switches to the conducting state in order to conduct a second electric current from the anode and through the semiconductor body.

Abstract: A thyristor device includes a semiconductor body and a conductive anode. The semiconductor body has a plurality of doped layers forming a plurality of dopant junctions and includes an optical thyristor, a first amplifying thyristor, and a switching thyristor. The conductive anode is disposed on a first side of the semiconductor body. The optical thyristor is configured to receive incident radiation to generate a first electric current, and the first amplifying thyristor is configured to increase the first electric current from the optical thyristor to at least a threshold current. The switching thyristor switches to the conducting state in order to conduct a second electric current from the anode and through the semiconductor body.

Abstract: An embodiment of a power device having a first current-conduction terminal, a second current-conduction terminal, a control terminal receiving, in use, a control voltage of the power device, and a thyristor device and a first insulated-gate switch device coupled in series between the first and the second conduction terminals; the first insulated-gate switch device has a gate terminal coupled to the control terminal, and the thyristor device has a base terminal. The power device is further provided with: a second insulated-gate switch device, coupled between the first current-conduction terminal and the base terminal of the thyristor device, and having a respective gate terminal coupled to the control terminal; and a Zener diode, coupled between the base terminal of the thyristor device and the second current-conduction terminal so as to enable extraction of current from the base terminal in a given operating condition.

Abstract: A bipolar power semiconductor component configured as an IGBT includes a semiconductor body, in which a p-doped emitter, an n-doped base, a p-doped base and an n-doped main emitter are arranged successively in a vertical direction. The p-doped emitter has a number of heavily p-doped zones having a locally increased p-type doping.

Abstract: A system and methods are provided for triggering an operating device. In one embodiment, a triggering device includes a receiving unit configured to receive one or more wireless control signals. The receiving unit may include a switch and a processor, wherein the processor is configured to control the switch for activation of an operating device coupled to a signaling line based, at least in part, on the one or more wireless control signals. According to another embodiment, the triggering device may include a connector configured to electrically couple the receiving unit to the signaling line, the connector having one or more contacts and a housing configured to clasp the signaling line and couple the one or more contacts to the signaling line. Additionally, the signaling line may relate to existing wiring of the operating device.

Abstract: The present invention improves the performance of a semiconductor device formed with a triac. A thyristor is formed between a back surface electrode and an electrode by p-type semiconductor regions, an n-type substrate region, p-type semiconductor regions and an n-type semiconductor region. A thyristor is formed therebetween by the p-type semiconductor regions, the n-type substrate region, the p-type semiconductor regions and an n-type semiconductor region. The two thyristors are opposite in the direction of currents flowing between the back surface electrode and the electrode. The p-type semiconductor region of a high impurity concentration is formed so as to be internally included in the p-type semiconductor region of a low impurity concentration. The p-type semiconductor region of a low impurity concentration is interposed between the p-type semiconductor region of a high impurity concentration and the n-type substrate region.

Abstract: In order to protect an integrated circuit provided with a cryptoprocessor from attacks aiming to reveal secrets, it is anticipated to use a component sensitive to the activation of a parasitic (latchup) thyristor and/or to the activation of a parasitic bipolar transistor, or to design a circuit having this property. If the component is stressed due to the presence of this circuit, it is immediately deactivated, actually preventing the revelation of the secrets thereof.

Abstract: The light-emitting element chip includes: a substrate; a light-emitting portion including plural light-emitting elements each having a first semiconductor layer that has a first conductivity type and that is stacked on the substrate, a second semiconductor layer that has a second conductivity type and that is stacked on the first semiconductor layer, the second conductivity type being a conductivity type different from the first conductivity type, a third semiconductor layer that has the first conductivity type and that is stacked on the second semiconductor layer, and a fourth semiconductor layer that has the second conductivity type and that is stacked on the third semiconductor layer; and a controller including a logical operation element that performs logical operation for causing the plural light-emitting elements to perform a light-emitting operation, the logical operation element being formed by combining some sequential layers of the first, second, third and fourth semiconductor layers.

Abstract: Preferred embodiments of the invention include a thyristor core that is single biased by a source, such as a power source (or a portion thereof) that is being switched through the thyristors. An optically activated transistor that is preferably a minority carrier device is in series with the thyristor core. The thyristor core has an optically activated gate. The turn-off of the thyristor can be accelerated by the turn-on (conduction state) of a gate switch, which ensures a unity gain turn-off of the core thyristor.

Abstract: A semiconductor device includes a direct light-triggered thyristor triggered by an optical gate signal, a first optical fiber connected to the direct light-triggered thyristor and through which the optical gate signal is transmitted, a second optical fiber used to extend the first optical fiber, and a inter-optical-fiber relaying unit configured to connect the first optical fiber to the second optical fiber and to input the optical gate signal output from the second optical fiber to the first optical fiber.

Abstract: The light-emitting element chip includes: a substrate; a light-emitting portion including plural light-emitting elements each having a first semiconductor layer that has a first conductivity type and that is stacked on the substrate, a second semiconductor layer that has a second conductivity type and that is stacked on the first semiconductor layer, the second conductivity type being a conductivity type different from the first conductivity type, a third semiconductor layer that has the first conductivity type and that is stacked on the second semiconductor layer, and a fourth semiconductor layer that has the second conductivity type and that is stacked on the third semiconductor layer; and a controller including a logical operation element that performs logical operation for causing the plural light-emitting elements to perform a light-emitting operation, the logical operation element being formed by combining some sequential layers of the first, second, third and fourth semiconductor layers.

Abstract: The present invention is a semiconductor light emitting device including an n-type semiconductor layer, an active layer, a first p-type semiconductor layer between the n-type semiconductor layer and the active layer, and a second p-type semiconductor layer on the opposite side of the first p-type semiconductor layer from the active layer. Further, the present invention is a nitride semiconductor light emitting device including an n-type nitride semiconductor layer, a nitride semiconductor active layer, a first p-type nitride semiconductor layer between the n-type nitride semiconductor layer and the nitride semiconductor active layer, and a second p-type nitride semiconductor layer on the opposite side of the first p-type nitride semiconductor layer from the nitride semiconductor active layer.

Abstract: A fast injection optical switch is disclosed. The optical switch includes a thyristor having a plurality of layers including an outer doped layer and a switching layer. An area of the thyristor is configured to receive a light beam to be directed through at least one of the plurality of layers and exit the thyristor at a predetermined angle. At least two electrodes are coupled to the thyristor and configured to enable a voltage to be applied to facilitate carriers from the outer doped layer to be directed to the switching layer. Sufficient carriers can be directed to the switching layer to provide a change in refractive index of the switching layer to redirect at least a portion of the light beam to exit the thyristor at a deflection angle different from the predetermined angle.

Abstract: An image sensing apparatus includes a pixel array including a light-shielded area where light-shielded pixels are arranged, and an effective area where non-light-shielded pixels are arranged. Each of the light-shielded pixels includes a first photoelectric conversion unit, a first charge-voltage converter which converts charges generated in the first photoelectric conversion unit into a voltage, and a first amplification transistor functioning as a MOS transistor which receives, at the gate, the voltage converted by the first charge-voltage converter. Each of the non-light-shielded pixels includes a second photoelectric conversion unit, a second charge-voltage converter which converts charges generated in the second photoelectric conversion unit into a voltage, and a second amplification transistor functioning as a MOS transistor which receives, at the gate, the voltage converted by the second charge-voltage converter.

Abstract: Bipolar power semiconductor component comprising a p-type emitter and more highly doped zones in the p-type emitter, and production method. The invention relates to a bipolar power semiconductor component comprising a semiconductor body (1), in which a p-doped emitter (8), an n-doped base (7), a p-doped base (6) and an n-doped main emitter (5) are arranged successively in a vertical direction (v). The p-doped emitter (8) has a number of heavily p-doped zones (82) having a locally increased p-type doping.

Abstract: A light-emitting element including a light-emitting thyristor and a Schottky barrier diode is provided. A Schottky barrier diode is formed by contacting a metal terminal to a gate layer of a three-terminal light-emitting thyristor consisting of a PNPN-structure. A self-scanning light-emitting element array may be driven at 3.0V by using such a Schottky barrier diode as a coupling diode of a diode-coupled self-scanning light-emitting element array.

Abstract: The present invention provides an optically triggered switch and a method of forming the optically triggered switch. The optically triggered switch includes a silicon layer having at least one trench formed therein and at least one silicon diode formed in the silicon layer. The switch also includes a first thyristor formed in the silicon layer. The first thyristor is physically and electrically isolated from the silicon diode by the trench and the first thyristor is configured to turn on in response to electromagnetic radiation generated by the silicon diode.

Abstract: A SGPMOS transistor includes a base, a P-type diffusion layer, a gate electrode, and a LOCOS oxide film. The base includes at least one of a N-type semiconductor substrate, a P-type semiconductor substrate, and a N-type well. The P-type diffusion layer includes a P-type source and a P-type drain. At least the P-type drain includes a double diffusion structure including first and second P-type drain diffusion layers. The LOCOS oxide film is provided on the first P-type drain diffusion layer and covered by an end of the gate electrode. The first and the second P-type drain diffusion layers satisfy a relation of Y<Xj, in which Y represents a distance of the first P-type drain diffusion layer between the second P-type drain diffusion layer and the channel, and Xj represents a difference between depths of the second P-type drain diffusion layer and the first P-type drain diffusion layer.

Abstract: The present invention provides a method and apparatus for providing electro-static discharge (ESD) protection between a first and a second circuit node. One embodiment of the ESD protection circuit includes one or more steering diodes that generate electromagnetic radiation and couple the first circuit node to ground in response to a voltage applied to the first circuit node. The ESD protection circuit also includes a latch circuit that couples the first circuit node to ground in response to the electromagnetic radiation generated by the steering diode(s).

Abstract: On the back surface of a transparent plate having a light extracting part for outputting lights to the outside, an electrode for wiring, and an electrode for an electromagnetic shield, an optical device is flip-chip mounted right under the light extracting part, an a driver IC is flip-chip mounted at a desired position with metal bumps. When currents driving the optical device flow from the driver IC according to an electric logical signal from the outside, an optical signal is emitted from the optical device, and is output to the outside through the light extracting part. The light extracting part may be provided with a light coupling material or an optical axis converter.

Abstract: A main thyristor (1) has a recovery protection which is integrated into a drive thyristor (2) whose n-doped emitter (25) is electrically connected to a main thyristor control terminal (140). Moreover, the p-doped emitter (28) of the drive thyristor (2) is electrically connected to the p-doped emitter (18) of the main thyristor (1). Various optional measures for realizing a recovery protection are provided in this case. A method for producing a thyristor system having a main thyristor and a drive thyristor, the drive thyristor (2) having anode short circuits (211) involves introducing particles (230) into a target region (225) of the semiconductor body (200) of the drive thyristor (2), the distance between the target region (225) and a front side (201) of the semiconductor body (200) opposite to the rear side (202) being less than or equal to the distance between the p-doped emitter (28) and the front side (201).

Abstract: A pixel having a well-isolated charge storage region or floating diffusion region may be obtained by providing a separate P-well around the storage region or floating diffusion region. In one embodiment, a separate P-well entirely encases the storage region and is in contact with the storage region. This P-well provides an electrical barrier for preventing electrons that are generated elsewhere in the pixel from contaminating the storage region. In another embodiment, a first separate P-well encases and is in contact with the storage region and a second separate P-well encases and is in contact with the floating diffusion region.

Abstract: The present invention provides an optically triggered switch and a method of forming the optically triggered switch. The optically triggered switch includes a silicon layer having at least one trench formed therein and at least one silicon diode formed in the silicon layer. The switch also includes a first thyristor formed in the silicon layer. The first thyristor is physically and electrically isolated from the silicon diode by the trench and the first thyristor is configured to turn on in response to electromagnetic radiation generated by the silicon diode.

Abstract: An optoelectronic circuit includes a resonant cavity formed on a substrate and into which is injected an input digital optical signal that encodes bits of information (each bit representing an OFF logic level or an ON logic level). A heterojunction thyristor device, formed in the resonant cavity, produces an output digital electrical signal corresponding to the input digital optical signal. A sampling clock defines sampling periods that overlap the bits (e.g., ON/OFF pulse durations) in the input digital optical signal. The sampling clock can be in the form of electrical pulses supplied to the n-channel injector terminal(s) and/or p-channel injector terminals of the heterojunction thyristor device. Alternatively, the sampling clock can be in the form of optical pulses that are part of the Optical IN signal that is resonantly absorbed by the device. The heterojunction thyristor device operates in an OFF state and an ON state.

Abstract: CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.

Abstract: A photosensor includes a plurality of photosensitive regions including a first photosensitive region connected to a first voltage reference, and at least one additional photosensitive region. A signal collector is connected to the first photosensitive region. At least one switching device is for switching the at least one additional photosensitive region between the first voltage reference and a second voltage reference that is less than the first voltage reference, and for reversibly connecting the at least one additional photosensitive region to the signal collector so that the photosensor is variably responsive to different light levels.

Abstract: An integrated circuit having memory, including thyristor-based memory cells, is described, where each of the thyristor-based memory cells includes a thyristor-based storage element and an access transistor. Where the thyristor-based storage element includes an anode region and a cathode region, a pair of the thyristor-based memory cells are commonly coupled via a bitline associated with the access transistor or via a reference voltage line coupled to the anode region. Bitline or anode regions are separated from one another by an isolation region. In another configuration, a bitline region has a locally implant-damaged region to inhibit charge transfer between the pair. In yet another configuration, a storage node contact or contacts respectively can extend over or are coupled to a storage node line extending over an isolation region. In this latter configuration, a source/drain region and the cathode region are separated from one another by an isolation region.

Abstract: A semiconductor device may include at least one memory cell comprising a negative differential resistance (NDR) device and a control gate coupled thereto. The NDR device may include a superlattice including a plurality of stacked groups of layers, with each group of layers of the superlattice including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: Disclosed is a photoelectric surface including: a first group III nitride semiconductor layer that produces photoelectrons according to incidence of ultraviolet rays; and a second group III nitride semiconductor layer provided adjacent to the first group III nitride semiconductor layer and made of a thin-film crystal having c-axis orientation in a thickness direction, the second group III nitride semiconductor layer having an Al composition higher than that of the first group III nitride semiconductor layer.

Abstract: An ESD protection structure has: a first P-type semiconductor region connected to a pad; a first N-type semiconductor region coupled with the first P-type semiconductor region; a second P-type semiconductor region coupled with the first N-type semiconductor region and connected to a ground terminal; a second N-type semiconductor region coupled with the second P-type semiconductor region and connected to a ground terminal; and a trigger circuit configured to draw a trigger current from the first N-type semiconductor region when a surge is applied to the pad. The trigger circuit is connected to the first N-type semiconductor region through a resistive element.

Abstract: Planar AWG circuits and systems are disclosed that use air trench bends to increase planar circuit compactness.

Abstract: In an operational amplifier including first and second power supply terminals, first and second input terminals, and a first and second output terminals, a first differential amplifier circuit includes first and second MOS transistors with a common source connected to a first tail current source, first and second load resistors and a first non-doped MOS transistor connected between the first and second resistors and the second power supply terminal. A second differential amplifier circuit includes third and fourth MOS transistors with a common source connected to a second tail current source, third and fourth load resistors and a second non-doped MOS transistor connected between the third and fourth load resistors and the second power supply terminal.

Abstract: Microelectronic imagers with curved image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device includes an imager die having a substrate, a curved microelectronic image sensor having a face with a convex and/or concave portion at one side of the substrate, and integrated circuitry in the substrate operatively coupled to the image sensor. The imager die can further include external contacts electrically coupled to the integrated circuitry and a cover over the curved image sensor.

Abstract: A thyristor and family of high speed transistors and optoelectronic devices are obtained on a monolithic substrate (149) with an epitaxial layer structure comprised of two modulation doped transistor structures inverted with respect to each other. The transistor structures are obtained by adding planar doping to the Pseudomorphic High Electron Mobility Transistor (PHEMT) structure. For one transistor, two sheets of planar doping of the same polarity separated by a lightly doped layer are added which are opposite to the modulation doping of the PHEMT. The combination is separated from the PHEMT modulation doping by undoped material. The charge sheets are thin and highly doped. The top charge sheet (168) achieves low gate contact resistance and the bottom charge sheet (153) defines the capacitance of the field-effect transistor (FET) with respect to the modulation doping layer of the PHEMT. For the other transistor, only one additional sheet is added.

Abstract: In order to provide a photothyristor having high breakdown voltage and less-varying light sensitivity by improving the sensitivity and the breakdown voltage of the device while maintaining the device small, the device includes a silicon substrate, a transistor portion including an anode region, a gate region and a cathode region and placed on a first main surface of the silicon substrate, a light-receiving portion for receiving light from the outside, and an electrode for establishing an ohmic contact between the anode region and the cathode region. The light receiving portion includes an oxygen-doped polysilicon film overlaid on the silicon substrate through a transparent insulating film and is disposed to surround the transistor portion. The electrode is placed above the transistor portion and has a double-structure consisting of a center portion and an outer portion surrounding the center portion, and the center portion and the outer portion are electrically connected.

Abstract: A thyristor and a method for manufacturing the thyristor that includes a gate region extending from the first major surface into a semiconductor substrate and an anode region extending from the second major surface into the semiconductor substrate. A cathode region extends into a portion of the gate region. Optionally, enhanced doped regions extend into the gate and anode regions. A mesa structure having a height HG is formed from the first major surface and a mesa structure having a height HA is formed from the second major surface. The gate region extends under the first major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HG. The anode region extends under the second major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HA.

Abstract: A 3-dimensional PCM structure and method for using the same for carrying out 3-dimensional integrated circuit wiring electrical testing and failure analysis in an integrated circuit manufacturing process, the method including forming a first metallization layer; carrying out a first wafer acceptance testing (WAT) process to test the electrical continuity of the first metallization layer; forming first metal vias on the first metallization layer conductive portions and a second metallization layer comprising metal islands on the first metal vias wherein the metal islands electrically communicate with the first metallization layer to form a process control monitor (PCM) structure; and, carrying out a second WAT process to test the electrical continuity of the first metallization layer.

Abstract: A vertical SCR switch to be controlled by a high-frequency signal having at least four main alternated layers. The switch includes a gate terminal and a gate reference terminal connected via integrated capacitors to corresponding areas. In the case of a thyristor, having on its front surface side a main P-type semiconductor area formed in an N-type gate semiconductor area, a first portion of the main area being connected to one of the main areas, a second portion of the main area is connected to one of the control terminals via a first integrated capacitor, and a portion of the gate area being connected to the other of the control terminals via a second integrated capacitor.