With Electrical Trigger Signal Amplification Means (e.g., Amplified Gate, "pilot Thyristor", Etc.) Patents (Class 257/115)
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Patent number: 7214971Abstract: A semiconductor light-receiving device has a substrate including upper, middle and lower regions in its front side. A p-type layer on the lower region has a top surface including a portion on a level with the middle region. An electrode covers at least part of the boundary between the portion of the p-type layer and the middle region. An n-type layer on the p-type layer has a top surface including a portion on a level with the upper region. Another electrode covers at least part of the boundary between the portion of the n-type layer and the upper region.Type: GrantFiled: June 10, 2004Date of Patent: May 8, 2007Assignee: Hamamatsu Photonics K.K.Inventors: Minoru Niigaki, Kazutoshi Nakajima
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Patent number: 7193322Abstract: A strained-silicon (Si) channel CMOS device shallow trench isolation (STI) oxide region, and method for forming same have been provided. The method forms a Si substrate with a relaxed-SiGe layer overlying the Si substrate, or a SiGe on insulator (SGOI) substrate with a buried oxide (BOX) layer. The method forms a strained-Si layer overlying the relaxed-SiGe layer; a silicon oxide layer overlying the strained-Si layer, a silicon nitride layer overlying the silicon oxide layer, and etches the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface. The method forms a sacrificial oxide liner on the STI trench surface. In response to forming the sacrificial oxide liner, the method rounds and reduces stress at the STI trench corners, removes the sacrificial oxide liner, and fills the STI trench with silicon oxide.Type: GrantFiled: November 9, 2004Date of Patent: March 20, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: Jong-Jan Lee, Sheng Teng Hsu
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Patent number: 7193250Abstract: A light-emitting element including a light-emitting thyristor and a schottky barrier diode is provided. A schottky barrier diode is formed by contacting a metal terminal to a gate layer of a three-terminal light-emitting thyristor consisting of a PNPN-structure. A self-scanning light-emitting element array may be driven at 3.0 V by using such a schottky barrier diode as a coupling diode of a diode-coupled self-scanning light-emitting element array.Type: GrantFiled: February 21, 2003Date of Patent: March 20, 2007Assignee: Nippon Sheet Glass Company, LimitedInventor: Seiji Ohno
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Patent number: 7115925Abstract: An active pixel includes a a photosensitive element formed in a semiconductor substrate. A transfer transistor is formed between the photosensitive element and a floating diffusion and selectively operative to transfer a signal from the photosensitive element to the floating diffusion. The floating diffusion is formed from an n-type implant with a dosage in the range of 5e13 to 5e14 ions/cm2. Finally, an amplification transistor is controlled by the floating diffusion.Type: GrantFiled: January 14, 2005Date of Patent: October 3, 2006Assignee: OmniVision Technologies, Inc.Inventor: Howard E. Rhodes
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Patent number: 7102185Abstract: An interline transfer type image sensing device that can be operated at high speed and with low image smear is described. The device incorporates a refractory metal layer which is used for both a light shield over the vertical charge transfer region and as a wiring layer for low resistance strapping of poly crystalline silicon (polysilicon) gate electrodes for the vertical charge transfer region. Plugs provided by a separate metallization layer connect the refractory light shield to the polysilicon gate electrode. These plugs allow high temperature processing after refractory light shield patterning for improved sensor performance without degradation of the polysilicon gate electrode or the refractory lightshield layer.Type: GrantFiled: June 21, 2004Date of Patent: September 5, 2006Assignee: Eastman Kodak CompanyInventors: David N. Nichols, David L. Losee, Christopher Parks
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Patent number: 7057214Abstract: Semiconductor switches, such as thyristors, may be light activated by introducing the light into the switch via a groove having a sloped surface to receive the triggering light. The use of a sloped surface increases the surface path length between points of different electrical potential in the groove and, therefore, reduces the likelihood of electrical breakdown on the groove wall. In one particular embodiment, a light-activated thyristor includes a semiconductor anode layer, an n-base layer, a p-base layer and a semiconductor cathode layer disposed parallel to a thyristor plane. A thyristor axis lies perpendicular to the thyristor plane. A groove having a light refracting side wall extends into the thyristor from the anode layer. A portion of the light refracting side wall is disposed non-parallel to the thyristor plane and to the thyristor axis, and extends in the n-drift layer.Type: GrantFiled: July 1, 2003Date of Patent: June 6, 2006Assignee: Optiswitch Technology CorporationInventors: David M. Giorgi, Tajchai Navapanich
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Patent number: 7002829Abstract: A method and apparatus for opening a fuse formed on a semiconductor substrate. The apparatus comprises a thyristor formed from CMOS device regions and having a one or two control terminals for permitting current to flow through the thyristor into the fuse, for opening the fuse.Type: GrantFiled: September 30, 2003Date of Patent: February 21, 2006Assignee: Agere Systems Inc.Inventors: Ranbir Singh, Richard J. McPartland, Ross A. Kohler
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Patent number: 6919583Abstract: An edge-emitting thyristor having an improved external luminous efficiency and a self-scanning light-emitting device array comprising the edge-emitting thyristor are disclosed. To improve the external luminous efficiency of an edge-emitting light-emitting thyristor, a structure where the current injected from an electrode concentrates on and near the edge of the light-emitting thyristor is adopted.Type: GrantFiled: February 11, 2004Date of Patent: July 19, 2005Assignee: Nippon Sheet Glass Company, LimitedInventors: Takashi Tagami, Yukihisa Kusuda, Seiji Ohno, Nobuyuki Komaba
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Optoelectronic circuit employing a heterojunction thyristor device that performs high speed sampling
Patent number: 6853014Abstract: An optoelectronic circuit employing a heterojunction thyristor device that is configured as an optically-controlled (or electrically-controlled) sampling/switching device. First and second channel regions are disposed between the anode terminal and the cathode terminal of the device, and an electrical input terminal and an electrical output terminal are coupled to opposite ends of the first channel region. At least one control signal is supplied to the device. When the control signal corresponds to a predetermined ON condition, sufficient charge is stored in the second channel region to cause the heterojunction thyristor device to operate in an ON state whereby current flows between the anode terminal and the cathode terminal and the electrical input terminal is electrically coupled to the electrical output terminal.Type: GrantFiled: December 19, 2002Date of Patent: February 8, 2005Assignees: The University of Connecticut, Opel, Inc.Inventors: Geoff W. Taylor, Jianhong Cai -
Patent number: 6818927Abstract: A monolithic bidirectional switch formed in a semiconductor substrate of type N, including a first main vertical thyristor, the rear surface layer of which is of type P, a second main vertical thyristor, the rear surface layer of which is of type N, an auxiliary vertical thyristor, the rear surface layer of which is of type P and is common with that of the first main thyristor, a peripheral region of type P especially connecting the rear surface layer of the auxiliary thyristor to the layer of this thyristor located on the other side of the substrate, a first metallization on the rear surface side, a second metallization on the front surface side connecting the front surface layers of the first and second thyristors. An additional region has a function of isolating the rear surface of the auxiliary thyristor and the first metallization.Type: GrantFiled: July 25, 2002Date of Patent: November 16, 2004Assignee: STMicroelectronics S.A.Inventor: Jean-Michel Simonnet
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Patent number: 6809355Abstract: A solid-state imaging device having a gate structure including an oxide film and a nitride film includes upper layer films (for example, a planarization film, an insulating film, and a protective film) allowing ultraviolet rays having a wavelength of 400 nm or less to pass therethrough; and a metal made shield film or an organic film capable of absorbing the ultraviolet rays formed in such a manner as to cover a region of the gate structure (for example, an output gate and a reset gate), excluding a light receiving portion and a transfer portion, of the solid-state imaging device. With this configuration, it is possible to prevent the shift of a threshold voltage Vth, and hence to enhance the reliability of the transfer or reset of electric charges.Type: GrantFiled: March 30, 2001Date of Patent: October 26, 2004Assignee: Sony CorporationInventor: Kazushi Wada
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Publication number: 20040079961Abstract: A photonic digital-to-analog converter employing a plurality of heterojunction thyristor devices that are configured to convert a digital word encoded by a parallel digital optical signal (e.g., a plurality of synchronous optical bits) to an output analog electrical signal whose magnitude corresponds to the digital word. Each heterojunction thyristor device is configured to convert an optical bit in the digital word to a corresponding digital electrical signal. The voltage levels (e.g., magnitudes) of the ON state of the digital electrical signals produced by the heterojunction thyristor devices may be supplied by voltage divider networks coupled between the cathode terminal of the devices and ground potential or voltage reference sources coupled to the input terminals of the heterojunction thyristor devices. In this manner, electrical signals whose magnitude corresponds to contribution of each optical bit in the digital word are produced.Type: ApplicationFiled: December 19, 2002Publication date: April 29, 2004Applicants: The University of Connecticut, OPEL, Inc.Inventors: Geoff W. Taylor, Jianhong Cai
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Patent number: 6724020Abstract: A semiconductor device comprising a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.Type: GrantFiled: April 23, 2003Date of Patent: April 20, 2004Assignee: Renesas Technology CorporationInventors: Hiroyuki Takazawa, Tohru Oka, Isao Ohbu, Yoshinori Imamura
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Patent number: 6717182Abstract: A self-scanning light-emitting element array using an end face light-emitting thyristor having improved external emission efficiency is provided. To improve the external emission efficiency of the end face light-emitting thyristor, the present invention adopts such structure that the current injected from an anode is concentrated to near the end face of the light-emitting thyristor. A self-scanning light-emitting element array is implemented by using such end face light-emitting thyristor.Type: GrantFiled: February 8, 2001Date of Patent: April 6, 2004Assignee: Nippon Sheet Glass Co., Ltd.Inventors: Takashi Tagami, Yukihisa Kusuda, Seiji Ohno, Nobuyuki Komaba
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Publication number: 20030205719Abstract: A semiconductor device comprising a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.Type: ApplicationFiled: April 23, 2003Publication date: November 6, 2003Applicant: Hitachi, Ltd.Inventors: Hiroyuki Takazawa, Tohru Oka, Isao Ohbu, Yoshinori Imamura
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Patent number: 6576937Abstract: A semiconductor device including a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.Type: GrantFiled: May 24, 2001Date of Patent: June 10, 2003Assignee: Hitachi, Ltd.Inventors: Hiroyuki Takazawa, Tohru Oka, Isao Ohbu, Yoshinori Imamura
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Patent number: 6521918Abstract: To make it possible to control turn-off operation even after switch over to transistor operation after commutation of the main current from cathode electrode to gate electrode in turn-off operation, a semiconductor device according to the invention comprises a first electrode, a first region of first conduction type provided on the first electrode, a second region of second conduction type provided on the first region, a third region and a fourth region of first conduction type respectively provided on the second region with a predetermined distance from each other to allow formation of a channel region on the second region, a fifth region of second conduction type provided on the third region, a second electrode provided on the fifth region, a gate electrode established in contact with the fourth region and a control electrode provided on a separate region between the third and fourth regions on the second region to control the channel region through an insulation layer.Type: GrantFiled: May 9, 2000Date of Patent: February 18, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kenji Oota, Kazuhiro Morishita, Katsumi Satoh
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Patent number: 6501099Abstract: A gate turn-off thyristor includes a substrate formed of n-type silicon carbide; a growth buffer formed of n-type silicon carbide and positioned to overlie said substrate; a field buffer region formed of p-type silicon carbide and positioned to overlie said growth buffer; a drift region formed of p-type silicon carbide and positioned to overlie said field buffer region; a gated base region formed of n-type silicon carbide and positioned to overlie said drift region; a modified anode region formed of first, second and third layers of silicon carbide and positioned to overlie said gated base region, said first layer comprising p-type silicon carbide and disposed adjacent said gated base region, said second layer comprising n-type silicon carbide and disposed adjacent said first layer, said third layer comprising p-type silicon carbide and disposed adjacent said second layer; an anode contact disposed on said third layer of said modified anode region; a cathode contact disposed on said substrate; and a gate contType: GrantFiled: March 5, 2001Date of Patent: December 31, 2002Assignee: The United States of America as represented by the Secretary of the ArmyInventor: Pankaj B. Shah
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Patent number: 6472691Abstract: A DFB semiconductor laser device including: a semiconductor substrate; and an active layer and a diffraction grating overlying the semiconductor substrate, the diffraction grating having a composition of GaInNAs(Sb) and absorbing light having a laser emission wavelength of the active layer. The DFB semiconductor laser device having a higher SMSR can be provided which stably operates in a wider range of injection current by proving the diffraction grating formed by the GaInNAs(Sb) having the composition for efficiently absorbing light which has the laser emission wavelength of the active layer.Type: GrantFiled: June 6, 2001Date of Patent: October 29, 2002Assignee: The Furukawa Electric Co., Ltd.Inventors: Toshikazu Mukaihara, Hitoshi Shimizu, Masaki Funabashi, Akihiko Kasukawa
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Publication number: 20020134992Abstract: A gate turn-off thyristor includes a substrate formed of n-type silicon carbide; a growth buffer formed of n-type silicon carbide and positioned to overlie said substrate; a field buffer region formed of p-type silicon carbide and positioned to overlie said growth buffer; a drift region formed of p-type silicon carbide and positioned to overlie said field buffer region; a gated base region formed of n-type silicon carbide and positioned to overlie said drift region; a modified anode region formed of first, second and third layers of silicon carbide and positioned to overlie said gated base region, said first layer comprising p-type silicon carbide and disposed adjacent said gated base region, said second layer comprising n-type silicon carbide and disposed adjacent said first layer, said third layer comprising p-type silicon carbide and disposed adjacent said second layer; an anode contact disposed on said third layer of said modified anode region; a cathode contact disposed on said substrate; and a gate contType: ApplicationFiled: March 5, 2001Publication date: September 26, 2002Inventor: Pankaj B. Shah
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Patent number: 6441404Abstract: A multichip module has a light-emitting device having an anode electrode or a cathode electrode thereof connected to a supplied voltage or a reference voltage, a control circuit, having a substrate of an opposite conductivity type to the substrate of the light-emitting device, for controlling the electric current that is passed through the light-emitting device, a lead frame including an island 4 on which both the light-emitting device and the control circuit are mounted, and a package for sealing the light-emitting device and the control circuit. Despite being compact, this multichip module allows a satisfactorily large amount of light to be emitted from the light-emitting device.Type: GrantFiled: January 14, 2000Date of Patent: August 27, 2002Assignee: Rohm Co., Ltd.Inventor: Kenji Yamamoto
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Publication number: 20020005525Abstract: A semiconductor device comprising a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.Type: ApplicationFiled: May 24, 2001Publication date: January 17, 2002Applicant: Hitachi, Ltd.Inventors: Hiroyuki Takazawa, Tohru Oka, Isao Ohbu, Yoshinori Imamura
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Patent number: 6066864Abstract: Given too great a dU/dt load of a thyristor, this can trigger in uncontrolled fashion in the region of the cathode surface. Since the plasma only propagates poorly there and the current density consequently reaches critical values very quickly, there is the risk of destruction of the thyristor due to local overheating. The proposed thyristor has a centrally placed BOD structure and a plurality of auxiliary thyristors (1.-5. AG) annularly surrounding the BOD structure. The resistance of the cathode-side base (8) is locally increased under the emitter region (11) allocated to the innermost auxiliary thyristor (1. AG). Since the width (L) and the sheet resistivity of this annular zone (15) critically influences the dU/dt loadability of the first auxiliary thyristor (1.Type: GrantFiled: November 20, 1998Date of Patent: May 23, 2000Assignee: Siemens AktiengesellschaftInventors: Martin Ruff, Hans-Joachim Schulze, Frank Pfirsch
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Patent number: 6034381Abstract: The present invention relates to a triac network wherein each triac includes an N-type semiconductor substrate, containing a first thyristor comprised of NPNP regions and a second thyristor comprised of PNPN regions, and surrounded with a P-type deep diffusion. A P-type well contains an N-type region, on the front surface side. A first metallization corresponds to a first main electrode, a second metallization corresponds to a second main electrode, a third metallization covers the N-type region and is connected to a gate terminal, and a fourth metallization connects the P-type well to the upper surface of the deep diffusion.Type: GrantFiled: June 9, 1997Date of Patent: March 7, 2000Assignee: SGS-Thomson Microelectronics S.A.Inventor: Robert Pezzani
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Patent number: 5801429Abstract: It is an object of the present invention to fix a semiconductor substrate and a thermal compensating plate in the alloy-free structure. An insulation resin (23) for side wall protection fixed on the outer periphery of a semiconductor substrate (1) and a projection (6a) inside an insulation tube are bonded with an adhesive agent (24) to restrict movements of the semiconductor substrate (1) in the radial direction. A thermal compensating plate (3) and a main electrode (5) are normally positioned with each other by a screw pin (32). A fixing ring (30) having resin or metal such as aluminum or the like which fits to the outer peripheral side of the main electrode (4) and the outer peripheral side of the thermal compensating plate (2) and the edge part of the upper main surface thereof restricts movement of the thermal compensating plate (2) in the radial direction.Type: GrantFiled: November 12, 1996Date of Patent: September 1, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yuzuru Konishi, Kyotaro Hirasawa, Kazunori Taguchi
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Patent number: 5767538Abstract: An integrated circuit photodetector includes a transimpedance amplifier including a differential amplifier stage with PNP emitter-coupled transistors and a PNP input transistor which are biased only by base currents of the emitter-coupled transistors, to achieve low input bias current. Low noise operation is achieved by bypass capacitors coupled between the bases and emitters of the input transistors, respectively. A constant current source supplies a current which develops a small pedestal voltage across a resistor to bias the non-inverting input of the transimpedance amplifier so as to avoid nonlinear amplification of low level light signals. A positively biased N-type guard tub surrounds the photodetector, which is formed in a junction-isolated N region on a P substrate, to collect electrons generated in the substrate by deep-penetrating IR light to prevent them from causing amplification errors.Type: GrantFiled: October 9, 1996Date of Patent: June 16, 1998Assignee: Burr-Brown CorporationInventors: Edward Mullins, Rodney T. Burt, Walter B. Meinel, R. Mark Stitt, II
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Patent number: 5652439Abstract: The invention relates generally to optoelectronic pnpn devices and more particularly to a layer structure suitable for fast electrical complete turn-off of such devices and to a method for efficient and fast operation of such devices and differential pairs of such devices. The devices have four layers and three junctions, and the invention provides for complete depletion of both center layers. The differential pair of pnpn devices also provides a very sensitive optical receiver which combines a very high cycle frequency with a very high optical sensitivity.Type: GrantFiled: September 8, 1995Date of Patent: July 29, 1997Assignee: IMECInventors: Maarten Kuijk, Paul Heremans, Roger Vounckx, Gustaaf Borghs
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Patent number: 5637886Abstract: When an abrupt voltage noise is applied across an anode electrode (A) and a cathode electrode (K), displacement currents (I.sub.10 to I.sub.30) which are responsive to junction capacitances (C.sub.10 to C.sub.30) of respective unit thyristors (ST.sub.1, ST.sub.2, MT) are generated. The displacement currents (I.sub.10 to I.sub.30) flow into a compensation electrode (C) through paths in a P base layer (2) having resistances (R.sub.10 to R.sub.30), and further flow to an external power source through the cathode electrode (K) which is short-circuited with the compensation electrode (C). The paths of the three displacement currents (I.sub.10 to I.sub.30) are separated from each other by resistances (R.sub.12, R.sub.23). Therefore, a forward bias voltage of a junction (D.sub.10) caused by the displacement current (I.sub.10) is attenuated by the displacement current (I.sub.20), while a forward bias voltage of a junction (D.sub.20) caused by the displacement current (I.sub.Type: GrantFiled: February 14, 1995Date of Patent: June 10, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsumi Satoh, Kenichi Honda, Kazuhiko Niwayama
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Patent number: 5614737Abstract: This thyristor comprises a main current-carrying portion in the form of a semiconductor body having four layers, with contiguous layers being of different P and N conductivity types and with three back-to-back PN junctions between contiguous layers. One end layer constitutes an anode layer, an opposite end layer constitutes a cathode layer, and an intermediate layer contiguous with the cathode layer constitutes a gate layer. The cathode layer is divided into many elongated fingers, thereby dividing the PN junction between the cathode layer and the gate layer into many discrete PN subjunctions between the fingers and the gate layer. These subjunctions are effectively in parallel with each other so as to share the main current through the thyristor when the thyristor is "on". The gate layer has predetermined surface regions adjacent the cathode layer that are uncovered by the cathode-layer fingers and that respectively surround the PN subjunctions between the fingers and the gate layer.Type: GrantFiled: July 19, 1995Date of Patent: March 25, 1997Assignee: Silicon Power CorporationInventor: Dante E. Piccone
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Patent number: 5428228Abstract: A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.Type: GrantFiled: December 10, 1993Date of Patent: June 27, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Kiminori Watanabe, Akio Nakagawa, Yoshihiro Yamaguchi, Norio Yasuhara, Tomoko Matsudai, Shigeru Hasegawa, Kazuya Nakayama
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Patent number: RE36770Abstract: This thyristor comprises a main current-carrying portion in the form of a semiconductor body having four layers, with contiguous layers being of different P and N conductivity types and with three back-to-back PN junctions between contiguous layers. One end layer constitutes an anode layer, an opposite end layer constitutes a cathode layer, and an intermediate layer contiguous with the cathode layer constitutes a gate layer. The cathode layer is divided into many elongated fingers, thereby dividing the PN junction between the cathode layer and the gate layer into many discrete PN subjunctions between the fingers and the gate layer. These subjunctions are effectively in parallel with each other so as to share the main current through the thyristor when the thyristor is "on". The gate layer has predetermined surface regions adjacent the cathode layer that are uncovered by the cathode-layer fingers and that respectively surround the PN subjunctions between the fingers and the gate layer.Type: GrantFiled: March 22, 1999Date of Patent: July 11, 2000Assignee: Silicon Power CorporationInventor: Dante E. Piccone