With Light Conductor Means (e.g., Light Fiber Or Light Pipe) Integral With Device Or Device Enclosure Or Package Patents (Class 257/116)
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Patent number: 11892691Abstract: A hermetic optical fiber alignment assembly includes a ferrule portion having a plurality of grooves receiving the end sections of optical fibers, wherein the grooves define the location and orientation of the end sections with respect to the ferrule portion. The assembly includes an integrated optical element for coupling the input/output of an optical fiber to the opto-electronic devices in the opto-electronic module. The optical element can be in the form of a structured reflective surface. The end of the optical fiber is at a defined distance to and aligned with the structured reflective surface. The structured reflective surfaces and the fiber alignment grooves can be formed by stamping.Type: GrantFiled: July 20, 2020Date of Patent: February 6, 2024Assignee: Senko Advanced Components, Inc.Inventors: Shuhe Li, Robert Ryan Vallance, Michael K. Barnoski, King-Fu Hii
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Patent number: 11803020Abstract: An optical bench subassembly including an integrated photonic device. Optical alignment of the photonic device with the optical bench can be performed outside of an optoelectronic package assembly before attaching thereto. The photonic device is attached to a base of the optical bench, with its optical input/output in optical alignment with the optical output/input of the optical bench. The optical bench supports an array of optical fibers in precise relationship to a structured reflective surface. The photonic device is mounted on a submount to be attached to the optical bench. The photonic device may be actively or passively aligned with the optical bench. After achieving optical alignment, the submount of the photonic device is fixedly attached to the base of the optical bench. The optical bench subassembly may be structured to be hermetically sealed as a hermetic feedthrough, to be hermetically attached to a hermetic optoelectronic package.Type: GrantFiled: August 20, 2020Date of Patent: October 31, 2023Assignee: Senko Advanced Components, IncInventors: Robert Ryan Vallance, Shuhe Li
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Patent number: 10348093Abstract: Unique systems, methods, techniques and apparatuses of a power collection system are disclosed herein. One exemplary embodiment is an MVDC collection system coupled to a utility grid including a collection bus, a plurality of branches coupled to the collection bus, and a branch controller. Each of the plurality of branches include a semiconductor switch coupled to the collection bus, and a DC/DC converter coupled to the semiconductor switch and an LVDC power source. The branch controller configured to determine a fault condition is occurring within the MVDC collection system, determine the location of the fault condition, and isolate the fault condition using at least one of the semiconductor switches and the DC/DC converters.Type: GrantFiled: December 14, 2016Date of Patent: July 9, 2019Assignee: ABB Schweiz AGInventors: Harish Suryanarayana, Hongrae Kim, Sara Ahmed, Peter Steimer, Philippe Maibach, Hans Krattiger, Silverio Alvarez, Paolo Casini, Jiuping Pan
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Patent number: 10094994Abstract: An electrical/optical connector system can include a first circuit board with a floating optical connector and a first electrical contact and a second circuit board with a second optical connector to blind mate with the floating optical connector and a second electrical contact to blind mate with the first electrical contact.Type: GrantFiled: April 25, 2012Date of Patent: October 9, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Kevin B. Leigh, George D. Megason, Paul K. Rosenberg
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Patent number: 10054749Abstract: An optical chip-scale package (CSP) is provided for use in a high channel density, high data rate communications system that has optical I/O ports and that is capable of being housed in a standard rackmount-sized box. The optical I/O ports comprise a bulkhead of multi-optical fiber (MF) adapters installed in a front panel of a switch box that houses the communications system. The adapters have first and second receptacles that are adapted to mate with first and second MF connectors, respectively. The communications system comprises a single-harness optical subassembly that uses a plurality of the optical CSPs that interface with a switch IC chip of the communications system to perform electrical-to-optical and optical-to-electrical conversion.Type: GrantFiled: April 28, 2017Date of Patent: August 21, 2018Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Tak Kui Wang, Chung-Yi Su, Nick Jordache
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Patent number: 9087873Abstract: A recessed portion is formed around an outer edge of a device wafer at a peripheral edge portion of a first face of the device wafer. A recessed portion is formed around an outer edge of a support substrate, at a bonding face of the support substrate. The first face of the device wafer and the bonding face of the support substrate are bonded together by an adhesive. The device wafer is ground from a second face side, on the opposite side to the first face 11, as far as a depth position to reach a bottom face of the recessed portion.Type: GrantFiled: June 17, 2014Date of Patent: July 21, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventor: Tamotsu Owada
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Patent number: 8981413Abstract: An optical communication module includes an optical semiconductor element. The element includes an optical functional region having a light receiving function or a light emitting function, a first transmission layer transmissive to light emitted from the optical functional region or light received by the optical functional region, and a wiring layer stacked on the first transmission layer and constituting a conduction path to the optical functional region. The communication module also includes a second transmission layer transmissive to the light and disposed to cover the optical semiconductor element, and a first resin member stacked on the second transmission layer. The communication module is formed with a fixing hole for fixing an optical fiber. The fixing hole includes a bottom face provided by the second transmission layer, and an opening formed in an outer surface of the first resin member.Type: GrantFiled: February 24, 2014Date of Patent: March 17, 2015Assignee: Rohm Co., Ltd.Inventor: Akira Obika
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Photo detector consisting of tunneling field-effect transistors and the manufacturing method thereof
Patent number: 8969911Abstract: The present invention belongs to the technical field of optical interconnection and relates to a photo detector, in particular to a photo detector consisting of tunneling field-effect transistors.Type: GrantFiled: April 13, 2012Date of Patent: March 3, 2015Assignee: Fudan UniveristyInventors: Pengfei Wang, Xi Lin, Wei Wang, Xiaoyong Liu, Wei Zhang -
Patent number: 8729591Abstract: Non-planar via designs for sub-mounts on which to mount a LED or other optoelectronic device include a continuous layer of metal to conduct the current from the front-side (e.g., LED side) to the backside (e.g., SMD side) through the via and to provide a sufficiently stable and reliable under bump metallization for SMD soldering. Each UBM can be structured so that it does not fully cover the sidewall surfaces of the via that forms the front-to-backside interconnect. In some implementations, each via structure for the feedthrough metallization extends to a respective side-edge of the sub-mount.Type: GrantFiled: April 20, 2009Date of Patent: May 20, 2014Assignee: TSMC Solid State Lighting Ltd.Inventors: Jochen Kuhmann, Lior Shiv
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Patent number: 8680572Abstract: Some embodiments provide a microdisplay integrated circuit (IC), a substantially transparent protective cover coupled to the microdisplay IC, and a base coupled to the microdisplay IC. Thermal expansion characteristics of the base may be substantially similar to thermal expansion characteristics of the protective cover. According to some embodiments, at least one set of imaging elements is fabricated on an upper surface of a semiconductor substrate, and a base is affixed to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base.Type: GrantFiled: October 13, 2011Date of Patent: March 25, 2014Assignee: Intel CorporationInventors: Michael O'Connor, Thomas W. Springett, Paul C. Ward-Dolkas
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Patent number: 8461620Abstract: An optically triggered semiconductor switch includes an anode metallization layer; a cathode metallization layer; a semiconductor between the anode metallization layer and the cathode metallization layer and a photon source. The semiconductor includes at least four layers of alternating doping in the form P-N-P-N, in which an outer layer adjacent to the anode metallization layer forms an anode and an outer layer adjacent the cathode metallization layer forms a cathode and in which the anode metallization layer has a window pattern of optically transparent material exposing the anode layer to light. The photon source emits light having a wavelength, with the light from the photon source being configured to match the window pattern of the anode metallization layer.Type: GrantFiled: May 19, 2011Date of Patent: June 11, 2013Assignee: Applied Pulsed Power, Inc.Inventors: Steven C. Glidden, Howard D. Sanders
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Patent number: 8410508Abstract: A light emitting diode (LED) package includes a substrate and a light emitting diode (LED) die on the substrate configured to emit electromagnetic radiation in a first spectral region. The (LED) package also includes a dielectric layer on the (LED) die and a wavelength conversion member on the dielectric layer configured to convert the electromagnetic radiation in the first spectral region to electromagnetic radiation in a second spectral region. The (LED) package also includes an interconnect comprising a conductive trace on the wavelength conversion member and on the dielectric layer in electrical contact with a die contact on the (LED) die and with a conductor on the substrate, and a transparent dome configured as a lens encapsulating the (LED) die.Type: GrantFiled: September 12, 2011Date of Patent: April 2, 2013Assignee: SemiLEDS Optoelectronics Co., Ltd.Inventors: Jui- Kang Yen, Trung Tri Doan
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Patent number: 8145020Abstract: A semiconductor device includes a direct light-triggered thyristor triggered by an optical gate signal, a first optical fiber connected to the direct light-triggered thyristor and through which the optical gate signal is transmitted, a second optical fiber used to extend the first optical fiber, and a inter-optical-fiber relaying unit configured to connect the first optical fiber to the second optical fiber and to input the optical gate signal output from the second optical fiber to the first optical fiber.Type: GrantFiled: October 22, 2009Date of Patent: March 27, 2012Assignee: Toshiba Mitsubishi—Electric Industrial Systems CorporationInventor: Takafumi Fujimoto
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Patent number: 8129739Abstract: In a semiconductor light emitting device having a matrix of a plurality of bumps composed of one n-bump formed on an n-electrode layer and of a large number of p-bumps formed on p-electrode layers, the occurrence of a faulty junction after mounting can be suppressed by placement of the n-bump at center of the bump array, because the position at the center is most resistant to occurrence of stress after the mounting. Employment of such a configuration of bump array increases reliability of mounting thereof while improving uniformity of light emission intensity in the semiconductor light emitting device having an increased size.Type: GrantFiled: July 12, 2006Date of Patent: March 6, 2012Assignee: Panasonic CorporationInventors: Kazushi Higashi, Shinji Ishitani
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Patent number: 8097890Abstract: An image sensor having a plurality of micro-lenses disposed on a semiconductor substrate. A first micro-lens has a different focal length, height, shape, curvature, thickness, etc., than a second micro-lens. The image sensor may be back side illuminated or front side illuminated.Type: GrantFiled: February 11, 2008Date of Patent: January 17, 2012Assignee: OmniVision Technologies, Inc.Inventors: WeiDong Qian, Hsin-Chih Tai, Vincent Venezia, Howard E. Rhodes
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Patent number: 8080821Abstract: An array of thyristor detector devices is provided having an epitaxial growth structure with complementary types of modulation doped quantum well interfaces located between a P+ layer and an N+ layer. The thyristor detector devices operate over successive cycles that each include a sequence of two distinct modes: a setup mode and a signal acquisition mode. During the setup mode, the n-type quantum well interface and/or the p-type quantum well interface is(are) substantially emptied of charge. During the signal acquisition mode, photocurrent is generated by the thyristor detector device in response to the absorption of incident electromagnetic radiation therein, which can induce the thyristor detector device to switch from an OFF state to an ON state. The OFF/ON state of the thyristor detector device produces an output digital electrical data that corresponds to the amount of incident radiation absorbed by the thyristor detector device during the signal acquisition mode of the current cycle.Type: GrantFiled: March 18, 2008Date of Patent: December 20, 2011Assignees: The University of Connecticut, Opel, Inc.Inventor: Geoff W. Taylor
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Publication number: 20110284920Abstract: An optically triggered semiconductor switch includes an anode metallization layer; a cathode metallization layer; a semiconductor between the anode metallization layer and the cathode metallization layer and a photon source. The semiconductor includes at least four layers of alternating doping in the form P-N-P-N, in which an outer layer adjacent to the anode metallization layer forms an anode and an outer layer adjacent the cathode metallization layer forms a cathode and in which the anode metallization layer has a window pattern of optically transparent material exposing the anode layer to light. The photon source emits light having a wavelength, with the light from the photon source being configured to match the window pattern of the anode metallization layer.Type: ApplicationFiled: May 19, 2011Publication date: November 24, 2011Applicant: APPLIED PULSED POWER, INCInventors: Steven C. Glidden, Howard D. Sanders
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Patent number: 8013359Abstract: A power switching device includes an optically controlled component using a semiconducting carbon nanotube. An optical signal transmitted over an optical fiber controls the conductivity of the nanotube. The nanotube transmits a signal controlled by the optical signal to a wide-bandgap semiconductor power switch, which switches the power.Type: GrantFiled: December 30, 2004Date of Patent: September 6, 2011Inventor: John W. Pettit
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Patent number: 7948004Abstract: A self-scanning light source head comprising: a substrate, surface emitting semiconductor lasers arranged in an array on the substrate, and at least one thyristor disposed on the substrate and serving as a switching element selectively turning ON and OFF light emission of the surface emitting semiconductor lasers, and an image forming apparatus using the same are provided.Type: GrantFiled: November 14, 2008Date of Patent: May 24, 2011Assignee: Fuji Xerox Co., Ltd.Inventor: Teiichi Suzuki
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Patent number: 7910949Abstract: A power semiconductor device includes a conductive board and a switching element mounted on the conductive board and electrically connected thereto. The power semiconductor device also includes an integrated circuit mounted on the conductive board at a distance from the switching element and electrically connected thereto. The switching element turns ON/OFF a connection between first and second main electrodes in response to a control signal inputted to a control electrode. The integrated circuit includes a control circuit which controls ON/OFF the switching element and a back side voltage detection element which detects a voltage of the back side of the integrated circuit.Type: GrantFiled: October 10, 2007Date of Patent: March 22, 2011Assignee: Mitsubishi Electric CorporationInventors: Yukio Yasuda, Atsunobu Kawamoto, Shinsuke Goudo
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Patent number: 7859071Abstract: A sensing system tethered to an optical fiber for delivering optical power. A sensing system has a semiconductor device that includes photodiodes and a laser. The optical signal delivered through the optical fiber generates a current in the photodiodes that can be used to at least recharge the sensing system's power supply or bias the laser. The optical signal can be modulated to deliver data to the sensing system. The laser can be modulated to transmit data from the sensing system over the optical fiber. Because the power source can be recharged, the sensing system can also transmit and receive using an RF module.Type: GrantFiled: March 30, 2006Date of Patent: December 28, 2010Assignee: Finisar CorporationInventor: Frank Levinson
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Patent number: 7786491Abstract: A semiconductor light-emitting device includes: a substrate; a plurality of semiconductor layers grown on the substrate and including an active layer; and an electrode formed on the semiconductor layers. An opening in which at least a portion of the semiconductor layers is exposed is formed in the substrate. The electrode faces the opening in the substrate and a portion of the substrate surrounding the opening.Type: GrantFiled: February 2, 2007Date of Patent: August 31, 2010Assignee: Panasonic CorporationInventors: Tetsuzo Ueda, Kenji Orita
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Patent number: 7781854Abstract: An image sensor chip package structure includes a transparent substrate, a chip, a sealing ring, a number of conductive posts, and a number of conductive bumps. The transparent substrate has a number of through holes. The through holes pass through the transparent substrate. The chip has an active surface, an image sensitive area, and a number of die pads. The image sensitive area and the die pads are located on the active surface. The sealing ring is disposed between the chip and the transparent substrate and surrounds the image sensitive area and the die pads. The conductive posts are disposed in the through holes, respectively. Here, the chip is electrically connected with the conductive posts via the die pads. The conductive bumps are disposed on the die pads, respectively. The conductive bumps are connected with the conductive posts, respectively.Type: GrantFiled: July 31, 2008Date of Patent: August 24, 2010Assignee: Unimicron Technology Corp.Inventor: Chih-Wei Lu
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Patent number: 7728339Abstract: A micromechanical structure is described. A region of semiconductor material has a first surface, a second surface opposite to the first surface, and a lateral surface that surrounds the region of semiconductor material. Insulative material covers the first surface and the lateral surface of the region of semiconductor material to provide electrical isolation to the region of semiconductor material by forming a boundary. To form the micromechanical structure, a trench is etched in a semiconductor substrate to surround a region of the semiconductor substrate. A surface of the semiconductor substrate and the trench are oxidized to form a top oxide and a lateral oxide region. A backside of the semiconductor substrate is etched to expose a backside of the region of the semiconductor substrate and a portion of the lateral oxide.Type: GrantFiled: May 3, 2002Date of Patent: June 1, 2010Assignee: Calient Networks, Inc.Inventors: Scott G. Adams, Tim Davis
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Patent number: 7728399Abstract: Apparatuses and methods directed to an integrated circuit package having an optical component are disclosed. The package may include an integrated circuit die having at least one light sensitive region disposed on a first surface thereof. By way of example, the die may be a laser diode that emits light through the light sensitive region, or a photodetector that receives and detects light through the light sensitive region. An optical concentrator may be positioned adjacent the first surface of the first die. The optical concentrator includes a lens portion positioned adjacent the light sensitive region and adapted to focus light.Type: GrantFiled: July 22, 2008Date of Patent: June 1, 2010Assignees: National Semiconductor Corporation, The Regents of the University of CaliforniaInventors: Randall L. Walberg, Luu T. Nguyen, Robert Dahlgren, James B. Wieser, Kenneth Pedrotti, Jacob A. Wysocki
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Patent number: 7693360Abstract: On the back surface of a transparent plate having a light extracting part for outputting lights to the outside, an electrode for wiring, and an electrode for an electromagnetic shield, an optical device is flip-chip mounted right under the light extracting part, an a driver IC is flip-chip mounted at a desired position with metal bumps. When currents driving the optical device flow from the driver IC according to an electric logical signal from the outside, an optical signal is emitted from the optical device, and is output to the outside through the light extracting part. The light extracting part may be provided with a light coupling material or an optical axis converter.Type: GrantFiled: April 18, 2003Date of Patent: April 6, 2010Assignee: NEC CorporationInventors: Takanori Shimizu, Takara Sugimoto, Jun-ichi Sasaki, Kazuhiko Kurata
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Patent number: 7638814Abstract: Standard solderless connectors extend from a molded package body supporting at least one high power LED. The package includes a relatively large metal slug extending completely through the package. The LED is mounted over the top surface of the metal slug with an electrically insulating ceramic submount in-between the LED and metal slug. Electrodes on the submount are connected to the package connectors. Solderless clamping means, such as screw openings, are provided on the package for firmly clamping the package on a thermally conductive mounting board. The slug in the package thermally contacts the board to sink heat away from the LED. Fiducial structures (e,g., holes) in the package precisely position the package on corresponding fiducial structures on the board. Other packages are described that do not use a molded body.Type: GrantFiled: June 19, 2007Date of Patent: December 29, 2009Assignee: Philips Lumileds Lighting Company, LLCInventors: Franklin Wall, Jr., Peter Stormberg, Jeffrey Kmetec, Mina Farr, Li Zhang
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Patent number: 7605440Abstract: A pixel having a well-isolated charge storage region or floating diffusion region may be obtained by providing a separate P-well around the storage region or floating diffusion region. In one embodiment, a separate P-well entirely encases the storage region and is in contact with the storage region. This P-well provides an electrical barrier for preventing electrons that are generated elsewhere in the pixel from contaminating the storage region. In another embodiment, a first separate P-well encases and is in contact with the storage region and a second separate P-well encases and is in contact with the floating diffusion region.Type: GrantFiled: April 7, 2006Date of Patent: October 20, 2009Assignee: Aptina Imaging CorporationInventor: Parker Altice
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Patent number: 7592654Abstract: CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.Type: GrantFiled: November 15, 2007Date of Patent: September 22, 2009Assignee: Aptina Imaging CorporationInventors: Sandeep R. Bahl, Fredrick P. LaMaster, David W. Bigelow
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Patent number: 7525131Abstract: Disclosed is a photoelectric surface including: a first group III nitride semiconductor layer that produces photoelectrons according to incidence of ultraviolet rays; and a second group III nitride semiconductor layer provided adjacent to the first group III nitride semiconductor layer and made of a thin-film crystal having c-axis orientation in a thickness direction, the second group III nitride semiconductor layer having an Al composition higher than that of the first group III nitride semiconductor layer.Type: GrantFiled: August 29, 2006Date of Patent: April 28, 2009Assignees: National University Corporation Shizuoka University, Hamamatsu Photonics K.K.Inventors: Masatomo Sumiya, Shunro Fuke, Tokuaki Nihashi, Minoru Hagino
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Patent number: 7518158Abstract: A submount for a semiconductor light emitting device includes a semiconductor substrate having a cavity therein configured to receive the light emitting device. A first bond pad is positioned in the cavity to couple to a first node of a light emitting device received in the cavity. A second bond pad is positioned in the cavity to couple to a second node of a light emitting device positioned therein. Light emitting devices including a solid wavelength conversion member and methods for forming the same are also provided.Type: GrantFiled: November 12, 2004Date of Patent: April 14, 2009Assignee: Cree, Inc.Inventors: Bernd Keller, James Ibbetson, Peter Andrews, Gerald H. Negley, Norbert Hiller
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Patent number: 7492017Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.Type: GrantFiled: September 9, 2005Date of Patent: February 17, 2009Assignee: Intel CorporationInventors: Anand Murthy, Robert S. Chau, Tahir Ghani
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Patent number: 7492988Abstract: Planar AWG circuits and systems are disclosed that use air trench bends to increase planar circuit compactness.Type: GrantFiled: December 4, 2007Date of Patent: February 17, 2009Inventors: Gregory P. Nordin, Yongbin Lin, Seunghyun Kim
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Publication number: 20090003399Abstract: An integrated circuit is provided with a photonic device and a spot-size converter waveguide device integrated on a common substrate. The spot-size converter waveguide device provides for transformation between a larger spot-size and a smaller spot-size corresponding to the photonic device. The spot-size converter waveguide device includes at least one of a bottom mirror and top mirror, which provide highly-reflective lower and upper cladding, respectively, for vertical confinement of light propagating through the waveguide device. The top mirror overlies opposing sidewalls of the spot-converter waveguide device, which provide highly-reflective sidewall cladding for lateral confinement of light propagating through the waveguide device. Advantageously, the highly-reflective lower cladding provided by the bottom mirror limits optical loss of the waveguide device. Similarly, the highly-reflective upper cladding and sidewall cladding provided by the top mirror limits optical loss of the waveguide device.Type: ApplicationFiled: June 26, 2007Publication date: January 1, 2009Inventor: Geoff W. Taylor
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Patent number: 7466015Abstract: A supporting frame is used to solidly bridge to the two metallic contacts of a surface mount diode chip. Any bending or twisting stress between the two contacts is borne by the supporting frame instead of the diode chip. Otherwise the stress may damage the diode chip. wherein said supporting forms a cantilever over said first metallic contact and the overhanging end of the cantilever is glued to said second metallic contact.Type: GrantFiled: December 11, 2006Date of Patent: December 16, 2008Inventor: Jiahn-Chang Wu
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Patent number: 7397066Abstract: Microelectronic imagers with curved image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device includes an imager die having a substrate, a curved microelectronic image sensor having a face with a convex and/or concave portion at one side of the substrate, and integrated circuitry in the substrate operatively coupled to the image sensor. The imager die can further include external contacts electrically coupled to the integrated circuitry and a cover over the curved image sensor.Type: GrantFiled: August 19, 2004Date of Patent: July 8, 2008Assignee: Micron Technology, Inc.Inventor: Steven D. Oliver
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Patent number: 7352010Abstract: A photoelectric conversion module with a cooling function has a semiconductor element to transmit/receive an optical signal, a stem to fix the semiconductor element, a cap to cover the semiconductor element, and a lead to apply an electrical signal to the semiconductor element or to transmit an electrical signal from the semiconductor element, wherein on the stem, there is provided a heat releasing device formed of a peltiert element, and a thermal conduction member for heat absorption and a thermal conduction member for heat release provided respectively on both sides of the peltiert element, and the semiconductor element is directly disposed on the thermal conduction member for heat absorption.Type: GrantFiled: January 11, 2005Date of Patent: April 1, 2008Assignee: Hitachi Cable, Ltd.Inventors: Juhyun Yu, Yoshiaki Ishigami, Yoshinori Sunaga, Akihiro Hiruta
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Patent number: 7250674Abstract: A coolant cooled type semiconductor device capable of achieving a superior heat radiation capability is provided, while having a simple structure. While a plurality of semiconductor modules are arranged in such a manner that main surface directions of these semiconductor modules are positioned in parallel to each other in a interval along a thickness direction thereof. These semiconductor modules are sandwiched by coolant tube having folded portions with fixing members. As a consequence, both surfaces of the semiconductor module can be cooled by a single coolant tube with a uniform pinching force.Type: GrantFiled: January 5, 2006Date of Patent: July 31, 2007Assignee: Denso CorporationInventor: Seiji Inoue
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Patent number: 7233027Abstract: The invention relates to an arrangement comprising at least two different electronic semiconductor circuits (HS) in which each of the semiconductor circuits (HS) is a component made of semiconductor material and which has an electrically active surface and electronic contacts, and corresponding contacts of the semiconductor circuits are connected to one another in an electrically conductive manner. In order to simplify production, the semiconductor circuits (HS) are produced in a common support (12) made of semiconductor material and are connected to one another in an electrically conductive manner. Electrically conductive contacts (18) that are connected to the semiconductor circuits (HS) are produced on the surface of the support (12) by metallizing the support. Said support (12) has an expansion (13), which is made of the same material, forming a unit with the same, and which is provided for accommodating additional switching elements or components.Type: GrantFiled: April 17, 2002Date of Patent: June 19, 2007Assignee: Merge Optics GmbHInventors: Dag Neumeuer, Martin Brahms
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Patent number: 7214971Abstract: A semiconductor light-receiving device has a substrate including upper, middle and lower regions in its front side. A p-type layer on the lower region has a top surface including a portion on a level with the middle region. An electrode covers at least part of the boundary between the portion of the p-type layer and the middle region. An n-type layer on the p-type layer has a top surface including a portion on a level with the upper region. Another electrode covers at least part of the boundary between the portion of the n-type layer and the upper region.Type: GrantFiled: June 10, 2004Date of Patent: May 8, 2007Assignee: Hamamatsu Photonics K.K.Inventors: Minoru Niigaki, Kazutoshi Nakajima
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Patent number: 7193303Abstract: A supporting frame is used to solidly bridge to the two metallic contacts of a surface mount diode chip. Any bending or twisting stress between the two contacts is borne by the supporting frame instead of the diode chip. Otherwise the stress may damage the diode chip. wherein said supporting forms a cantilever over said first metallic contact and the overhanging end of the cantilever is glued to said second metallic contact.Type: GrantFiled: August 10, 2005Date of Patent: March 20, 2007Inventor: Jiahn-Chang Wu
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Patent number: 7112827Abstract: A light oscillation part including an active layer for generating light by current injection, a tuning layer with an intermediate layer formed between the active layer and the tuning layer, for varying an oscillation wavelength by current injection and a diffraction grating formed near the active layer and the tuning layer, and a light amplification part including an active layer for amplifying light by current injection are formed on a semiconductor substrate. Light oscillation elements having wide wavelength variation ranges and the light amplification are integrated on a semiconductor substrate, whereby wide wavelength variation ranges can be obtained and the output light can be much increased.Type: GrantFiled: October 22, 2003Date of Patent: September 26, 2006Assignee: Fujitsu LimitedInventors: Akinori Hayakawa, Yoshihiro Sato, Ken Morito, Norihiko Sekine
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Patent number: 7102185Abstract: An interline transfer type image sensing device that can be operated at high speed and with low image smear is described. The device incorporates a refractory metal layer which is used for both a light shield over the vertical charge transfer region and as a wiring layer for low resistance strapping of poly crystalline silicon (polysilicon) gate electrodes for the vertical charge transfer region. Plugs provided by a separate metallization layer connect the refractory light shield to the polysilicon gate electrode. These plugs allow high temperature processing after refractory light shield patterning for improved sensor performance without degradation of the polysilicon gate electrode or the refractory lightshield layer.Type: GrantFiled: June 21, 2004Date of Patent: September 5, 2006Assignee: Eastman Kodak CompanyInventors: David N. Nichols, David L. Losee, Christopher Parks
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Patent number: 7095101Abstract: A supporting frame is used to solidly bridge to the two metallic contacts of a surface mount diode chip. Any bending or twisting stress between the two contacts is borne by the supporting frame instead of the diode chip. Otherwise the stress may damage the diode chip.Type: GrantFiled: December 3, 2002Date of Patent: August 22, 2006Inventor: Jiahn-Chang Wu
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Patent number: 7057214Abstract: Semiconductor switches, such as thyristors, may be light activated by introducing the light into the switch via a groove having a sloped surface to receive the triggering light. The use of a sloped surface increases the surface path length between points of different electrical potential in the groove and, therefore, reduces the likelihood of electrical breakdown on the groove wall. In one particular embodiment, a light-activated thyristor includes a semiconductor anode layer, an n-base layer, a p-base layer and a semiconductor cathode layer disposed parallel to a thyristor plane. A thyristor axis lies perpendicular to the thyristor plane. A groove having a light refracting side wall extends into the thyristor from the anode layer. A portion of the light refracting side wall is disposed non-parallel to the thyristor plane and to the thyristor axis, and extends in the n-drift layer.Type: GrantFiled: July 1, 2003Date of Patent: June 6, 2006Assignee: Optiswitch Technology CorporationInventors: David M. Giorgi, Tajchai Navapanich
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Patent number: 6995443Abstract: An integrated circuit with a number of optical fibers that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical fibers include a cladding layer and a core formed in the high aspect ratio hole. These optical fibers are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.Type: GrantFiled: February 5, 2004Date of Patent: February 7, 2006Assignee: Micron Technology, Inc.Inventors: Joseph E. Geusic, Kie Y. Ahn, Leonard Forbes
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Patent number: 6900508Abstract: A flat filter layer is received between upper and lower mold portions of a mold for packaging an integrated circuit sensor device, held by the mold over and in contact with the integrated circuit's sensing surface, in light compression between the sensing surface and a mold surface. The filter layer includes slots allowing passage of injected encapsulating material to cover the integrated circuit die, with overlap portions embedded in the encapsulating material, while preventing such encapsulating material from flowing onto the sensing surface. The filter layer may be, for example, a liquid and/or light filter, and may include a protective or supportive backing. The filter is thus affixed to the packaged integrated circuit sensor device, while mold residue is reduced and mold life extended.Type: GrantFiled: April 16, 2002Date of Patent: May 31, 2005Assignee: STMicroelectronics, Inc.Inventors: Anthony M. Chiu, Harry Michael Siegel
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Publication number: 20040217373Abstract: An integrated circuit die includes optical interconnect ports on a first side and electrical interconnect ports on a second side.Type: ApplicationFiled: April 30, 2003Publication date: November 4, 2004Applicant: Intel CorporationInventors: Tanay Karnik, Jianping Xu
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Patent number: 6809355Abstract: A solid-state imaging device having a gate structure including an oxide film and a nitride film includes upper layer films (for example, a planarization film, an insulating film, and a protective film) allowing ultraviolet rays having a wavelength of 400 nm or less to pass therethrough; and a metal made shield film or an organic film capable of absorbing the ultraviolet rays formed in such a manner as to cover a region of the gate structure (for example, an output gate and a reset gate), excluding a light receiving portion and a transfer portion, of the solid-state imaging device. With this configuration, it is possible to prevent the shift of a threshold voltage Vth, and hence to enhance the reliability of the transfer or reset of electric charges.Type: GrantFiled: March 30, 2001Date of Patent: October 26, 2004Assignee: Sony CorporationInventor: Kazushi Wada
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Patent number: 6614055Abstract: A surface light-emitting element having improved external light emission efficiency and a self-scanning light-emitting device using this surface light-emitting element are provided. To improve external light-emission efficiency, the light-emitting center is shifted to an area where there is no light shielding layer thereon. When the surface light-emitting element is a surface light-emitting thyristor of the PNPN structure, it is necessary to have such a construction that part of the injected current is prevented from flowing toward the gate electrode to improve external light emission efficiency. The self-scanning light-emitting device of this invention is accomplished by using this type of surface light-emitting element.Type: GrantFiled: November 10, 2000Date of Patent: September 2, 2003Assignee: Nippon Sheet Glass Co., Ltd.Inventors: Yukihisa Kusuda, Seiij Ohno, Shunsuke Ohtsuka