Six Or More Semiconductor Layers Of Alternating Conductivity Types (e.g., Npnpnpn Structure) Patents (Class 257/120)
  • Patent number: 10748818
    Abstract: In various examples, a method and apparatus are provided to achieve dynamic biasing to mitigate electrical stress. Described examples include a device includes a first resistor portion having a first terminal and a second terminal, and a second resistor portion having a third terminal and a fourth terminal. The device also includes a well in a substrate proximate to the first resistor portion and the second resistor portion and an insulating layer between the well and the first resistor portion and the second resistor portion. The device also includes a transistor having a control terminal coupled to the second terminal of the first resistor portion and the third terminal of the second resistor portion, the transistor having a first current-handling terminal coupled to a first voltage and a second current-handling terminal coupled to a current source and to the well.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tathagata Chatterjee, Steven Loveless, James Robert Todd, Andrew Strachan
  • Patent number: 10698334
    Abstract: In a light emitting element array in which a plurality of components having multiple light emitting thyristors connected to a single shift thyristor are arranged in a plurality of lines, the density of the light emitting thyristor is increased without reduction in the amount of light emission of each of the light emitting thyristors. In the light emitting element array in which multiple light emitting thyristors are formed on a single island structure and the multiple light emitting thyristors are connected to a single shift thyristor, a first element-isolating groove that element-isolates the multiple light emitting thyristors from each other inside the single island structure is formed shallower than a second element-isolating groove that element-isolates the island structure.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: June 30, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Koichiro Nakanishi
  • Patent number: 10387344
    Abstract: In one embodiment, a Light Emitting Diode (LED) driving device for driving a plurality of LEDs has a switching matrix utilizing a plurality of one of a turn off thyristors or turn off triacs coupled to the plurality of LEDs. A controller is coupled to the switching matrix responsive to a voltage of a rectified AC halfwave, wherein combinations of the plurality of LEDs are altered to ensure a maximum operating voltage of the plurality of LEDs is not exceeded. A current limiting device is coupled to the combinations of the plurality of LED to regulate current.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 20, 2019
    Inventors: David Schie, Mike Ward
  • Patent number: 10326010
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface, first to eighth regions, a first thyristor, and a second thyristor. The seventh region with the impurity concentration higher than that of the first region is formed in the first region while being apart from the sixth region electrically connected to the gate electrode, and being electrically connected to the first electrode. The eighth region with the impurity concentration higher than that of the third region is formed in contact with the second surface side of the third region and the fourth region, and with the second surface, while being electrically connected to the fourth region by the second electrode. The seventh region has the impurity concentration higher than that of the first region. The eighth region has the impurity concentration higher than that of the third region.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: June 18, 2019
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Yukihiro Shibata, Tadashi Inoue
  • Patent number: 9837554
    Abstract: The disclosure relates to a data transmission system (100) comprising a signal line (101) and a ground line (103). A first signal path (102) is provided between the signal line (101) and the ground line (103). The first signal path (102) comprises a Shockley diode (104) having a cathode (106) and an anode (108). The cathode (106) is connected to the ground line (103) and the anode (108) is connected to the signal line (101).
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: December 5, 2017
    Assignee: Nexperia B.V.
    Inventor: Hans-Martin Ritter
  • Patent number: 9741571
    Abstract: Disclosed is a bipolar semiconductor device, comprising a semiconductor body having a first surface; and a base region of a first doping type and a first emitter region in the semiconductor body, wherein the first emitter region adjoins the first surface and comprises a plurality of first type emitter regions of a second doping type complementary to the first doping type, a plurality of second type emitter regions of the second doping type, a plurality of third type emitter regions of the first doping type, and a recombination region comprising recombination centers, wherein the first type emitter regions and the second type emitter regions extend from the first surface into the semiconductor body, wherein the first type emitter regions have a higher doping concentration and extend deeper into the semiconductor body from the first surface than the second type emitter regions, wherein the third type emitter regions adjoin the first type emitter regions and the second type emitter regions, and wherein the recom
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: August 22, 2017
    Assignee: Infineon Technologies AG
    Inventors: Roman Baburske, Christian Jaeger, Franz-Josef Niedernostheide, Hans-Joachim Schulze, Antonio Vellei
  • Patent number: 9520492
    Abstract: A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and formed in the substrate, a drift region formed in the high-voltage well, and a buried layer having the first conductivity type formed below the high-voltage well and vertically aligned with the drift region.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: December 13, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Ching-Lin Chan, Shyi-Yuan Wu, Cheng-Chi Lin
  • Patent number: 9443754
    Abstract: A semiconductor device includes a substrate, a high-voltage N-well (HVNW) disposed in the substrate, a bulk P-well disposed in the substrate and adjacent to an edge of the HVNW, a high-voltage (HV) diode disposed in the HVNW, the HV diode including a HV diode P-well disposed in the HVNW and spaced apart from the edge of the HVNW, and an N-well disposed in the HVNW and between the HV diode P-well and the bulk P-well. A doping concentration of the N-well is higher than a doping concentration of the HVNW.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: September 13, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Jui Chang, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 9054183
    Abstract: The present invention provides AccuFETs with single or dual accumulation channels and methods for manufacturing the same. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: June 9, 2015
    Assignee: United Silicon Carbide, Inc.
    Inventors: Leonid Fursin, Xueqing Li
  • Patent number: 9006780
    Abstract: Between a back surface electrode and an electrode, a first thyristor is formed of fifth and seventh semiconductor regions, a substrate region, first and second semiconductor regions and a third semiconductor region, and a second thyristor is formed of the second and first semiconductor regions, the substrate region, the seventh and fifth semiconductor regions and a sixth semiconductor region. Depths from the surface of the semiconductor substrate to bottom surfaces of the third and fourth semiconductor regions are 20 ?m or more. The second semiconductor region with a high impurity concentration is enclosed by the first semiconductor region with a low impurity concentration, and a difference between a depth from the surface of the semiconductor substrate to the bottom of the second semiconductor region and a depth from the surface of the semiconductor substrate to the bottom of the first semiconductor region is less than 10 ?m.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: April 14, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Aki Moroda, Kosuke Miyazaki
  • Publication number: 20140175507
    Abstract: Between a back surface electrode and an electrode, a first thyristor is formed of fifth and seventh semiconductor regions, a substrate region, first and second semiconductor regions and a third semiconductor region, and a second thyristor is formed of the second and first semiconductor regions, the substrate region, the seventh and fifth semiconductor regions and a sixth semiconductor region. Depths from the surface of the semiconductor substrate to bottom surfaces of the third and fourth semiconductor regions are 20 ?m or more. The second semiconductor region with a high impurity concentration is enclosed by the first semiconductor region with a low impurity concentration, and a difference between a depth from the surface of the semiconductor substrate to the bottom of the second semiconductor region and a depth from the surface of the semiconductor substrate to the bottom of the first semiconductor region is less than 10 ?m.
    Type: Application
    Filed: December 17, 2013
    Publication date: June 26, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Aki Moroda, Kosuke Miyazaki
  • Patent number: 8664728
    Abstract: A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: March 4, 2014
    Assignee: Volterra Semiconductor Corporation
    Inventors: Yang Lu, Budong You, Marco A. Zuniga, Hamza Yilmaz
  • Patent number: 8633509
    Abstract: An apparatus and method for high voltage transient electrical overstress protection are disclosed. In one embodiment, the apparatus includes an internal circuit electrically connected between a first node and a second node; and a protection circuit electrically connected between the first node and the second node. The protection circuit is configured to protect the internal circuit from transient electrical overstress events while maintaining a relatively high holding voltage upon activation.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: January 21, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Javier Alejandro Salcedo, Karl Sweetland
  • Patent number: 8592881
    Abstract: An organic light emitting element includes an organic light emitting diode formed on a substrate, coupled to a transistor including a gate, a source and a drain and including a first electrode, an organic thin film layer and a second electrode; a photo diode formed on the substrate and having a semiconductor layer including a high-concentration P doping region, a low-concentration P doping region, an intrinsic region and a high-concentration N doping region; and a controller that controls luminance of light emitted from the organic light emitting diode, to a constant level by controlling a voltage applied to the first electrode and the second electrode according to the voltage outputted from the photo diode.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: November 26, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-gyu Lee, Byoung-deog Choi, Hye-hyang Park, Ki-ju Im
  • Patent number: 8564047
    Abstract: A semiconductor power device having shielded gate structure integrated with a trenched clamp diode formed in a semiconductor silicon layer, wherein the shielded gate structure comprises a shielded electrode formed by a first poly-silicon layer and a gate electrode formed by a second poly-silicon layer. The trenched clamp diode is formed by the first poly-silicon layer. A shielded gate mask used to define the shielded gate is also used to define the trenched clamp diode. Therefore, one poly-silicon layer and a mask for the trenched clamp diode are saved.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: October 22, 2013
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20130270605
    Abstract: An apparatus and method for high voltage transient electrical overstress protection are disclosed. In one embodiment, the apparatus includes an internal circuit electrically connected between a first node and a second node; and a protection circuit electrically connected between the first node and the second node. The protection circuit is configured to protect the internal circuit from transient electrical overstress events while maintaining a relatively high holding voltage upon activation.
    Type: Application
    Filed: June 7, 2013
    Publication date: October 17, 2013
    Inventors: Javier Alejandro Salcedo, Karl Sweetland
  • Patent number: 8476673
    Abstract: A diode has a semiconductor layer and cathode and anode electrodes on a surface of the semiconductor layer. The semiconductor layer has cathode and anode regions respectively contacting the cathode and anode electrodes. The anode region has a first diffusion region having high surface concentration, a second diffusion region having intermediate surface concentration, and a third diffusion region having low surface concentration. The first diffusion region is covered with the second and third diffusion regions. The second diffusion region has a first side surface facing the cathode region, a second side surface opposite to the cathode region, and a bottom surface extending between the first and second side surfaces. The third diffusion region covers at least one of the first corner part connecting the first side surface with the bottom surface and the second corner part connecting the second side surface with the bottom surface.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: July 2, 2013
    Assignee: DENSO CORPORATION
    Inventors: Norihito Tokura, Satoshi Shiraki, Shigeki Takahashi, Shinya Sakurai, Takashi Suzuki
  • Patent number: 8466489
    Abstract: An apparatus and method for high voltage transient electrical overstress protection are disclosed. In one embodiment, the apparatus includes an internal circuit electrically connected between a first node and a second node; and a protection circuit electrically connected between the first node and the second node. The protection circuit is configured to protect the internal circuit from transient electrical overstress events while maintaining a relatively high holding voltage upon activation.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: June 18, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Javier A. Salcedo, Karl Sweetland
  • Patent number: 8242534
    Abstract: The present invention improves the performance of a semiconductor device formed with a triac. A thyristor is formed between a back surface electrode and an electrode by p-type semiconductor regions, an n-type substrate region, p-type semiconductor regions and an n-type semiconductor region. A thyristor is formed therebetween by the p-type semiconductor regions, the n-type substrate region, the p-type semiconductor regions and an n-type semiconductor region. The two thyristors are opposite in the direction of currents flowing between the back surface electrode and the electrode. The p-type semiconductor region of a high impurity concentration is formed so as to be internally included in the p-type semiconductor region of a low impurity concentration. The p-type semiconductor region of a low impurity concentration is interposed between the p-type semiconductor region of a high impurity concentration and the n-type substrate region.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: August 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Aki Moroda, Kosuke Miyazaki
  • Publication number: 20120199874
    Abstract: An apparatus and method for high voltage transient electrical overstress protection are disclosed. In one embodiment, the apparatus includes an internal circuit electrically connected between a first node and a second node; and a protection circuit electrically connected between the first node and the second node. The protection circuit is configured to protect the internal circuit from transient electrical overstress events while maintaining a relatively high holding voltage upon activation.
    Type: Application
    Filed: February 4, 2011
    Publication date: August 9, 2012
    Applicant: Analog Devices, Inc.
    Inventors: Javier A. Salcedo, Karl Sweetland
  • Patent number: 8120023
    Abstract: The present invention is directed to novel front side illuminated, back side contact photodiodes and arrays thereof. In one embodiment, the photodiode has a substrate with at least a first and a second side and a plurality of electrical contacts physically confined to the second side. The electrical contacts are in electrical communication with the first side through a doped region of a first type and a doped region of a second type, each of the regions substantially extending from the first side through to the second side. In another embodiment, the photodiode comprises a wafer with at least a first and a second side; and a plurality of electrical contacts physically confined to the second side, where the electrical contacts are in electrical communication with the first side through a diffusion of a p+ region through the wafer and a diffusion of an n+ region through the wafer.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: February 21, 2012
    Assignee: UDT Sensors, Inc.
    Inventors: Peter Steven Bui, Narayan Dass Taneja
  • Patent number: 8035115
    Abstract: A semiconductor apparatus includes a substrate; and a plurality of semiconductor thin films formed on said substrate, each of said semiconductor thin films having a pn-junction, and electrodes of p-type and n-type for injecting carriers to the pn-junction, wherein said semiconductor thin films are formed so that all or a part of said pn-junctions are connected serially. As different from a semiconductor thin film constituted of a single pn-junction, the light emission with the invented semiconductor apparatus is the summation of the light emission intensities of the entire pn-junctions, so that the light emitting intensity can be increased largely.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: October 11, 2011
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Takahito Suzuki, Hiroshi Kurokawa, Taishi Kaneto
  • Publication number: 20110220960
    Abstract: The present invention improves the performance of a semiconductor device formed with a triac. A thyristor is formed between a back surface electrode and an electrode by p-type semiconductor regions, an n-type substrate region, p-type semiconductor regions and an n-type semiconductor region. A thyristor is formed therebetween by the p-type semiconductor regions, the n-type substrate region, the p-type semiconductor regions and an n-type semiconductor region. The two thyristors are opposite in the direction of currents flowing between the back surface electrode and the electrode. The p-type semiconductor region of a high impurity concentration is formed so as to be internally included in the p-type semiconductor region of a low impurity concentration. The p-type semiconductor region of a low impurity concentration is interposed between the p-type semiconductor region of a high impurity concentration and the n-type substrate region.
    Type: Application
    Filed: February 1, 2011
    Publication date: September 15, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Aki MORODA, Kosuke MIYAZAKI
  • Patent number: 7893457
    Abstract: A semiconductor device includes at least one cell including a base region of a first conductivity type having disposed therein at least one emitter region of a second conductivity type, a first well region of a second conductivity type, a second well region of a first conductivity type, a drift region of a second conductivity type, a collector region of a first conductivity type, and a collector contact. Each cell is disposed within the first well region, and the first well region is disposed within the second well region. The device further includes a first gate in communication with a base region so that a MOSFET channel can be formed between an emitter region and the first well region, and at least one embedded region embedded in the first well region. The device is configured such that during operation of the device a depletion region at a junction between the base region and the first well region can extend to a junction between the first well region and the second well region.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: February 22, 2011
    Assignee: ECO Semiconductors Ltd.
    Inventors: Sankara Narayanan Ekkanath Madathil, Mark Robert Sweet, Konstantin Vladislavovich Vershinin
  • Patent number: 7883941
    Abstract: A method for fabricating a memory device is provided. A semiconductor layer is provided that includes first, second, third and fourth well regions of a first conductivity type in the semiconductor layer. A first gate structure overlies the first well region, a second gate structure overlies the second well region, a third gate structure overlies the third well region and is integral with the second gate structure, and a fourth gate structure overlies the fourth well region. Sidewall spacers are formed adjacent a first sidewall of the first gate structure and sidewalls of the second through fourth gate structures. In addition, an insulating spacer block is formed overlying a portion of the first well region and a portion of the first gate structure. The insulating spacer block is adjacent a second sidewall of the first gate structure.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: February 8, 2011
    Assignee: GlobalFoundries Inc.
    Inventor: Hyun-Jin Cho
  • Patent number: 7868387
    Abstract: A high-voltage, low-leakage, bidirectional electrostatic discharge (ESD, or other electrical overstress) protection device includes a doped well disposed between the terminal regions and the substrate. The device includes an embedded diode for conducting current in one direction, and a transistor feedback circuit for conducting current in the other direction. Variations in the dimensions and doping of the doped well, as well as external passive reference via resistor connections, allow the circuit designer to flexibly adjust the operating characteristics of the device, such as trigger voltage and turn-on speed, to suit the required mixed-signal operating conditions.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: January 11, 2011
    Assignee: Analog Devices, Inc.
    Inventors: Javier A. Salcedo, Jean-Jacques Hajjar, Todd Thomas
  • Patent number: 7804150
    Abstract: A field effect transistor includes a trench gate extending into a semiconductor region. The trench gate has a front wall facing a drain region and a side wall perpendicular to the front wall. A channel region extends along the side wall of the trench gate, and a drift region extends at least between the drain region and the trench gate. The drift region includes a stack of alternating conductivity type silicon layers.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: September 28, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Chang-ki Jeon, Gary Dolny
  • Patent number: 7554155
    Abstract: A power semiconductor device has a first main electrode formed along a surface of a substrate, a first semiconductor layer of first conductive type electrically connected to the first main electrode, a cyclic structure section which is formed on the first semiconductor layer and has second semiconductor layers of first conductive type and third semiconductor layers of second conductive type alternately and cyclically formed along the surface of the substrate, a fourth semiconductor layer of second conductive type selectively formed on a part of the second and third semiconductor layers, a fifth semiconductor layer of first conductive type selectively formed on the fourth semiconductor layer, a second main electrode contacted the fourth and fifth semiconductor layers, a control electrode disposed adjacent via a first insulating film on the second, fourth and fifth semiconductor layers, and a depletion layer blocking section which is formed outside of the cyclic structure section and prevents a depletion layer
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: June 30, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Ichiro Omura
  • Patent number: 7465964
    Abstract: A high voltage/power semiconductor device has a substrate, an insulating layer on the substrate, and a semiconductor layer on the insulating layer. Low and high voltage terminals are connected to the semiconductor layer. The device has a control terminal. The semiconductor layer includes a drift region and a relatively highly doped injector region between the drift region and the high voltage terminal. The device has a relatively highly doped region in electrical contact with the highly doped injector region and the high voltage terminal and forming a semiconductor junction with the substrate. The combination of the insulating layer and the relatively highly doped region of the first conductivity type effectively isolate the highly doped injector region from the substrate.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: December 16, 2008
    Assignee: Cambridge Semiconductor Limited
    Inventor: Florin Udrea
  • Patent number: 7332749
    Abstract: A compact, inexpensive static induction thyristor (SIThy) which is less likely to be broken down at a high voltage rise-up rate during operation and which is used in a high-voltage pulse generator capable of generating a high-voltage short pulse is provided. Thicknesses and impurity concentrations of a base region and a buffer region are determined such that a peak voltage obtained by a peak current at which a punch-through state is brought about does not exceed a breakdown voltage of the SIThy. Such design can achieve an SIThy having a self protecting function of autonomously preventing its breakdown without compromising a turn-on performance in which the peak voltage does not drastically exceed the breakdown voltage of the SIThy even when the peak current increases. Further, a compact SIThy capable of generating a short pulse can be achieved by reducing a gate-channel current-carrying area to a minimum.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: February 19, 2008
    Assignee: NGK Insulators, Ltd.
    Inventors: Naohiro Shimizu, Takayuki Sekiya
  • Patent number: 7317213
    Abstract: A semiconductor device includes: a center region; a periphery region; and a semiconductor layer including pairs of a first region having a first impurity amount and a second region having a second impurity amount. The first and the second regions are alternately aligned in a plane. The periphery region includes an utmost outer and an utmost inner periphery pairs. The utmost outer periphery pair has a difference between the second and the first impurity amounts, which is smaller than a maximum difference in the periphery region. The utmost inner periphery pair has a difference between the second and the first impurity amounts, which is larger than a difference in the center region.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: January 8, 2008
    Assignee: DENSO CORPORATION
    Inventors: Hitoshi Yamaguchi, Tomoatsu Makino, Yoshiyuki Hattori, Kyoko Okada
  • Patent number: 7145185
    Abstract: The invention concerns a voltage-controlled triac-type component, formed in a N-type substrate (1) comprising first and second vertical thyristors (Th1, Th2), a first electrode (A2) of the first thyristor, on the front side of the component, corresponding to a first N-type region (6) formed in a first P-type box (5), the first box corresponding to a first electrode (A2) of the second thyristor, the first box containing a second N-type region (8); and a pilot structure comprising, above an extension of a second electrode region (4) of the second thyristor, a second P-type box (11) containing third and fourth N-type regions, the third region (12) and a portion of the second box (11) being connected to a gate terminal (G), the fourth region (13) being connected to the second region (8).
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: December 5, 2006
    Assignee: STMicroelectronics S.A.
    Inventor: Jean-Michel Simmonet
  • Patent number: 7126166
    Abstract: In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The body of semiconductor material includes alternating layers of opposite conductivity type that extend between a trench drain region and a trench gate structure. The trench gate structure controls at least one sub-surface channel region. The body of semiconductor material provides sub-surface drift regions to reduce on resistance without increasing device area.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: October 24, 2006
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Rajesh S. Nair, Shanghui Larry Tu, Zia Hossain, Mohammed Tanvir Quddus
  • Patent number: 7064384
    Abstract: A semiconductor device comprises: a first main electrode; a second main electrode; a semiconductor base region of a first conductivity type; a gate electrode provided in a trench through an insulating film, the trench being formed to penetrate the semiconductor base region; and a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type provided under the semiconductor base region. A flow of a current between the first and second main electrodes when a voltage of a predetermined direction is applied between these electrodes is controllable in accordance with a voltage applied to the gate electrode. A depleted region extends from a junction between the first and the second semiconductor regions reaching the trench.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: June 20, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuma Hara, Mitsuhiko Kitagawa
  • Patent number: 7053423
    Abstract: A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, a base region and an adjacent emitter region of a thyristor are doped such that the emitter region has a lightly-doped portion having a light dopant concentration, relative to the base region. In one embodiment, the thyristor is implemented in a memory circuit, wherein the emitter region is coupled to a reference voltage line and a control port is arranged for capacitively coupling to the thyristor for controlling current flow therein. In another implementation, the thyristor is formed on a buried insulator layer of a silicon-on-insulator (SOI) structure. With these approaches, current flow in the thyristor, e.g., for data storage therein, can be tightly controlled.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: May 30, 2006
    Assignee: T-RAM, Inc.
    Inventors: Farid Nemati, Scott Robins, Andrew Horch
  • Patent number: 7038234
    Abstract: A super-lattice thermoelectric device. The device includes p-legs and n-legs, each leg having a large number of alternating layers of two materials with differing electron band gaps. The n-legs in the device are comprised of alternating layers of silicon and silicon germanium. The p-legs includes alternating layers of B4C and B9C. In preferred embodiments the layers are about 100 angstroms thick. Applicants have fabricated and tested a first Si/SiGe (n-leg) and B4C/B9C (p-leg) quantum well thermocouple. Each leg was only 11 microns thick on a 5 micron Si substrate. Nevertheless, in actual tests the thermocouple operated with an amazing efficiency of 14 percent with a Th of 250 degrees C. Thermoelectric modules made according to the present invention are useful for both cooling applications as well as electric power generation. This preferred embodiment is a thermoelectric 10×10 egg crate type module about 6 cm×6 cm×0.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: May 2, 2006
    Assignee: Hi-Z Technology, Inc.
    Inventors: Saeid Ghamaty, Norbert B. Elsner, John C. Bass
  • Patent number: 7002218
    Abstract: An ESD-protection structure is located substantially under an integrated circuit bond pad. This ESD-protection structure is formed as a low capacitance structure by inserting a forward diode between the bond pad and the ESD clamp circuit. Placing the ESD-protection structure under the bond pad eliminates parasitic substrate capacitance and utilizes a parasitic PNP transistor formed from the inserted forward biased diode. The ESD-protection structure includes adjacent alternating P+ and N+ diffusions located substantially under a bond pad to be ESD protected. The P+ diffusions are connected to the bond pad metal with metal vias through an insulating layer. The N+ diffusions are adjacent to the P+ diffusions. An N+ diffusion surrounds the N+ and P+ diffusions, and ties together the N+ diffusions so as to form a continuous N+ diffusion completely around each of the P+ diffusions. An N? well is located substantially under the N+ and P+ diffusions.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: February 21, 2006
    Assignee: Microchip Technology Incorporated
    Inventor: Randy L. Yach
  • Patent number: 6995408
    Abstract: A Schottky barrier diode 44 is formed between a P-gate diffusion region 33 and an N-type silicon substrate 31 in a photothyristor on a CH1 side and a photothyristor on a CH2 side. With this arrangement, the injection of minority carriers from the P-gate diffusion region 33 to the N-type silicon substrate 31 is restrained to reduce the amount of remaining carriers, and an excessive amount of carriers remaining in the N-type silicon substrate 31 during commutation has a reduced chance of moving toward the opposite channel side, allowing the commutation characteristic to be improved. Therefore, by a combination with an LED, there can be provided a light-fired coupler for firing and controlling the load.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: February 7, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Mitsuru Mariyama, Masaru Kubo
  • Patent number: 6965130
    Abstract: A semiconductor device including a semiconductive body having formed therein an active region and a termination feature which includes spaced field rings disposed around the active region and diffusion rings of the same conductivity type as, but different conductivity than the semiconductive body formed between each pair of field rings.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: November 15, 2005
    Assignee: International Rectifier Corporation
    Inventor: Milton J. Boden
  • Patent number: 6870202
    Abstract: A pnpn thyristor element Thy1 and six pn diode elements D1, D2, D3, D4, D5, and D6 are formed in a semiconductor substrate of a first conductivity type, and separated into six regions by a diffusion layer of a second conductivity type which also functions as the anode of the thyristor element Thy1. A double isolation diffusion layer is disposed between the region of the thyristor element Thy1 and three pn diode elements D1 ·D2 and D6, and the region of the three remaining pn diodes D3, D4, and D5. Surface connection is performed to provide a balance type surge protection circuit.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: March 22, 2005
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventor: Ritsuo Oka
  • Patent number: 6838707
    Abstract: A bi-directional silicon controlled rectifier formed in a silicon layer and disposed over shallow trench isolations and therefore electrically isolated from the substrate to be insensitive to substrate noise for electrostatic discharge protection an electrostatic discharge protection device that includes a semiconductor substrate, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first p-type portion and the first n-type portion, a second n-type portion, a third p-type portion, a third n-type portion contiguous with the third p-type portion, and a fourth p-type portion contiguous with the third p-type portion and the third n-type portion, wherein at least one of the first p-type portion, second p-type portion, third p-type portion, fourth p-type portion, first n-type portion, second n-type portion, and third n-type portion overlaps the isolation structure.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: January 4, 2005
    Assignee: Industrial Technology Research Institute
    Inventor: Chyh-Yih Chang
  • Patent number: 6700141
    Abstract: A reliable super-junction semiconductor device is provided that facilitates relaxing the tradeoff relation between the on-resistance and the breakdown voltage and improving the avalanche withstanding capability under an inductive load. The super-junction semiconductor device includes an active region including a thin first alternating conductivity type layer and a heavily doped n+-type intermediate drain layer between first alternating conductivity type layer and an n++-type drain layer, and a breakdown withstanding region including a thick second alternating conductivity type layer. Alternatively, active region includes a first alternating conductivity type layer and a third alternating conductivity type layer between first alternating conductivity type layer and n++-type drain layer, third alternating conductivity type layer being doped more heavily than first alternating conductivity type layer.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: March 2, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Susumu Iwamoto, Tatsuhiko Fujihira, Katsunori Ueno, Yasuhiko Onishi, Takahiro Sato
  • Publication number: 20030034500
    Abstract: High quality epitaxial layers of monocrystalline materials (106) can be grown overlying monocrystalline substrates (102) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating Zintl buffer layer (104) on a silicon wafer. Any lattice mismatch between the monocrystalline layer (106) and the underlying silicon substrate (102) is absorbed by the Zintl interface layer (104).
    Type: Application
    Filed: August 15, 2001
    Publication date: February 20, 2003
    Applicant: MOTOROLA, INC.
    Inventors: Alexander A. Demkov, Zhiyi Yu, Jamal Ramdani
  • Patent number: 6486501
    Abstract: The invention relates to a component having a rectifying function, fulfilled by means of charge transfer by ions. To this end, the component is composed of multiple layers which have, successively, an asymmetric energy level course, and an electric field applied to these multiple layers.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: November 26, 2002
    Assignee: Forschungszentrum Julich GmbH
    Inventors: Klaus W. Kehr, Kiaresch Mussawisade, Thomas Wichmann, Ulrich Poppe
  • Patent number: 6066863
    Abstract: A lateral semiconductor device, such as an LIGBT, LMOSFET, lateral bipolar transistor, lateral thyristor, or lateral MOS control thyristor, includes a device area surrounded by an n-type region in an n-channel lateral semiconductor device or by a p-type region in a p-channel lateral semiconductor device. Connecting the n-type region in the n-channel lateral semiconductor device or the p-type region in the p-channel lateral semiconductor device at a same potential as a first main electrode suppresses operation of parasitic transistors, as well as prevents carrier accumulation in isolated regions or a substrate. As a result, a switching loss of the lateral semiconductor device is greatly reduced, a switching speed of the lateral semiconductor device is improved, and a current capacity of the lateral semiconductor device is increased.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: May 23, 2000
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Naoto Fujishima
  • Patent number: 6037613
    Abstract: In a bidirectional photothyristor formed on a single N type silicon substrate, a distance between a P-gate diffusion region of one thyristor and an anode diffusion region of another thyristor opposed thereto is set to be 40 to 1,000 .mu.m, preferably, 70 to 600 .mu.m, thereby eliminating a malfunction caused by a noise due to a differentiation circuit which is composed of parasitic resistors and junction capacitances. In a field portion between the P-gate diffusion region and the anode diffusion region, an oxygen-doped semi-insulating film is formed via an SiO.sub.2 film, and an Al conductor is removed to form a field light receiving portion. Unlike a P-gate light receiving portion formed in the P-gate diffusion region, the field light receiving portion does not involve a junction capacitance. Therefore, a light sensitivity can be enhanced without lowering a dV/dt resistance.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: March 14, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Mitsuru Mariyama
  • Patent number: 5955750
    Abstract: A four-region (PNPN) semiconductor device structure that provides greater flexibility in the setting of PN junction breakdown conditions. The four-region (PNPN) semiconductor device includes an additional N-type body at the junction between the inner N-type region and the inner P-type region, the additional N-type body including a first part adjacent to a second part, the first and second parts having different impurity concentrations from one another, both being of high impurity concentration than the inner N-type region and of lower impurity concentration than the inner P-type region.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: September 21, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Stephen W. Byatt
  • Patent number: 5952728
    Abstract: A thermoelectric conversion module having a large capacity and a curved surface which can be secured to a corresponding curved surface of a base member is manufactured by inserting N type and P type semiconductor strips into through holes formed in a honeycomb structural body, filling spaces between walls defining the through holes and the semiconductor strips with an electrically insulating filler members made of an easily deformable material such as polyimide resin and silicone resin, cutting the honeycomb structural body into a plurality of thermoelectric conversion module main bodies each having a desired surface configuration, and providing metal electrodes on both surfaces of a thermoelectric conversion module main body such that alternate N type and P type semiconductor elements are connected in cascade.
    Type: Grant
    Filed: November 7, 1996
    Date of Patent: September 14, 1999
    Assignees: NGK Insulators, Ltd., Nissan Motor Co., Ltd.
    Inventors: Yuichiro Imanishi, Makoto Miyoshi, Tetsuo Watanabe, Keiko Kushibiki, Kazuhiko Shinohara, Masakazu Kobayashi, Kenji Furuya
  • Patent number: 5777346
    Abstract: One embodiment of a metal oxide semiconductor controlled thyristor in accordance with the present invention has a semiconductor wafer with opposing first and second surfaces. The wafer includes first through sixth sequential regions which are disposed one above the other. The first region includes the second surface of the wafer and each of the second through sixth regions has at least a portion which extends up to the first surface. The first, third, and sixth regions have a first type of conductivity and the second, fourth, and fifth regions have a second type of conductivity. A trench with a bottom and sidewalls extends from the first surface and passes through the fourth, fifth, and sixth regions and into the third region. A dielectric material coats the bottom and sidewalls of the trench and a conductive material fills the remainder of the trench.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: July 7, 1998
    Assignee: Harris Corporation
    Inventor: Victor Albert Keith Temple
  • Patent number: 5757033
    Abstract: A bidirectional thyristor structure with a single MOS gate controlled turn off capability. In a vertical conduction embodiment, the device has a six layer structure including a backside diffusion. One vertical conduction structure includes a single body region at the first surface of the device for conduction in both the forward and reverse directions. Another vertical conduction structure includes a two body regions at the first surface, one for controlling forward conduction and the other for controlling reverse conduction. The vertical conduction embodiments are preferably implemented in a cellular geometry, with a large number of symmetrical cells connected in parallel. The bidirectional thyristor of the present invention can also be provided in a lateral conduction structure for power IC applications.
    Type: Grant
    Filed: August 21, 1995
    Date of Patent: May 26, 1998
    Assignee: International Rectifier Corporation
    Inventor: Janardhanan S. Ajit