Abstract: One embodiment of a metal oxide semiconductor controlled thyristor in accordance with the present invention has a semiconductor wafer with opposing first and second surfaces. The wafer includes first through sixth sequential regions which are disposed one above the other. The first region includes the second surface of the wafer and each of the second through sixth regions has at least a portion which extends up to the first surface. The first, third, and sixth regions have a first type of conductivity and the second, fourth, and fifth regions have a second type of conductivity. A trench with a bottom and sidewalls extends from the first surface and passes through the fourth, fifth, and sixth regions and into the third region. A dielectric material coats the bottom and sidewalls of the trench and a conductive material fills the remainder of the trench.

Abstract: A bidirectional thyristor structure with a single MOS gate controlled turn off capability. In a vertical conduction embodiment, the device has a six layer structure including a backside diffusion. One vertical conduction structure includes a single body region at the first surface of the device for conduction in both the forward and reverse directions. Another vertical conduction structure includes a two body regions at the first surface, one for controlling forward conduction and the other for controlling reverse conduction. The vertical conduction embodiments are preferably implemented in a cellular geometry, with a large number of symmetrical cells connected in parallel. The bidirectional thyristor of the present invention can also be provided in a lateral conduction structure for power IC applications.

Abstract: A second region 3 is formed via a buffer layer 3a on a first region 2 formed with an anode electrode 1 on the rear and a third region 4 like a well is formed on the surface of the second region 3. A fourth region 15 like a well is formed at the center on the surface of the third region 4 and a fifth region 16 is formed along the well end. A sixth region 17 like a well is formed on the surface of the fourth region 15. Cathode electrodes 18 as metal electrodes of the first layer come in conductive contact with the fifth region 16 and the sixth region 17. A MOSFET 12 of n channel type for injecting majority carriers (electrons) is disposed from the first region 16 to the surfaces of the third region 4 and the second region 3, and a MOSFET 23 of p channel type is disposed from the sixth region 17 to the surfaces of the fourth region 16 and the third region 4. The second MOSFET 23 has a double diffusion type structure.

Abstract: A protection device against overloads that may occur on an interface between a telephone exchange and line switches connected to a subscriber's line, comprises a single protection circuit on the subscriber side of the line switches with respect to the interface. The overvoltage protection circuit ensures an overvoltage protection when the line switches are off, and an overcurrent protection when the switches are on. A controlled switch, disposed between each conductor and ground, is switched on in response to the detection of an overvoltage or overcurrent.

Abstract: A bidirectional thyristor structure with a single MOS gate controlled turn-on and turn-off capability. In a vertical conduction embodiment, the device has a six layer structure including a backside diffusion. One vertical conduction structure includes a single body region at the first surface of the device for conduction in both the forward and reverse directions. Another vertical conduction structure includes a two body regions at the first surface, one for controlling forward conduction and the other for controlling reverse conduction. The vertical conduction embodiments are preferably implemented in a cellular geometry, with a large number of symmetrical cells connected in parallel.

Abstract: A bidirectional thyristor structure with a single MOS gate controlled turn off capability. In a vertical conduction embodiment, the device has a six layer structure including a backside diffusion. One vertical conduction structure includes a single body region at the first surface of the device for conduction in both the forward and reverse directions. Another vertical conduction structure includes a two body regions at the first surface, one for controlling forward conduction and the other for controlling reverse conduction. The vertical conduction embodiments are preferably implemented in a cellular geometry, with a large number of symmetrical cells connected in parallel. The bidirectional thyristor of the present invention can also be provided in a lateral conduction structure for power IC applications.

Abstract: An object of the present invention is to provide a semiconductor device which is designed so as to increase a maximum controllable current and decrease hold current without degrading its characteristic and to provide a method of manufacturing such a semiconductor device. A transistor formation region 3 and a P diffusion region 15 are selectively formed through an insulating film 4 between gate electrodes 5 on an N.sup.- epitaxial layer 2. In a transistor formation region 3, an N.sup.+ diffusion region 12 is formed on a P diffusion region 11, a P diffusion region 13 is formed on the N.sup.+ diffusion region 12, and an N.sup.+ diffusion region 14 is selectively formed on a surface of the P diffusion region 13. Then, a cathode electrode 7 is formed on the P diffusion region 13, N.sup.+ diffusion region 14 and P diffusion region 15, and an anode electrode 8 is formed on a second major surface of the P.sup.+ substrate 1.

Abstract: A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.

Abstract: A static induction thyristor has a first semiconductor area having a high impurity concentration of a first conductivity type. A second semiconductor area having low impurity concentration is formed adjacent to the first semiconductor area. A third semiconductor area having a high impurity concentration of a second conductivity type which is the conductivity type opposite to the first conductivity type is formed on a part of a surface of the second semiconductor area so located as to form a fourth semiconductor area located within the third semiconductor area. A fifth semiconductor area having a high impurity concentration of the first conductivity type is formed on the part of the surface of the second semiconductor area in spaced relation to the forth semiconductor area.

Abstract: A set of three-dimensional structures and devices may be wired together to perform a wide variety of circuit functions such as SRAMs, DRAMs, ROMs and PLAs. Both N-Channel and P-Channel transistors can be made. The P-channel devices are fabricated conventionally in separate N-wells or, alteratively, they are constructed in a like manner to the array N-channel devices. N and P diffused wire can be electrically joined at polysilicon contacts.