Abstract: The present disclosure provides a latch-up test structure, including: a substrate of a first conductive type; a first well region of the first conductive type, located in the substrate of the first conductive type; a first doped region of the first conductive type, located in the first well region of the first conductive type; a first doped region of a second conductive type, located in the first well region of the first conductive type; and a second doped region of the first conductive type, a second doped region of the second conductive type, a third doped region of the first conductive type, and a third doped region of the second conductive type that are arranged at intervals in the substrate of the first conductive type.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.

Abstract: An integrated circuit includes an inductor over a substrate and a guard ring surrounding the inductor. The guard ring includes a first staggered line, a first metal line extending in a first direction and a second metal line extending in a second direction different from the first direction. The first staggered line has a first end coupled to the first metal line, and a second end coupled to the second metal line. The first staggered line includes a first set of vias, a first set of metal lines in a first metal layer and a second set of metal lines in a second metal layer different from the first metal layer. The first set of vias coupling the first set of metal lines with the second of second metal lines.

Abstract: Examples of the present disclosure provide power gating for stacked die structures. In some examples, a stacked die structure comprises a first die and a second die bonded to the first die. In some examples, a power gated power path is from a bonding interface between the dies through TSVs in the second die, a power gating device in the second die, and routing of metallization layers in the second die to the circuit region in the second die. In some examples, a power gated power path comprises a power gating device in a power gating region of the first die and is configured to interrupt a flow of current through the power gated power path to a circuit region in the second die.

Abstract: A crack detection chip includes a chip which includes an internal region and an external region surrounding the internal region, a guard ring formed inside the chip along an edge of the chip to define the internal region and the external region, an edge wiring disposed along an edge of the internal region in the form of a closed curve and a pad which is exposed on a surface of the chip and is connected to the edge wiring. The edge wiring is connected to a Time Domain Reflectometry (TDR) module which applies an incident wave to the edge wiring through the pad, and detects a reflected wave formed in the edge wiring to detect a position of a crack.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive line over the semiconductor substrate. The semiconductor device structure also includes a conductive via on the conductive line. The conductive via has an upper portion and a protruding portion. The protruding portion extends from a bottom of the upper portion towards the conductive line. The bottom of the upper portion is wider than a top of the upper portion. The semiconductor device structure further includes a dielectric layer over the semiconductor substrate, and the dielectric layer surrounds the conductive line and the conductive via.

Abstract: A rear-projection photodetection yarn clearing apparatus includes a light emitting diode and a detector arranged behind a to-be-detected yarn, and further includes a reflector arranged in front of the to-be-detected yarn. A front end face of the light emitting diode is flush with a photosurface of the detector, a light filter for capturing light rays having a waveband from 330 nm to 470 nm is also arranged in front of the light emitting diode and the detector, and a light-reflecting surface of the reflector is in parallel with the photosurface of the detector. The light emitting diode includes an ultraviolet light emitting diode, and the detector includes an ultraviolet enhanced silicon photodiode. The ultraviolet enhanced silicon photodiode is made from a high-resistivity N-type (111) silicon wafer having a resistivity of 3,000 ?·cm and a field oxide thickness of 1,000 nm.

Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing an adhesive layer to attach an upper electronic package to a lower die and/or utilizing metal pillars for electrically connecting the upper electronic package to a lower substrate, wherein the metal pillars have a smaller height above the lower substrate than the lower die.

Abstract: A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor substrate; an electrode pad provided on the main plane of the semiconductor substrate and connected to the semiconductor element; a guard ring surrounding the semiconductor element and the electrode pad, and provided on the main plane of the semiconductor substrate; and an insulating film covering all region of a semiconductor of the main plane of the semiconductor substrate exposed inside the guard ring, wherein the insulating film is made of a water impermeable material.

Abstract: The present technology relates to a solid state imaging device that enables a reduction in the manufacturing cost of the solid state imaging device, and an electronic apparatus. A first substrate including a pixel circuit having a pixel array unit and a second substrate including a first and a second signal processing circuit arranged side by side across a scribe area are stacked. The second substrate includes a first moisture-resistant ring surrounding at least part of a periphery of the first signal processing circuit, a second moisture-resistant ring surrounding at least part of a periphery of the second signal processing circuit, a third moisture-resistant ring surrounding at least part of a periphery of the second substrate in a layer different from the first and second moisture-resistant rings, and a barrier unit separating a first area between the first and second moisture-resistant rings and a second area.

Abstract: An integrated circuit comprises an inductor over a substrate and a guard ring surrounding the inductor. The guard ring comprises a plurality of first metal lines extending in a first direction and a plurality of second metal lines extending in a second direction. The second metal lines of the plurality of second metal lines are each coupled with at least one first metal line of the plurality of first metal lines. The guard ring also comprises a staggered line comprising a connected subset of at least one first metal line of the plurality of first metal lines and at least one second metal line of the plurality of second metal lines. The first metal lines of the plurality of first metal lines outside of the connected subset, the second metal lines of the plurality of second metal lines outside of the connected subset, and the staggered line surround the inductor.

Abstract: A semiconductor apparatus includes a semiconductor substrate, a semiconductor element, an edge termination region that surrounds the semiconductor element, a protective diode that has a first terminal and a second terminal, where the first terminal is positioned within the edge termination region and the second terminal is positioned outside the edge termination region, and a diffusion layer that has a floating potential, where the diffusion layer is provided in a gap portion between a region of the edge termination region that is aligned with the protective diode and the protective diode.

Abstract: A large scale integrated circuit chip includes a semiconductor circuit having a multilayered wiring structure, a metal guard ring surrounding the semiconductor circuit, and a plurality of external connection terminals, on a semiconductor circuit. The plurality of external connection terminals connect to an uppermost-layer wiring of the multilayered wiring structure and are exposed on a surface of the large scale integrated circuit chip. A predetermined external connection terminal conducts to a predetermined wiring through a conductive via within the guard ring and conducts to a conductive piece through another conductive via outside the guard ring. One side of the external connection terminal extending over the guard ring connects to the conductive piece, and the other side of the external connection terminal connects to the uppermost-layer wiring within the guard ring. Thus, a cutout part is not necessary in the guard ring.

Abstract: Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed.

Abstract: A semiconductor device includes a semiconductor substrate and a first semiconductor element. The semiconductor substrate has a circuit core area. The first semiconductor element is arranged on the semiconductor substrate and at least partially surrounds the periphery of the circuit core area. A layout area of the first semiconductor element is larger than a layout area of any of the semiconductor elements in the circuit core area.

Abstract: A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor substrate; an electrode pad provided on the main plane of the semiconductor substrate and connected to the semiconductor element; a guard ring surrounding the semiconductor element and the electrode pad, and provided on the main plane of the semiconductor substrate; and an insulating film covering all region of a semiconductor of the main plane of the semiconductor substrate exposed inside the guard ring, wherein the insulating film is made of a water impermeable material.

Abstract: Integrated circuits with components for protection from electrostatic discharge are provided. An integrated circuit includes a first common line and a second common line. A first electrostatic discharge line is in electrical communication with the first and second common lines. The first electrostatic discharge line includes a first diode and a first clamping device.

Abstract: The present disclosure relates an integrated circuit (IC) for an embedded flash memory device. In some embodiments, the IC includes a memory array region and a boundary region surrounding the memory array region disposed over a semiconductor substrate. A hard mask is disposed at the memory array region comprising a plurality of discrete portions. The hard mask is disposed under a control dielectric layer of the memory array region.

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; and a first doped region of type one, doped in the well of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

Abstract: In order to prevent the detachment of a film which is a constituent part of an interlayer-insulating film, and to prevent a decline in the device properties of a semiconductor device, a semiconductor device is provided with an interlayer-insulating film having, in this order, a carbon-containing silicon nitride (SiCN) film, a first silicon nitride film, and a silicon oxide film or a carbon-containing silicon oxide (SiOC) film.

Abstract: A method of manufacturing a photoelectric device, the method including: forming a first semiconductor layer on a semiconductor substrate through a first ion implantation; forming a second semiconductor layer having an inverted conductive type on a part of the first semiconductor layer through a second ion implantation; and performing thermal processing to restore lattice damage of the semiconductor substrate and activate a dopant into which ion implanted. According to one or more embodiments of the present invention, a photoelectric device having a reduction in the number of processes for manufacturing the photoelectric device and improved output characteristics is provided.

Abstract: A semiconductor device is provided, comprising a substrate; a first well having a first conductive type and extending down from a surface of the substrate; a diffusion region doped with impurity of the first conductive type and extending down from a surface of the first well; and a plurality of active devices formed within the diffusion region, and the active devices arranged separately from each other. The active devices are electrically isolated from each other by the diffusion region. The active device is self-isolated by a conductive guarding structure, and the semiconductor device comprising embodied STI-free active devices solves STI edge issues.

Abstract: A semiconductor device is manufactured by forming a lower structure on a substrate including first and second regions, simultaneously forming a first interconnection on the lower structure of the first region and a first portion of a second interconnection on the lower structure of the second region, forming a first interlayer insulating layer on the first interconnection and on the first portion of the second interconnection, forming a trench exposing a top surface of the first portion of the second interconnection in the first interlayer insulating layer, and forming a second portion of the second interconnection in the trench. Related structures are also disclosed.

Abstract: A semiconductor structure is arranged on an integrated circuit, the integrated circuit includes a seal ring arranged at outer periphery of the integrated circuit, a metal ring arranged at an inner side of the seal ring and a power bus arranged at a side of the metal ring. The semiconductor structure includes a first P type electrode area, a second P type electrode area and a first N type electrode area. The first P type electrode area is formed at a position on a P well corresponding to the seal ring, and coupled to the seal ring. The second P type electrode area is formed at a position on the P well corresponding to the metal ring, and coupled to the metal ring. The first N type electrode area is formed at a position corresponding to the power bus, and coupled to the power bus.

Abstract: Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed.

Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

Abstract: The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent to the package paddle; depositing a lead conductive cap on the lead, the lead conductive cap includes a nickel layer having a thickness between 2.55 ?m to 8.00 ?m deposited on the lead, a palladium layer deposited on the nickel layer, and a gold layer deposited on the palladium layer; mounting an integrated circuit over the package paddle; attaching an electrical connector between the lead conductive cap and the integrated circuit; and forming an encapsulation over the integrated circuit, a portion of the lead, and a portion of the package paddle.

Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

Abstract: Methods and apparatus for ESD structures. A semiconductor device includes a first active area containing an ESD cell coupled to a first terminal and disposed in a well; a second active area in the semiconductor substrate, the second active area comprising a first diffusion of the first conductivity type for making a bulk contact to the well; and a third active area in the semiconductor substrate, separated from the first and second active areas by another isolation region, a portion of the third active area comprising an implant diffusion of the first conductivity type within a first diffusion of the second conductivity type and adjacent a boundary with the well of the first conductivity type; wherein the third active area comprises a diode coupled to the terminal and reverse biased with respect to the well of the first conductivity type.

Abstract: In a first embodiment, an ultra-fast breakover diode has a turn on time TON that is less than 0.3 microseconds, where the forward breakover voltage is greater than +400 volts and varies less than one percent per ten degrees Celsius change. In a second embodiment, a breakover diode has a reverse breakdown voltage that is greater, in absolute magnitude, than the forward breakover voltage, where the forward breakover voltage is greater than +400 volts. In a third embodiment, a string of series-connected breakover diode dice is provided, along with a resistor string, in a packaged circuit. The packaged circuit acts like a single breakover diode having a large forward breakover voltage and a comparably large reverse breakdown voltage, even though the packaged circuit includes no discrete high voltage reverse breakdown diode. The packaged circuit is usable to supply a triggering current to a thyristor in a voltage protection circuit.

Abstract: A semiconductor device includes an active section for a main current flow and a breakdown withstanding section for breakdown voltage. An external peripheral portion surrounds the active section on one major surface of an n-type semiconductor substrate. The breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring. The ring-shaped semiconductor protrusion has a p-type region therein, is sandwiched between a plurality of concavities deeper than the p-type region, and has an electrically conductive film across an insulator film on the surface thereof. Because of this, it is possible to manufacture at low cost a breakdown withstanding structure with which a high breakdown voltage is obtained in a narrow width, wherein there is little drop in breakdown voltage, even when there are variations in a patterning process of a field oxide film.

Abstract: Methods and apparatus for flip chip substrates with guard rings. An embodiment comprises a substrate core with a die attach region for attaching an integrated circuit die; at least one dielectric layer overlying a die side surface of the substrate core; and at least one guard ring formed adjacent a corner of the substrate core, the at least one guard ring comprising: a first trace overlying the dielectric layer having rectangular portions extending in two directions from the corner of the substrate core and in parallel to the edges of the substrate core; a second trace underlying the dielectric layer; and at least one via extending through the dielectric layer and coupling the first and second traces; wherein the first trace, the at least one via, and the second trace form a vertical via stack. Methods for forming the flip chip substrates with the guard rings are disclosed.

Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

Abstract: A method for forming an integrated circuit. The method includes forming a first guard ring around at least one transistor over a substrate, the first guard ring having a first type dopant. The method further includes forming a second guard ring around the first guard ring, the second guard ring having a second type dopant. The method includes forming a first doped region adjacent to the first guard ring, the first doped region having the second type dopant. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having the first type dopant, wherein the first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

Abstract: A semiconductor device is disclosed wherein a peripheral region with a high breakdown voltage and high robustness against induced surface charge is manufactured using a process with high mass productivity. The device has n-type drift region and p-type partition region of layer-shape deposited in a vertical direction to one main surface of n-type semiconductor substrate with high impurity concentration form as drift layer, alternately adjacent parallel pn layers in a direction along one main surface. Active region through which current flows and peripheral region enclosing the active region include parallel pn layers.

Abstract: In a method for producing an electronic component, a substrate is doped by introducing doping atoms. In the doped substrate, at least one connection region of the electronic component is formed by doping with doping atoms. Furthermore, at least one additional doped region is formed at least below the at least one connection region by doping with doping atoms. Furthermore, at least one well region is formed in the substrate by doping with doping atoms in such a way that the well region doping is blocked at least below the at least one additional doped region.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: A mesa-type bidirectional vertical power component, including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; first regions of the first conductivity type in each of the layers of the second conductivity type; and, at the periphery of each of its surfaces, two successive grooves, the internal groove crossing the layers of the second conductivity type, second doped regions of the first conductivity type being formed under the surface of the external grooves and having the same doping profile as the first regions.

Abstract: This invention comprises photodiodes, optionally organized in the form of an array, including p+ deep diffused regions or p+ and n+ deep diffused regions. More specifically, the invention permits one to fabricate thin 4 inch and 6 inch wafer using the physical support provided by a n+ deep diffused layer and/or p+ deep diffused layer. Consequently, the present invention delivers high device performances, such as low crosstalk, low radiation damage, high speed, low leakage dark current, and high speed, using a thin active layer.

Abstract: A silicon photomultiplier maintains the photon detection efficiency high while increasing a dynamic range, by reducing the degradation of an effective fill factor that follows the increase of cell number density intended for a dynamic range enhancement.

Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.

Abstract: An electro-static discharge protection circuit includes: a PNPN junction, a P-type side of the PNPN junction being coupled to a terminal, an N-type side of the PNPN junction being coupled to ground; and a P-type metal oxide semiconductor transistor, a source and a gate of the P-type metal oxide semiconductor transistor being coupled to an N-type side of a PN junction whose P-type side coupled to the ground, and a drain of the P-type metal oxide semiconductor transistor being coupled to the terminal.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: A modified MOSFET structure comprises an integrated field effect rectifier connected between the source and drain of the MOSFET to shunt current during switching of the MOSFET. The integrated FER provides faster switching of the MOSFET due to the absence of injected carriers during switching while also decreasing the level of EMI relative to discrete solutions. The integrated structure of the MOSFET and FER can be fabricated using N-, multi-epitaxial and supertrench technologies, including 0.25 ?m technology. Self-aligned processing can be used.

Abstract: A guard ring system is disclosed for protecting an integrated circuit comprising. It has a first guard ring area formed by a well in the substrate, a capacitor area formed within the first guard ring area which further includes two well contacts formed into the well and biased by a first supply voltage, and a dielectric layer placed between the two contacts on the well with its first side in contact with the well. A second supply voltage complementary to the first supply voltage is applied to a second side of the dielectric layer so that a voltage difference across the dielectric layer provides a local capacitance embedded therein.

Abstract: An integrated circuit device includes a substrate having adjacent first and second regions, and a device isolation structure in the substrate between the first and second regions. The first and second regions of the substrate may respectively include transistors configured to be driven at different operational voltages, and the device isolation structure may electrically separates the transistors of the first region from the transistors of the second region. The device isolation structure includes outer portions immediately adjacent to the first and second regions and an inner portion therebetween. The outer portions of the device isolation structure comprise a material having an etching selectivity with respect to that of the inner portion. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor wafer has a semiconductor substrate and films on the substrate. The substrate and/or the films have at least one etch line creating a discontinuous surface that reduces residual stress in the wafer. Reducing residual stress in the semiconductor wafer reduces warpage of the wafer when the wafer is thin. Additionally, isolation plugs may be used to fill a portion of the etch lines to prevent shorting of the layers.