Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.

Abstract: A semiconductor apparatus that includes a semiconductor substrate having a first main surface and a second main surface, a first electrode opposing the first main surface of the semiconductor substrate, a dielectric layer between the semiconductor substrate and the first electrode, a second electrode opposing the second main surface of the semiconductor substrate, and a resistance control layer between the semiconductor substrate and the second electrode. The resistance control layer includes a first region having a first electrical resistivity and electrically connecting the semiconductor substrate and the second electrode, and a second region having a second electrical resistivity higher than the first electrical resistivity of the first region and adjacent to the first region.

Abstract: A method for fabricating an (Al,Ga,In,B)N or III-nitride semiconductor device, including performing a growth of III-nitride or (Al,Ga,In,B)N material including a p-n junction with an active region and using metal-organic chemical vapor deposition (MOCVD) or chemical vapor deposition; and performing a subsequent regrowth of n-type (Al,Ga,In,B)N or III-nitride material using MOCVD or chemical vapor deposition while utilizing a pulsed delta n-type doping scheme to realize an abrupt, smoother surface of the n-type material and a higher carrier concentration in the n-type material. In another example, the method comprises forming a mesa having a top surface; and activating magnesium in the p-type GaN of the (Al,Ga,In,B)N material through openings in the top surface that expose the p-type GaN's surface. The openings are formed before or after the subsequent regrowth of the tunnel junction.

Abstract: Radiation detectors based on high electron mobility transistors (HEMTs) are provided. Methods for detecting ultraviolet radiation using the HEMTs are also provided. The transistors are constructed from an intrinsic high bandgap semiconductor material with a built-in polarization field sandwiched between graphene and a two-dimensional electron gas (2DEG).

Abstract: Provided is method of manufacturing a conductive film. The method includes forming a conductive film including a plurality of flakes on a substrate, wherein the conductive film is a semiconductor or a conductor, and forming a passivation region selectively on a boundary between the flakes adjacent to each other. The passivation region includes a metal compound selected from the group consisting of metal chalcogenide and transition metal chalcogenide. The forming of the passivation region includes providing a solution containing a first precursor including a cation of the metal compound and a second precursor including an anion of the metal compound on the conductive film. pH of the solution is between 7.0 and 10.0.

Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

Abstract: Described is an arrangement for registering light, comprising: a MOS-transistor structure having a first source/drain region, a second source/drain region, and a bulk region at least partially between the first source/drain region and the second source/drain region, wherein the bulk region has a doping type different from another doping type of the first and the second source/drain regions, wherein in the bulk region charge carriers are generated in dependence of light impinging on the bulk region, wherein the generated charge carriers control a current flowing from the first source/drain region to the second source/drain region via at least a portion of the bulk region.

Abstract: The present invention provides a bipolar transistor, a method for forming the bipolar transistor, a method for turning on the bipolar transistor, and a band-gap reference circuit, virtual ground reference circuit and double band-gap reference circuit with the bipolar transistor. The bipolar transistor includes: a Silicon-On-Insulator wafer; a base area, an emitter area and a collector area; a base area gate dielectric layer on a top silicon layer and atop the base area; a base area control-gate on the base area gate dielectric layer; an emitter electrode connected to the emitter area via a first contact; a collector electrode connected to the collector area via a second contact; and a base area control-gate electrode connected to the base area control-gate via a third contact.

Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode. The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.

Abstract: A semiconductor device includes: a semiconductor substrate; a first insulating film on a surface of the semiconductor substrate; a temperature sensing diode on the first insulating film; a trench extending inward from the surface of the semiconductor substrate; and a trench electrode embedded in the trench via a second insulating film and connected to the temperature sensing diode.

Abstract: An A-NPC circuit is configured so that the intermediate potential of two connected IGBTs is clamped by a bidirectional switch including two RB-IGBTs. Control is applied to the turn-on di/dt of the IGBTs during the reverse recovery of the RB-IGBTs. The carrier life time of an n? drift region in each RB-IGBT constituting the bidirectional switch is comparatively longer than that in a typical NPT structure device. A low life time region is also provided in the interface between the n? drift region and a p collector region, and extends between the n? drift region and the p collector region. Thus, it is possible to provide a low-loss semiconductor device, a method for manufacturing the semiconductor device and a method for controlling the semiconductor device, in which the reverse recovery loss is reduced while the reverse recovery current peak and the jump voltage peak during reverse recovery are suppressed.

Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.

Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Abstract: A semiconductor component has a first and a second contact-making region, and a semiconductor volume arranged between the first and the second contact-making region. Within the semiconductor volume, it is possible to generate a current flow that runs from the first contact-making region to the second contact-making region, or vice versa. The semiconductor volume and/or the contact-making regions are configured in such a way that the local flow cross-section of a locally elevated current flow, which is caused by current splitting, is enlarged at least in partial regions of the semiconductor volume.

Abstract: The invention relates to a high-speed diode comprising a semiconductor body (1), in which a heavily n-doped zone (8), a weakly n-doped zone (7) and a weakly p-doped zone (6) are arranged successively in a vertical direction (v), between which a pn load junction (4) is formed. A number of heavily p-doped islands (51-57) spaced apart from one another are arranged in the weakly p-doped zone (6). In this case, it is provided that the cross-sectional area density of the heavily p-doped islands (51-57) is smaller in a first area region (100) near to the edge than in a second area region (200) remote from the edge.

Abstract: An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.

Abstract: An object of the present invention is to provide a semiconductor device capable of radiating electron-beams only to a desired region without forming a layer for restricting the radiating rays. A source electrode 22 made of aluminum prevents the generation of bremsstrahlung even when the electron-beams are radiated to the source electrode in a exposed condition. Also, the source electrode having an opening 25 at above of a crystal defect region 11 is used as a mask when the electron-beams are radiated thereto. That is the source electrode made of aluminum can be used both as a wiring and a mask for the radiating rays.

Abstract: A thyristor-based memory device may comprise two base regions of opposite type conductivity formed between a cathode-emitter region and an anode-emitter region. A junction defined between the p-base region and the cathode-emitter region of the thyristor may be “treated” with a high ionization energy acceptor such as indium in combination with carbon as an activation assist species. These two implants may form complexes that may extend across the junction region.

Abstract: Semiconductor devices having recombination centers comprised of well-positioned heavy metals. At least one lattice defect region within the semiconductor device is first created using particle beam implantation. Use of particle beam implantation positions the lattice defect region(s) with high accuracy in the semiconductor device. A heavy metal implantation treatment of the device is applied. The lattice defects created by the particle beam implantation act as gettering sites for the heavy metal implantation. Thus, after the creation of lattice defects and heavy metal diffusion, the heavy metal atoms are concentrated in the well-positioned lattice defect region(s).

Abstract: A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N? doped, P? doped, and P+ doped semiconductor layers, the P? and P+ doped layers having a combined thickness of about 5 ?m to about 12 ?m. Recombination centers comprising noble metal impurities are disposed substantially in the N? and P? doped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an N? doped epitaxial layer on an N+ doped substrate, forming a P? doped layer in the N? doped epitaxial layer, forming a P+ doped layer in the P? doped layer, and forming in the P? and N? doped layers recombination centers comprising noble metal impurities. The P+ and P? doped layers have a combined thickness of about 5 ?m to about 12 ?m.

Abstract: A method for producing a semiconductor component has the following step: the front side (101) of the semiconductor body (100) is irradiated with high-energy particles using the terminal electrode (40) as a mask, in order to produce recombination centres (80A, 80B) in the semiconductor body (100) for the recombination of the first and second conduction type of charge carriers.

Abstract: A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N?-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.

Abstract: A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N?-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.

Abstract: A rescue structure to repair an open wire includes a first metal layer having at least a rescue line, an isolation layer formed on the first metal layer, and a second metal layer formed on the isolation layer. The second metal layer has at least a signal line crossing the rescue line to form an enlarged intersection node. The intersection node is particularly arranged far from the side where the rescue line is used for signal transmission.

Abstract: An object of the present invention is to provide a semiconductor device capable of radiating electron-beams only to a desired region without forming a layer for restricting the radiating rays. A source electrode 22 made of aluminum prevents the generation of bremsstrahlung even when the electron-beams are radiated to the source electrode in a exposed condition. Also, the source electrode having an opening 25 at above of a crystal defect region 11 is used as a mask when the electron-beams are radiated thereto. That is the source electrode made of aluminum can be used both as a wiring and a mask for the radiating rays.

Abstract: An electronic power device comprising a single crystal silicon segment being characterized in that the segment comprises a non-uniform distribution of minority carrier recombination centers, the minority carrier recombination centers comprising a substitutional metal, with the concentration of the centers in a bulk layer being greater than the concentration in a surface layer. The centers have a concentration profile in which the peak density of the centers is at or near the central plane with the concentration generally decreasing from the position of peak density in the direction of the front surface of the segment and generally decreasing from the position of peak density in the direction of the back surface of the segment.

Abstract: A switching semiconductor device includes a first compound layer formed on a single crystal substrate which includes silicon carbide or sapphire, and including a general formula InxGa1-xN, where 0?x?1; a second compound layer formed on the first compound layer, and including a general formula InyALzGa1-y-zN, where 0?y?1 and 0<z?1; and a gate electrode formed on the second compound layer. The gate electrode is electrically connected to a resistance element formed on a first interlayer insulating film that covers the gate electrode, through a metal wiring formed on a second interlayer insulating film that covers the first interlayer insulating film.

Abstract: A novel architecture of high-power four-quadrant hybrid power modules based on high-current trench gate IGBTs and arrays of low-current wide-bandgap diodes is conceived. The distributed physical layout of high power density wide-bandgap devices improves the cooling inside a fully-sealed module case, thus avoiding excessive internal heat flux build up and high PN junction temperature, and benefiting the converter's reliability and efficiency. The design of multiple-in-one hybrid integrated AC-switch module at high power ratings is enabled by using hybrid AC switch cells and aluminum nitride substrate structure.

Abstract: A semiconductor device that helps to prevent the occurrence of current localization in the vicinity of an electrode edge and improves the reverse-recovery withstanding capability. The semiconductor device according to the invention includes a first carrier lifetime region, in which the carrier lifetime is short, formed in such a configuration that the first carrier lifetime region extends across the edge area of an anode electrode projection, which projects the anode electrode vertically into a semiconductor substrate. The first carrier lifetime region also includes a vertical boundary area spreading nearly vertically between a heavily doped p-type anode layer and a lightly doped semiconductor layer. The first carrier lifetime region of the invention is formed by irradiating with a particle beam, such as a He2+ ion beam or a proton beam.

Abstract: A process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a segment having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the segment. Platinum atoms are then in-diffused into the silicon matrix such that the resulting platinum concentration profile is substantially related to the concentration profile of the crystal lattice vacancies.

Abstract: The present invention provides a semiconductor device wherein the turning-off time thereof can be reduced substantially and, at the same time, the turned-on resistance thereof can also be prevented effectively from increasing as well. Lattice defects are distributed at a high concentration in a defect region an area in close proximity to the boundary surface between an n drift region and a p+ substrate. The half-value width of the distribution is set at a value which is large enough for the defect region to include a non-depletion region in the n drift region. However, the defect region is not spread to cover a diffusion layer. In this way, the turning-off time of the semiconductor device can be reduced considerably without being accompanied by an increase in turned-on resistance thereof. In addition, by employing an absorber with an uneven surface, the distribution of lattice defects can be obtained by carrying out radiation of ions at only one time.

Abstract: A preferably asymetrical thyristor (1) with at least one driver stage (20) for amplifying a control current (I) fed into the cathodal base (16) of the thyristor, in which, in the driver stage, the transistor gain factors &agr;npn and &agr;pnp are in each case greater than, preferably, in the thyristor and anode short circuits of the thyristor (174) have a smaller electrical conductivity in the driver stage than in the thyristor.

Abstract: An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.

Abstract: According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.

Abstract: In a bonded semiconductor member, microgaps are formed on a substrate side of a bonding interface to thereby constitute a gettering site, and heavy metal elements contaminated in the substrate are captured by the microgaps. The bonded semiconductor member is manufactured by interposing the microgaps between two substrates.

Abstract: The present invention provides, in a TFT, a channel region facing a gate electrode through a gate insulating film, a source electrode connected to the channel region and a drain region connected to the channel region on the side opposite the source region that are formed in a polycrystal semiconductor film that was patterned in island forms. In the channel region, a recombination center is formed for capturing a small number of carriers (holes) by impurities, such as inert-gas, metals, Group III elements, Group IV elements and Group V elements, introduced to a predetermined region in this channel region, or by defects generated due to the introduction of these impurities. The present invention thus provides an arrangement restraining bipolar transistor type behavior to stabilize saturation current and to provide a TFT that can improve reliability.

Abstract: To suppress spike voltage generated at turn-off operation, a semiconductor device according to the invention comprises a first region composed of a first conductor, a second region composed of a second conductor formed on top of the first region, a third region composed of the first conductor formed on top of the second region and a fourth region composed of the second conductor formed on top of the third region. The second region is comprised of a depletion-layer forming auxiliary layer having a short lifetime and formed in the vicinity of the third region, a tail-current suppression layer having a shorter lifetime than that of the depletion-layer forming auxiliary layer and formed in the vicinity of the first region and a depletion-layer forming suppression layer having a longer lifetime than that of the depletion-layer forming auxiliary layer and formed between the depletion-layer forming auxiliary layer and the tail-current suppression layer.

Abstract: A vehicle wheel lift includes a base, a substantially upright member, a linear actuator, and a lift arm. The linear actuator is coupled to the upright member, which is attached to and extends from the base. The lift arm is pivotally coupled to the upright member proximate a first end of the lift arm and above the linear actuator. The lift arm includes a wheel cradle shaped for receiving a vehicle wheel proximate a second end of the lift arm that is opposite the first end of the lift arm and is connected to a ram of the linear actuator between the first and second ends of the lift arm.

Abstract: A semiconductor rectifier includes a substrate of a first conductivity type; a current path layer of the first conductivity type formed near the surface of the substrate; a current block layer of a second conductivity type laterally enclosing the current path layer and extending to a depth deeper than the current path layer; and first and second metal layers formed respectively contacting upper and lower surfaces of the substrate. The current path layer has an impurity concentration higher than that of the substrate, and the current block layer has an impurity concentration higher than that of the current path layer. The current path layer is small enough for the portion below the current path layer to be completely blocked by the depletion region formed around the current block layer when a reverse bias or no is applied to the rectifier.

Abstract: The thyristor is based on a semiconductor body with an anode-side base zone of the first conductivity type and one or more cathode-side base zones of the opposite, second conductivity type. Anode-side and cathode-side emitter zones are provided, and at least one region in the cathode-side base zone whose geometry gives it a reduced breakdown voltage as compared with the remaining regions in the cathode-side base zone and the edge of the semiconductor body. At the anode, below the region of reduced breakdown voltage, the thyristor has at least one recombination zone in which the free charge carriers have a reduced lifetime.

Abstract: One embodiment of a semiconductor device includes a laterally extending semiconductor base, a buffer adjacent the base and having a first conductivity type dopant, and a laterally extending emitter adjacent the buffer and opposite the base and having a second conductivity type dopant. The buffer is relatively thin and has a first conductivity type dopant concentration greater than a second conductivity type dopant concentration in adjacent emitter portions to provide a negative temperature coefficient for current gain and a positive temperature coefficient for forward voltage for the device. The buffer may be silicon or germanium. A low temperature bonded interface may be between the emitter and the buffer or the buffer and the base. Another embodiment of a device may include a laterally extending localized lifetime killing portion between oppositely doped first and second laterally extending portions.

Abstract: An IGBT is optimized for ZVS operation, thereby significantly reducing switching losses during ZVS operation. In effect, the IGBT is optimized to operate as a MOSFET with a very small bipolar transistor component. Switching losses are reduced by reducing the number of minority carriers injected into the device during conduction. Additionally, this ZVS IGBT structure allows for a small increase in stored charge as the operating temperature is increased, allowing the device to operate at higher temperatures with relatively low switching losses.

Abstract: A thyris a thyristor is provided in which a lifetime of a minority carrier is controlled to improve the trade-off relationship between an ON-state voltage and a turn-off time and attain a high frequency and a low loss. Shielding members formed of metal plates are provided respectively in spaces above a plane on which a cathode electrode is provided and a plane on which an anode electrode is provided.

Abstract: A semiconductor device includes a plurality of defect layers separated from one another in the semiconductor layer. A distance separating any adjacent ones of the defect layers is kept such that they are prevented from contacting each other and those regions having effect of shortening a carrier lifetime overlap each other.

Abstract: In a semiconductor device, such as a diode and thyristor, having at least one pn junction between a pair of main surfaces, a first main electrode formed on the surface of one of the main surfaces and a second main electrode formed on the surface of the other one of the main surfaces, a semiconductor lattice defect is formed such that its lattice defect density increases gradually in the direction from the first main electrode to the second main electrode. Since the distribution of the carrier density in the conduction state can be flattened, the reverse recovery charge can be reduced substantially without causing the ON-state voltage to increase.

Abstract: A method of depositing high quality diamond films and a light emitting device are described. The deposition is carried out in a reaction chamber. After disposing a substrate to be coated in the chamber, a carbon compound gas including a C--OH bond is introduced together with hydrogen thereinto. Then, deposition of diamond takes place in a magnetic field by inputting microwave energy. The present invention is particularly characterized in that the volume ratio of the carbon compound to hydrogen introduced into the reaction chamber is 0.4 to 2; the pressure in said reaction chamber is 0.01 to 3 Torr; the temperature of the substrate is kept between 200.degree. to 1000.degree. C. during deposition; and the input energy of the microwave is no lower than 2 KW. By this method, uniform and high quality diamond films can be formed.

Abstract: A static induction thyristor has a first semiconductor area having a high impurity concentration of a first conductivity type. A second semiconductor area having low impurity concentration is formed adjacent to the first semiconductor area. A third semiconductor area having a high impurity concentration of a second conductivity type which is the conductivity type opposite to the first conductivity type is formed on a part of a surface of the second semiconductor area so located as to form a fourth semiconductor area located within the third semiconductor area. A fifth semiconductor area having a high impurity concentration of the first conductivity type is formed on the part of the surface of the second semiconductor area in spaced relation to the forth semiconductor area.

Abstract: There is provided an optical image processor for forming a charge image according to a first optical image by photoelectric effect when illuminated with an electro-magnetic radiation beam for writing carrying the first optical image and forming, in accordance with the charge image, a second optical image correlating with the first optical image by light-modulation when illuminated with an electro-magnetic radiation beam for reading, in the presence of an electric field. The processor comprises a plurality of photoconductive segments two-dimensionally arranged with a space among the photoconductive segments for forming the charge image when illuminated with the electro-magnetic radiation beam for writing and a high resistive member provided in the space for preventing transfer of electric charges of the formed charge image among the photoconductive segments.