Abstract: A dynamically-operating restoration circuit (106) is used to apply a voltage or current restore pulse signal to thyristor-based memory cells (108) and therein restore data in the cell using the internal positive feedback loop of the thyristor (110). In one example implementation, the internal positive feedback loop in the thyristor (110) is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.

Abstract: A surface region of a first base layer is formed with a second base layer. Trenches are formed over a range from the surface of the second base layer to the first base layer. The second base layer is divided into base layers. Each of first trenches is formed with a trench gate electrode. An emitter layer is formed in a surface region of the base layer intermittently selected from base layers positioned between first trenches, and contacts with the trench. Dummy trenches are formed over a range from the surface of the base region where the emitter layer is not formed to the first base layer at a position near to each of trenches. A diffusion region is formed in the first base layer to contact with the side portion of dummy trenches formed at the bottom of each trench and a position near thereto.

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is realized. Break down voltage of a power device is controlled by a thickness of a drift layer. A positive base layer, a negative emitter layer and a positive base contact layer are formed on a side of the other surface of the semiconductor substrate. A negative low resistant layer reduces a junction FET effect. An emitter electrode comes into contact with the negative emitter layer and the positive base contact layer. A collector electrode comes into contact with the positive collector layer. A gate electrode is formed on a gate insulating film above a channel region on a surface portion of the positive base layer.

Abstract: A semiconductor device is formed having a thyristor, a pass device and a conductive shunt that electrically connects an emitter region of the thyristor with a node near an upper surface of the substrate. In one example embodiment of the present invention, the conductive shunt is formed in a trench in a substrate and extending from an upper surface of the substrate to an emitter region of a vertical thyristor, with the emitter region being in the substrate and below the upper surface. In one implementation, the thyristor includes a thyristor body and a control port, with an N+ emitter region of the thyristor body being in the substrate and below and upper surface thereof. A pass device is formed adjacent to the thyristor, and the conductive shunt is formed in a trench extending from the N+ emitter region to a source/drain region of the pass device.

Abstract: A semiconductor device having a thyristor-based memory device exhibits improved stability under adverse operating conditions related to temperature, noise, electrical disturbances and light. In one particular example embodiment of the present invention, a semiconductor device includes a thyristor-based memory device that uses a shunt that effects a leakage current in the thyristor. The thyristor includes a capacitively-coupled control port and anode and cathode end portions. Each of the end portions has an emitter region and an adjacent base region. In one implementation, the current shunt is located between the emitter and base region of one of the end portions of the thyristor and is configured and arranged to shunt low-level current therebetween.

Abstract: A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is realized. Break down voltage of a power device is controlled by a thickness of a drift layer. A positive base layer, a negative emitter layer and a positive base contact layer are formed on a side of the other surface of the semiconductor substrate. A negative low resistant layer reduces a junction FET effect. An emitter electrode comes into contact with the negative emitter layer and the positive base contact layer. A collector electrode comes into contact with the positive collector layer. A gate electrode is formed on a gate insulating film above a channel region on a surface portion of the positive base layer.

Abstract: A power MOSFET includes an n−-drain layer, a drain contact layer disposed on a first side of the drain layer, a p-type base layer disposed on a second side of the drain layer, and an n-source layer disposed on the base layer. A gate electrode faces, through a gate insulating film, a channel region, which is part of the base layer between the drain and source layers. Source and drain electrodes are electrically connected to the source and drain contact layers, respectively. A plurality of hetero regions having a dielectric constant higher than that of the drain layer is disposed in the drain layer between the source and drain electrodes.

Abstract: To suppress spike voltage generated at turn-off operation, a semiconductor device according to the invention comprises a first region composed of a first conductor, a second region composed of a second conductor formed on top of the first region, a third region composed of the first conductor formed on top of the second region and a fourth region composed of the second conductor formed on top of the third region. The second region is comprised of a depletion-layer forming auxiliary layer having a short lifetime and formed in the vicinity of the third region, a tail-current suppression layer having a shorter lifetime than that of the depletion-layer forming auxiliary layer and formed in the vicinity of the first region and a depletion-layer forming suppression layer having a longer lifetime than that of the depletion-layer forming auxiliary layer and formed between the depletion-layer forming auxiliary layer and the tail-current suppression layer.

Abstract: A Silicon Carbide (SiC) Gate Turn-Off (GTO) thyristor is formed of a substrate having at least three epi-layers provided thereon as first, second and third doped regions, respectively, and the substrate being a fourth doped region, wherein the at least four doped regions alternate between a p-type doping and an n-type doping, with the regions being at least partially overlaid. An anode is arranged on the first region, and a base is arranged on the second region. A controlling gate is arranged on the third region, and a cathode is arranged on the fourth region. A current divider divides the load current between the anode and the base. This reduces the voltage drop of a portion of the load current passing through the thyristor, allowing for the switching of higher current densities than in prior art thyristors, faster switching speeds and reduced junction temperatures.

Abstract: A semiconductor device having a thyristor-based memory device exhibits improved stability under adverse operating conditions related to temperature, noise, electrical disturbances and light. In one particular example embodiment of the present invention, a semiconductor device includes a thyristor-based memory device that uses a shunt between a base and emitter region in a thyristor that effects a leakage current in the thyristor. The thyristor includes a capacitively coupled control port and anode and cathode end portions. Each of the end portions has an emitter region and an adjacent base region, and the current shunt is located between the emitter and base region of one of the end portions of the thyristor.

Abstract: A semiconductor component including a housing for a semiconductor substrate, an anode, a cathode, an annular gate electrode flange, which laterally protrudes from the housing and concentrically surrounds the housing, and an annular auxiliary cathode flange, which protrudes from the housing and makes contact with the cathode.

Abstract: A field emission type cold cathode device comprises a substrate, and a metal plating layer formed on the substrate, the metal plating layer contains at least one carbon structure selected from a group of fullerenes and carbon nanotubes, the carbon structure is stuck out from the metal plating layer and a part of the carbon structure is buried in the metal plating layer.

Abstract: An insulated gate thyristor is provided which includes: a first-conductivity-type base layer, first and second-conductivity-type base regions formed in the base layer, a first-conductivity-type source region formed in the first base region, a first-conductivity-type emitter region formed in the second base region, and a gate electrode layer formed on a gate insulating film over the first base region, first-conductivity-type base layer, and second base region, which are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region.

Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

Abstract: The semiconductor component has a small forward voltage and a high blocking ability. At least one drift path suitable for taking up voltage is formed in a semiconductor body between two electrodes that are arranged at a distance from one another. At least one semi-insulating layer is provided parallel to the drift path. The semi-insulating layer leads to a linear rise in the potential between the two electrodes when a reverse voltage is applied.

Abstract: The MOS gate thyristor of the present invention has a p+ type anode layer (first semiconductor layer), an n− type base region (second semiconductor layer) with the function of acting as a drift layer, a p− type base region (third semiconductor layer), and an n+ type impurity diffusion layer (fourth semiconductor layer) with the function of acting as a source region. On the surface of the base region, an n+ type floating emitter region (fifth semiconductor layer) is formed, while a first channel region (sixth semiconductor layer) is formed between the impurity diffusion layer and the floating emitter region. At the lower ends of the fourth semiconductor layer and the first channel region an insulation layer is formed. The insulation layer acts to suppress the operation of a parasitic thyristor to ensure a reliable turn-off operation of the transistor.

Abstract: A latch-up controllable insulated gate bipolar transistor is formed with a thyristor structure, which has a first region of a first conductivity type, a second region of a second conductivity type formed on the first region, a third region of the first conductivity type formed on the second region, and a fourth region of the second conductivity type contacting the third region and forming a P-N junction therewith. The first and third regions contact a first and second electrode regions respectively. A first field effect transistor means for controlling conduction between the fourth region and the second region in response to an actuation bias; and a second field effect transistor means between the fourth region and the second electrode region for turning the thyristor off in response to a cutoff bias.

Abstract: A monolithic integrated device includes a protection structure and is formed in a semiconductor material substrate having a first conductivity type, which device includes at least a first epitaxial layer formed on the substrate. The integrated device further includes a bipolar first transistor formed of a base region having a second conductivity type and including a first buried region formed in the first epitaxial layer, and having a first diffused region which extends from the first buried region to contact a top surface of the integrated device through a surface contact region with a high concentration of dopant material. The first transistor also has an emitter region with the first conductivity type, embedded in the base region, and including a second buried region formed on the first buried region and a second diffused region, with a high concentration of dopant material, which extends from the second buried region to contact the top surface of the integrated device.

Abstract: In an emitter-switched thyristor with a main thyristor (TH) composed of a p+ anode emitter (1), a drift zone (3') of opposite conductivity type, a zone (4) which has in the switched-off state a blocking zone with respect to zone (3) and an emitter zone (5) at the cathode side, again with an opposite conductivity type, so that a p+n-pn+ zone sequence results, a transistor structure (T) composed of the first three zones of alternating conductivity is provided in parallel thereto with an emitter (1), base (3) and a collector (8). This structure contains a NMOSFET (M1) for directly driving the cathode emitters (5) through the cathode connection (KA). The source of this transistor is contacted by the cathode, as well as the collector zone (8) which forms the channel zone of the MOSFET at the surface of the semiconductor. The corresponding drain zone is connected to the n+ cathode emitter (5) of the main thyristor (TH) by an electric conductor (6).

Abstract: An insulated gate thyristor includes a first-conductivity-type base layer having a high resistivity, first and second second-conductivity-type base regions formed in a surface layer of the first-conductivity-type base layer, a first-conductivity-type source region formed in a surface layer of the first second-conductivity-type base region, and a first-conductivity-type emitter region formed in a surface layer of the second second-conductivity-type base region.

Abstract: An insulated gate thyristor is provided which includes: a first-conductivity-type base layer, first and second second-conductivity-type base regions formed in the base layer, a first-conductivity-type source region formed in the first base region, a first-conductivity-type emitter region formed in the second base region, and a gate electrode layer formed on a gate insulating film over the first base region, first-conductivity-type base layer, and second base region, which are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region.

Abstract: A semiconductor power device (100) that includes active cells in an interior region of an epitaxial layer (16) on a semiconductor substrate (12), and an edge termination structure that surrounds the cells and separates the cells from the die edge (48). A polysilicon layer (26) overlies and is electrically insulated from the epitaxial layer (16), a gate metal field plate (36) contacts the polysilicon layer (26), and a portion of the polysilicon layer (26) forms a gate for each cell. Each of the active cells also has a collector/anode terminal formed by the substrate (12), an emitter/cathode terminal formed by a well (18), emitter diffusion (20) and emitter metal (22), and a base formed by the epitaxial layer (16).

Abstract: In a composite controlled semiconductor device having an insulated gate and a power conversion device using the same, a p type semiconductor region forming no channel is provided in the composite device structure between a plurality of p type semiconductor regions forming a channel and the potential of the p type semiconductor region in an ON state takes a value high enough to inject holes into an n type semiconductor region adjacent to the p type semiconductor region.

Abstract: A first metal electrode layer is formed to be electrically connected with a p base region formed in an n drift region. A second metal electrode layer which is electrically connected with an emitter region provided in the p base region is formed. A direct current power supply unit is provided to be electrically connected with the first and second metal electrode layers. The direct current power supply unit functions as means for applying forward bias to a pn junction between the n emitter region and the p base region.

Abstract: A monolithic semiconductor component has a first thyristor having a gate, an anode and a cathode. The gate is connected to the cathode through a first resistor and to the anode through the series connection of a zener diode and a second thyristor. The thyristors are of the vertical type and the zener diode is of the lateral type. The cathode of the zener diode is connected to the cathode of the second thyristor through a metallization forming an output terminal.

Abstract: A method of manufacturing a joined-type semiconductor device having a gate structure. The semiconductor device includes a first and second semiconductor substrates each having a substrate body, and a first and a second main surfaces which are opposite to each other. A gate structure is formed in the first main surface of the first substrate. A highly-doped semiconductor layer is formed in the first main surface of the second substrate and has an impurity-concentration which is higher than that of the substrate body of the second substrate. The first main surfaces of the two substrates are joined with each other, by subjecting the two substrates to a heat treatment so that impurities in the highly-doped semiconductor layer of the second substrate are driven into the surface region of the first substrate, and a diffusion layer is thereby formed in the first main surface of the first substrate.

Abstract: An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

Abstract: A semiconductor device comprises a plurality of IGBT-like cells arranged in groups on a single wafer of silicon. Each group of cells has a unified gate structure and a unified source structure electrically insulated therefrom but physically overlying it. The gate structure of each group of cells is brought via a removable link to a single gate electrode for the whole device, so that the gate connection to any group of cells may be broken by removing the link, thus disabling the corresponding group of cells. Also, each group of cells is provided separately with a built-in controlled shunt conductance between its source structure and its gate structure.

Abstract: A bidirectional thyristor structure with a single MOS gate controlled turn off capability. In a vertical conduction embodiment, the device has a six layer structure including a backside diffusion. One vertical conduction structure includes a single body region at the first surface of the device for conduction in both the forward and reverse directions. Another vertical conduction structure includes a two body regions at the first surface, one for controlling forward conduction and the other for controlling reverse conduction. The vertical conduction embodiments are preferably implemented in a cellular geometry, with a large number of symmetrical cells connected in parallel. The bidirectional thyristor of the present invention can also be provided in a lateral conduction structure for power IC applications.

Abstract: A thyristor structure in which the DMOSFET connecting the N.sup.+ emitter to the N.sup.- drift region is eliminated and instead replaced with a DMOSFET connecting the N.sup.+ cathode to the N- drift region providing the base drive for the PNP transistor of the thyristor structure. The thyristor structure of the present invention provides lower on-state voltage drop as compared to prior art EST structures.

Abstract: MOS-gate controlled thyristor structures which have current saturation characteristics, do not have any parasitic thyristor structure, and require only a single gate drive. A resistive structure such as a MOSFET, Schottky diode, PN junction diode, diffused resistor or punch-through device (e.g. punch through PNP structure) is incorporated in series with the N.sup.+ emitter of the thyristor. In the on-state of the device, with a positive gate voltage, when operating at high currents, because of the voltage drop in the resistive structure in series with the N.sup.+ emitter, the potential of the N.sup.+ emitter, and along with it the potential of the P base, increases. When the potential is increased beyond a certain predetermined value, diversion of current is accomplished by one of the following ways: (i) the smallest distance between the P base region and the P.sup.+ cathode is such that punch-through occurs in these regions.

Abstract: An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

Abstract: After selectively forming P.sup.+ -type gate regions 14 in the upper surface of a first N.sup.- -type semiconductor substrate 10, gate electrodes 30 are selectively formed on the P.sup.+ -type gate regions. A P.sup.+ -type layer 12 is formed in the lower surface of the N.sup.- -type substrate 10. Recessed portions 26 which can house the gate electrodes are formed in the lower surface of the second N.sup.- -type semiconductor substrate 20 and an N.sup.+ -type layer 22 is formed in the upper surface thereof. After removing impurities from the surfaces of the first and second semiconductor substrates 10 and 20 by RCA cleaning, the surfaces are cleaned with a pure water and are dried by a spinner. Then the substrates 10 and 20 are joined to each other by heating the substrates 10 and 20 at 700-1100.degree. C. in an H.sub.2 atmosphere, while the upper surface of the first semiconductor substrate 10 is brought into contact with projected portions 29 on the lower surface of the second semiconductor substrate 20.

Abstract: An insulated-gate semiconductor device comprises a p type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

Abstract: In a power semiconductor device, an n-base is formed on a p-emitter layer. On the n-base layer, a p-base layer, an n-emitter layer, and a high-concentration p-layer are formed laterally. In the p-base layer, an n-source layer is formed a specified distance apart from the n-emitter layer. In the n-emitter layer, a p-source layer is formed a specified distance apart from the high-concentration p-layer. A first gate electrode is formed via a first gate insulating film on the region sandwiched by the n-source layer and the n-emitter layer. A second gate electrode is formed via a second gate insulating film on the region sandwiched by the high-concentration p-layer and the p-source layer. On the p-emitter layer, a first main electrode is formed. A second main electrode is formed so as to be in contact with the p-base layer, the n-source layer, and the p-source layer.

Abstract: A MOS-controlled thyristor which has current saturation characteristics and does not have any parasitic thyristor structure. In some embodiments, the device has two gate drives and is a four terminal device. In other embodiments, the device requires only a single gate drive and is a three terminal device. The device can be constructed in a cellular geometry. In all embodiments, the device has superior turn-off characteristics and a wider Safe-Operating-Area because the N.sup.++ emitter/P base junction is reverse biased during turn-off.

Abstract: An insulated gate field effect device (1a,1b,1c,1d) has a semiconductor body (2) with a first region (3) of one conductivity type, a second region (4) of the opposite conductivity type, a third region (6) of the one conductivity type (7) separated from the first region (3) by the second region (4) and at least one injector region (8) for injecting charge carriers of the opposite conductivity type into the first region (3). The conduction channel area (40) adjoining the insulated gate (9, 10) has first and second subsidiary areas (40 and 40b) for providing respective first and second subsidiary conduction channels.

Abstract: A gate-controlled bipolar transistor with buried collector includes a wide base bipolar transistor in a semiconductor substrate having a trench at a face thereof. A dual-channel insulated-gate field effect transistor (IGFET) is also included adjacent a sidewall of the trench for providing gated turn-on and turn-off control of the bipolar transistor. The bipolar transistor includes a buried collector region at a bottom of the trench, which is electrically connected to a cathode contact at the face. An emitter of the transistor is electrically connected to an anode contact at an opposing face of the substrate. For turn-on, the base of the bipolar transistor is electrically connected to the cathode contact upon the application of a gate bias signal to the IGFET. By electrically connecting the base to the cathode contact, forward conduction can be established once the anode contact is appropriately biased relative to the cathode contact.

Abstract: A MOS-controlled thyristor which has current saturation characteristics and does not have any parasitic thyristor structure. The device requires only a single gate drive and is a three terminal device. The device can be constructed in a cellular geometry. In all embodiments, the device has superior turn-off characteristics and a wider Safe-Operating-Area because the N.sup.++ emitter/P base junction is reverse biased during turn-off.

Abstract: A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.

Abstract: An integrated power switch structure comprises a lateral MOS transistor (3) and a lateral or vertical thyristor (2). The drain-source path of the lateral MOS transistor (3) is in series with the cathode-anode path of the thyristor (2). In order to ensure that the power switch structure reliably switches on and off with great dielectric strength and low switch-on resistance, at least the source electrode of the lateral MOS transistor (3) is insulated against the substrate (7) by means of a buried oxide layer (8) in accordance with the present invention.

Abstract: A non-planar MOS-controlled thyristor (MCT) which improved turn-off capabilities. The unique non-planar geometry brings the MOS channel region closer to the active thyristor junction, thereby reducing an "effective" resistance which inhibits turn-off of prior art devices 10. This effective resistance is a combination of the resistance through the MOS and the parasitic resistance between the MOS and active thyristor junction. For efficient thyristor turn-off at high current, the effective resistance should be about 0.6 v or less. Both the recessed gate 30 and the MCT with built-up cathode 60 have effective resistances of about 0.6 v or less.

Abstract: In a semiconductor device having insulated gate field effect transistors and bipolar transistors, a buried layer of a first conductivity type having an impurity concentration higher than that of a second layer of the first conductivity type is disposed in at least a lower region between a second layer of a second conductivity type and a third layer of the second conductivity type and in the vicinity of a boundary between the second layer of the first conductivity type, which serves as back gates of the field effect transistors and base layers of the bipolar transistors, and the first layer of the second conductivity type.

Abstract: The semiconductor device is formed of an EST part and an IGBT part, wherein the EST part has a first MOSFET and a second MOSFET synchronously switching, and the IGBT part has a third MOSFET controllable independently from them. At a turn-off of the semiconductor device, when turning off the first and second MOSFETs while keeping the third MOSFET at an on-state, IGBT operation remains. Thus, the current path which tends to flow to an emitter region changes toward an emitter electrode side even if the recovery of the potential barrier is late due to the junction in the emitter region, and the charge accumulation to the emitter region is restrained. After the potential barrier is recovered, the third MOSFET is turned off. Controllable turn-off current can be enlarged and turn-off time can be shortened.

Abstract: A self arc-extinguishing thyristor having a large main current is disclosed. An n-type base layer is formed on a p-type anode layer. The n-type base layer includes in its top center portion a relatively heavily doped p+-type region which is surrounded by p-type region. A p-type base layer is locally coated at its top surface with a relatively thin first n-type emitter layer and a relatively thick second n-type emitter layer. A gate electrode buried in a gate oxide film is disposed on two channel regions and areas around the same. This structure suppresses a current amplification factor of a parasitic thyristor which is formed by the n-type base layer, the p-type region and the first n-type emitter layer, which in turn represses latching up of the parasitic thyristor.

Abstract: A self turn-off power semiconductor device includes a P type emitter layer, a high resistive N type base layer, a P type base layer and a MOS channel structure for injecting electrons into the N type base layer. A series of trench-like grooves are formed in the top surface of a substrate constituting the N type base layer at a constant interval. Insulated gate electrodes are buried in these grooves. The injection efficiency of electrons into the base layer is enhanced by locally controlling the flow of holes in the N type base layer. Controlling the flow of holes is achieved by specifically arranging the width of a hole-bypass path among the grooves, the trench width and the placement distance of the grooves, thereby causing the accumulation of carriers to increase in the base layer to decrease the on-resistance of the device.

Abstract: A thyristor with an insulated gate includes a p-type emitter layer, an n-type base layer, a p-type base layer, and an n-type emitter layer. A drain electrode contacting the p-type base layer is formed adjacent to one side of the n-type emitter layer. An n-type drain layer, which is short-circuited with the p-type base layer by the drain electrode, is formed. An n-type source layer is formed a predetermined distance away from the n-type drain layer. A turn-off insulated gate is formed between the n-type source layer and the n-type drain layer. A source electrode is connected to a cathode electrode. Thereby, turn-off capability of the thyristor can be improved.

Abstract: An emitter of a thyristor is divided into a plurality of emitter regions. An electrode is provided next to each of these regions, and a turn-off current path proceeds via this electrode from the base adjoining the emitter region over a first field effect transistor to a main terminal of the thyristor. Every emitter region is also connected to this main terminal via a second field effect transistor which is integrated into the semiconductor body of the thyristor, or is manufactured in thin-film technology.

Abstract: A base resistance controlled thyristor with single-polarity and dual-polarity turn-on and turn-off control includes a turn-off device provided between the second base region and the cathode of a thyristor. Controlled turn-off is provided by either a near-zero positive bias or a negative bias being applied to the turn-off device. In the preferred embodiment, the turn-off device is a P-channel depletion-mode MOSFET in the surface of a semiconductor substrate. Accordingly, an accumulation-layer channel can be formed between the second base region and the cathode in response to a negative bias. Alternatively, if single-polarity control is desired, the P-type channel is provided to turn-off the device in response to a near-zero positive bias. In either type of operation, however, advantages are obtained over conventional turn-off devices wherein inversion-layer channels are used.