Abstract: A semiconductor device has a low lifetime layer in a selective portion of an N-type drain region to prevent a change in the element characteristic due to Fe contaminants, even if the device is kept at a high temperature. An impurity of a concentration of at least 10.sup.16 atoms/cm.sup.3 is deposited on a first main surface of the N-type drain region, and diffused into the region to a depth of 10 .mu.m, thereby forming a P-type anode region. An anode metal electrode is formed on the surface of the anode region. A P-type base region and an N-type source region are formed in a second main surface of the N-type drain region by ion injection or the like. A gate electrode is formed above the second main surface with a gate oxide film interposed therebetween. A metal gate electrode is formed in contact with the gate electrode. A source metal electrode is formed on the source region and the base region so as to short-circuit them. The low lifetime layer is formed in a selective portion of the N-type drain region.

Abstract: A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in the active regions of the integrated device so that the ions form bubbles in the active regions. A further thermal treatment is performed after the formation of bubbles of the noble gas in order to improve the structure of the bubbles and to make the noble gas evaporate, leaving cavities in the active regions.

Abstract: In a semiconductor device, such as a diode and thyristor, having at least one pn junction between a pair of main surfaces, a first main electrode formed on the surface of one of the main surfaces and a second main electrode formed on the surface of the other one of the main surfaces, a semiconductor lattice defect is formed such that its lattice defect density increases gradually in the direction from the first main electrode to the second main electrode. Since the distribution of the carrier density in the conduction state can be flattened, the reverse recovery charge can be reduced substantially without causing the ON-state voltage to increase.

Abstract: An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

Abstract: It is an object to provide a semiconductor apparatus having both fast switching characteristics and high dielectric breakdown strength or small leakage current characteristics, as well as a process for fabricating such improved semiconductor apparatus. The apparatus comprises a semiconductor substrate; a semiconductor layer on said semiconductor substrate, said semiconductor layer having a pn junction formed along the surface of said semiconductor substrate, wherein crystal defects being formed by irradiation with particle rays to the only vertical direction of said pn junction; and a silicon nitride film provided on the substrate surface of said layer for restraining the exposure to particle rays being provided on the substrate surface of said element in the areas other than said pn junction.

Abstract: An N.sup.- layer (11) of a low impurity concentration is formed on an upper major surface of an N.sup.+ layer (13) of a high impurity concentration in a diode (10). A P layer (12) is further formed on its upper major surface. The N.sup.- layer (11) is in a multilayer structure of first to third regions (11a to 11c) having carrier lifetimes .tau..sub.1, .tau..sub.2 and .tau..sub.3 respectively. These lifetimes are in relation .tau..sub.2 <.tau..sub.1 <.tau..sub.3. Due to the large lifetime .tau..sub.3 of the third region (11c), soft recovery can be implemented. The fact that the lifetime .tau..sub.3 of the third region (11c) is large serves as a factor reducing a forward voltage V.sub.f. It is possible to attain soft recovery without increasing the forward voltage V.sub.F by properly designing these lifetimes and thicknesses.

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.3 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: The present invention is directed to power semiconductor devices and, more particularly, to a semiconductor device with a static induction buffer structure which reduces the resistance of a buffer layer, enhances the injection efficiency of holes from the anode and permits the application of a high-intensity electric field across the cathode and anode, and a semiconductor device with a drift buffer structure in which an impurity density (concentration) gradient is set in a buffer layer to generate an internal electric field for holes to enhance the injection efficiency of holes from the anode and increase the electron storage efficiency or and impurity density (concentration) gradient is set in an anode region to generate an internal electric field for electrons and a high-intensity electric field can be applied across the cathode and anode.

Abstract: A semiconductor device comprises a semiconductor substrate having first and second major surfaces, semiconductor elements formed on the first surface of the semiconductor substrate, and a blocking layer formed within the substrate at a given distance from the second major surface for blocking the passage of heavy metals through the semiconductor substrate.

Abstract: For increasing the electric strength of a semiconductor component that comprises a sequence of semiconductor layers of alternating conductivity type and which is adapted to be charged with a voltage that biases at least one of the p-n junctions that separate the layers from one another in the non-conducting direction, the carrier life is reduced only in the lateral region of the edge termination of this p-n junction. The carrier life is reduced by irradiation with electrons or protons or by introducing atoms having recombination properties.

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to .about.10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: A merged P-I-N/Schottky power rectifier includes trenches, and P-N junctions along the walls of the trenches and along the bottoms of the trenches. By forming the P-N junctions along the trench walls, the total area of the P-N junctions relative to the surface area of the device can be increased, to thereby improve the device's on-state characteristics without sacrificing the total area of the Schottky region. The trenches may be U or V shaped in transverse cross-section or of other transverse cross-sectional shape, and the trenches may be polygonal or circular in top view.

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.