Abstract: A method of fabricating a device includes providing a fin having an epitaxial layer stack with a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes exposing lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers within a source/drain region of the semiconductor device. In some examples, the method further includes etching the exposed lateral surfaces of the plurality of dummy layers to form recesses and forming an inner spacer within each of the recesses, where the inner spacer includes a sidewall profile having a convex shape. In some cases, and after forming the inner spacer, the method further includes performing a sheet trim process to tune the sidewall profile of the inner spacer such that the convex shape of the sidewall profile becomes a substantially vertical sidewall surface after the sheet trim process.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for clock recovery in subcarrier based coherent optical systems. In one aspect, an apparatus includes a plurality of phase detectors configured to generate a plurality of phase detection outputs by detecting a plurality of digital signals associated with a plurality of frequency bands, each of the plurality of phase detection outputs being associated with a respective one of the plurality of frequency bands, alignment circuitry coupled to the plurality of phase detectors and configured to align phases of the plurality of phase detection outputs to be substantially same, and averaging circuitry coupled to the alignment circuitry and configured to generate a particular output based on the plurality of phase detection outputs with the aligned phases. The plurality of digital signals is adjusted based on the particular output.

Abstract: A semiconductor device includes a base substrate, a first thin film transistor disposed on the base substrate, a second thin film transistor disposed on the base substrate, and a plurality of insulating layers disposed on the base substrate. The first thin film transistor includes a first input electrode, a first output electrode, a first control electrode, and a first oxide semiconductor pattern, which are disposed on the base substrate. The second thin film transistor includes a second input electrode, a second output electrode, a second control electrode, and a second oxide semiconductor pattern, which are disposed on the base substrate. The first oxide semiconductor pattern includes a crystalline oxide semiconductor, and the second oxide semiconductor pattern includes an oxide semiconductor having a crystal structure different from a crystal structure of the first oxide semiconductor pattern.

Abstract: A semiconductor structure includes a semiconductor substrate having a trench isolation region formed therein. A conductive gate electrode is buried in the trench isolation region. An air gap is disposed between the conductive gate electrode and the semiconductor substrate.

Abstract: Provided are a display device and a method of manufacturing the same. A display device includes a coplanar thin-film transistor and a capacitor. The coplanar thin-film transistor comprises a gate electrode, an active layer including an oxide semiconductor, a source electrode and a drain electrode. The capacitor comprises a lower electrode, intermediate electrode and upper electrode. And the lower electrode is comprised of the same material as the active layer, and is conductivized. Also, the upper electrode is connected to the lower electrode. By using the conductivized lower electrode, the capacitor is configured to operate as multiple capacitors. Thus, the size of the capacitor is reduced, and sufficient capacitance may be secured with the capacitor with a smaller area. In this way, the area of each sub-pixel in the display device may be reduced, thereby achieving high resolution.

Abstract: The present invention provides a liquid crystal display panel. The liquid crystal display panel includes drive circuits, data lines for transmitting the data signals, scan lines, and pixel units. Each of the drive circuits includes a level shifter and an output buffer. Voltage signals which are inputted to a non-inverting input terminal and an inverting input terminal of the level shifter are determined according to a number of inverting amplifiers of the output buffer. The present invention further provides a liquid crystal display device. The present invention can effectively decrease the manufacture cost of the liquid crystal display panel.

Abstract: The present application provides a thin film transistor, an active matrix organic light emitting diode assembly and a method for manufacturing the same. The thin film transistor includes: a substrate; a buffer layer on the substrate; a semiconductor layer on the buffer layer, including a source region, a drain region and a channel region; a first gate insulating layer covering the semiconductor layer; a second gate insulating layer foot on the first gate insulating layer, a width of the second gate insulating layer foot being smaller than a width of the first gate insulating layer; and a gate electrode on the second gate insulating layer foot; wherein a part of the first gate insulating layer that is on the semiconductor layer has a flat upper surface. The present application may obtain better implantation profiles of source region and drain region, thereby obtaining better uniformity in TFT performance.

Abstract: A laser system may include a first portion of laser host material adapted for amplification of laser radiation and a second portion of laser host material surrounding the first portion which may be adapted for suppression of ASE. The first portion of laser host material and the second portion of laser host material may be respectively doped at a different predetermined concentration of laser ions. A heat exchanger may be provided to dissipate heat from the first portion and the second portion.

Abstract: An electrically programmable device with embedded EEPROM and method for making thereof. The method includes providing a substrate including a first device region and a second device region, growing a first gate oxide layer in the first device region and the second device region, and forming a first diffusion region in the first device region and a second diffusion region and a third diffusion region in the second device region. Additionally, the method includes implanting a first plurality of ions to form a fourth diffusion region in the first device region and a fifth diffusion region in the second device region. The fourth diffusion region overlaps with the first diffusion region.

Abstract: A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded.

Abstract: In an operational amplifier including first and second power supply terminals, first and second input terminals, and a first and second output terminals, a first differential amplifier circuit includes first and second MOS transistors with a common source connected to a first tail current source, first and second load resistors and a first non-doped MOS transistor connected between the first and second resistors and the second power supply terminal. A second differential amplifier circuit includes third and fourth MOS transistors with a common source connected to a second tail current source, third and fourth load resistors and a second non-doped MOS transistor connected between the third and fourth load resistors and the second power supply terminal.

Abstract: The present invention is directed to improve high frequency characteristics by reducing inductance of a source. In an HEMT assembled in a power amplifier device, each of a drain electrode, a source electrode, and a gate electrode is constructed by a base portion and a plurality of fingers projected in a comb-teeth shape from the base portion, and the fingers of the electrodes mesh with each other. In the source electrode, a width of the fingers positioned at both ends of the plurality of fingers is wider than a width of each of the fingers positioned between both ends. The width of each of the fingers positioned at both ends is a width equal to or larger than a sum of the widths of the plurality of fingers positioned between both ends, and the width of the base portion is wider than that of each of the fingers positioned at both ends. An electrode pad provided for the source base portion and an external electrode terminal are connected to each other via a conductive wire.

Abstract: A semiconductor component is arranged in a semiconductor body and has at least one integrated radially symmetrical lateral resistance having a location-dependent sheet resistance, the radial dependence of which is preferably configured such that the differential resistance dR is radially constant or the power dissipated in the resistance is radially constant.

Abstract: An MRAM cell includes a bottom electrode layer, a magnetic reference layer, an insulating layer, a synthetic free layer, and a top electrode layer. The synthetic free layer includes a first magnetic layer, a ruthenium anti-ferromagnetic coupling layer, and a second magnetic layer. The magnetic reference layer and the first and second magnetic layers are fabricated using magnetic materials such as CoFeB, CoFe, or a bilayer of NiFe and CoFe. The first magnetic layer of the synthetic free layer is made thicker than the second magnetic layer of the synthetic free layer for proper operation.

Abstract: An integrated NMOS circuit including an active stack having a plurality of isolated p-well active devices M1-M3, a bias stack having a plurality of diode-connected isolated p-well bias devices M4-M6, the gate of each of the plurality of diode-connected isolated p-well bias devices coupled to the gate of a corresponding one of the plurality of isolated p-well active devices, the bulk of each of the plurality of diode-connected isolated p-well bias devices coupled directly to the bulk of the corresponding one of the plurality of isolated p-well active devices, and the source of each of the plurality of diode-connected isolated p-well bias devices coupled directly to the bulk of the corresponding diode-connected isolated p-well bias device.

Abstract: An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.

Abstract: In a case of a liquid crystal display apparatus, a gate insulating film of a TFT driven at a low voltage (3.3 V or 5 V) is constituted by one insulating film, and a thickness thereof is set to, for example, 30 nm. This TFT has a structure in which LDD regions (low concentration impurity regions) are not provided. A TFT having a CMOS structure, which is driven at a high voltage (18 V), has a gate insulating film constituted by two insulating films having a thickness of, for example, 130 nm in total. In an n-type TFT, a low concentration impurity region is provided on a drain side. A p-type TFT has a structure having no LDD region. A pixel TFT has a gate insulating film constituted by two insulating films, and LDD regions provided in both of its source/drain.

Abstract: Within a method for forming a thin film transistor (TFT) structure, there is first provided a substrate. There is then formed over the substrate a gate electrode. There is then formed adjacent to the gate electrode but not covering a top surface of the gate electrode a backfilling dielectric layer. There is then formed over and covering the top surface of the gate electrode a gate dielectric layer. There is then formed over and covering the gate dielectric layer an active semiconductor layer. Finally, there is then formed over and in electrical communication with the active semiconductor layer a pair of source/drain electrodes, where the pair of source/drain electrodes having a separation distance which defines a channel region of the active semiconductor layer. The method for forming the thin film transistor (TFT) structure contemplates a thin film transistor (TFT) structure fabricated in accord with the method for forming the thin film transistor (TFT) structure.

Abstract: In an image sensing array, the structure of the image sensor pixel is based on a vertical punch through transistor with a junction gate surrounding its source and connected to it, the junction gate being further surrounded by an MOS gate. The new pixel has a large conversion gain, high dynamic range, blooming protection, and low dark current. It senses charge nondestructively with a complete charge removal, which avoids generation of kTC noise. The pixel fabrication is compatible with CMOS processing that includes two metal layers. The array also includes the pixel reset through column sense lines, polysilicon field plate in the image-sensing area for improved pixel isolation, denser pixel packing, and either n-channel or p-channel addressing transistor.

Abstract: A semiconductor device comprising a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.

Abstract: A sensor 1 produces an output that changes linearly with absolute temperature. In response to the output, a reference voltage generator 13 produces reference voltages Vhigh and Vlow that change linearly with absolute temperature. A Schmidt trigger 14 compares the output signal from a sensor signal amplifier 12 with the reference voltages for performing on-off output. A sensor signal amplifier 12 with a temperature-independent amplification factor amplifies the output signal from the sensor 1 while performing offset compensation. A sensor signal processing circuit 2 is formed out of thin-film silicon disposed on an insulating substrate. The output from the sensor 1 undergoes accurate temperature compensation over a wide temperature range from a low temperature to a high temperature, achieving a reliable operation with accuracy at high temperature.

Abstract: The present invention provides a thin film transistor (TFT) and a fabrication method thereof which suppresses the back channel effects in which a leakage current flows between a source electrode and a drain electrode at times during a turn off state of the TFT. A thin silicon oxynitride film 90 having a thickness preferably equal to or less than 50 Å is formed between an amorphous silicon layer 40 and a channel passivation film 50 (a silicon nitride film) above a back channel region 100 between a source electrode and a drain electrode of an inverted staggered type TFT to cause Si—O bonds to exist in an upper interface of the amorphous silicon layer. The Si—O bonds increase the Density of States in the back channel region and has an effect for suppressing the leakage current through the back channel region 100 at times during the turn off of the TFT.

Abstract: Given too great a dU/dt load of a thyristor, this can trigger in uncontrolled fashion in the region of the cathode surface. Since the plasma only propagates poorly there and the current density consequently reaches critical values very quickly, there is the risk of destruction of the thyristor due to local overheating. The proposed thyristor has a centrally placed BOD structure and a plurality of auxiliary thyristors (1.-5. AG) annularly surrounding the BOD structure. The resistance of the cathode-side base (8) is locally increased under the emitter region (11) allocated to the innermost auxiliary thyristor (1. AG). Since the width (L) and the sheet resistivity of this annular zone (15) critically influences the dU/dt loadability of the first auxiliary thyristor (1.

Abstract: An amplifying-gate thyristor having an increased integrated circuit includes a main thyristor and an amplifying thyristor. The amplifying thyristor is of the gate turnoff-type. The main thyristor and the amplifying thyristor are such that the amplifying thyristor remains in the conductive state while the main thyristor is conductive. A control circuit turns off the amplifying thyristor when the current through the main thyristor is approximately its hold current.

Abstract: A notched insulation gate static induction transistor integrated circuit ording to the present invention comprises an enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to prevent current from flowing in a standby mode, and a depletion enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to cause current to slightly flow in the standby mode. The enhancement mode CMOS logic circuit and the depletion enhancement mode CMOS logic circuit are formed on a major surface of a substrate, and the depletion enhancement mode CMOS logic circuit is used in a circuit in which an average power consumption in a switching operation is higher than that in the standby mode.