Abstract: A thyristor includes a base region, a pair of first doping regions, at least one second doping region, at least one third doping region, and a pair of metal layers. The first doping regions are formed in two opposite sides of the base region and touch the base region. The second doping region is formed between the base region and one of the first doping regions. The second doping region touches the base region and the first doping region. The third doping region is formed in one of the first doping regions and touches the first doping region. The type of the first doping region is different from the types of the second doping region, the third doping region, and the base region. The metal layers touch the first doping regions respectively. The first doping regions and the third doping region are located between the metal layers.

Abstract: According to one embodiment, a semiconductor device that has a rectification element includes a semiconductor substrate, a first well region of a first conductivity type formed on the semiconductor substrate, a second well region of a second conductivity type formed on the semiconductor substrate, and a plurality of fins arranged over the first well region and the second well region at a first pitch in the same direction. In the semiconductor device, the rectification element includes a cathode region, an anode region, a well contact region, and a trigger region that are configured using fins. These regions are connected to each wiring portion to form a PNP-type bipolar transistor and an NPN-type bipolar transistor.

Abstract: A metal complex is used as p-dopant for an organic semiconducting matrix material, to an organic semiconductor material and to an organic light-emitting diode. Also disclosed is the use of metal complexes, which function as Lewis acids, as p-dopants in organic matrix materials.

Abstract: A phase control thyristor includes a main gate structure and a plurality of local emitter shorts dots arranged in a shorts pattern on a cathode side of the thyristor. The main gate structure includes longitudinal main gate beams extending from a center region of the cathode side towards a circumferential region. Neighboring main gate beams are arranged with a distance with respect to an associated intermediate middle line. The shorts pattern is more homogeneous in a region closer to a main gate beam than in a region closer to an associated middle line. Adaptions to match shorts patterns in neighboring segments of the cathode side surface are made in regions away from the main gate beams such that an electron hole plasma spreading from the main gate beam is not interfered by any inhomogeneity of the shorts dots pattern. The design rules enable an improvement of the thyristor operational characteristics.

Abstract: A bipolar power semiconductor component configured as an IGBT includes a semiconductor body, in which a p-doped emitter, an n-doped base, a p-doped base and an n-doped main emitter are arranged successively in a vertical direction. The p-doped emitter has a number of heavily p-doped zones having a locally increased p-type doping.

Abstract: A sensor configured to sense an external event including: a first component having a first impedance that changes when the external event occurs and being connected between a reference voltage node and an output node wherein the output node is configured to provide, when the external event occurs, a feedback signal to the first component that further changes the first impedance and wherein the first component is a field effect transistor comprising: a gate formed from a conductive core of a nanowire and connected to the output node; a gate dielectric formed from an insulating shell of the nanowire; a source/drain electrode connected to the output node; a source/drain electrode connected to the reference node; and a channel extending between the source/drain electrodes.

Abstract: In order to protect an integrated circuit provided with a cryptoprocessor from attacks aiming to reveal secrets, it is anticipated to use a component sensitive to the activation of a parasitic (latchup) thyristor and/or to the activation of a parasitic bipolar transistor, or to design a circuit having this property. If the component is stressed due to the presence of this circuit, it is immediately deactivated, actually preventing the revelation of the secrets thereof.

Abstract: The light-emitting element chip includes: a substrate; a light-emitting portion including plural light-emitting elements each having a first semiconductor layer that has a first conductivity type and that is stacked on the substrate, a second semiconductor layer that has a second conductivity type and that is stacked on the first semiconductor layer, the second conductivity type being a conductivity type different from the first conductivity type, a third semiconductor layer that has the first conductivity type and that is stacked on the second semiconductor layer, and a fourth semiconductor layer that has the second conductivity type and that is stacked on the third semiconductor layer; and a controller including a logical operation element that performs logical operation for causing the plural light-emitting elements to perform a light-emitting operation, the logical operation element being formed by combining some sequential layers of the first, second, third and fourth semiconductor layers.

Abstract: A semiconductor device includes a direct light-triggered thyristor triggered by an optical gate signal, a first optical fiber connected to the direct light-triggered thyristor and through which the optical gate signal is transmitted, a second optical fiber used to extend the first optical fiber, and a inter-optical-fiber relaying unit configured to connect the first optical fiber to the second optical fiber and to input the optical gate signal output from the second optical fiber to the first optical fiber.

Abstract: According to an aspect of the invention, a light-emitting element includes a shift thyristor, a light emitting thyristor, and a vertical type gate load resistor. The shift thyristor includes a first anode layer, a first gate layer, and a first cathode layer. The light-emitting thyristor includes a second anode layer, a second gate layer, and a second cathode layer. The vertical type gate load resistor is arranged on the first gate layer under a power line and limits a current flowing from the first gate layer and the second gate layer to the power line.

Abstract: The light-emitting element chip includes: a substrate; a light-emitting portion including plural light-emitting elements each having a first semiconductor layer that has a first conductivity type and that is stacked on the substrate, a second semiconductor layer that has a second conductivity type and that is stacked on the first semiconductor layer, the second conductivity type being a conductivity type different from the first conductivity type, a third semiconductor layer that has the first conductivity type and that is stacked on the second semiconductor layer, and a fourth semiconductor layer that has the second conductivity type and that is stacked on the third semiconductor layer; and a controller including a logical operation element that performs logical operation for causing the plural light-emitting elements to perform a light-emitting operation, the logical operation element being formed by combining some sequential layers of the first, second, third and fourth semiconductor layers.

Abstract: A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction.

Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.

Abstract: A semiconductor device includes: a bulk semiconductor substrate; a thyristor formed in the bulk semiconductor substrate; a gate electrode formed at the third region; and a well region. The thyristor included a first region of a first conduction type, a second region of a second conduction type opposite to the first conduction type, a third region of the first conduction type, and a fourth region of the second conduction type, junctioned in order. The well region of the second conduction type is formed in the bulk semiconductor substrate, the third region is formed in the well region. A first voltage is impressed on the first region side of the thyristor, a second voltage higher than the first voltage is impressed on the fourth region side of the thyristor, and a voltage higher than or equal to the first voltage is impressed on the well region.

Abstract: An over-voltage protection thyristor has reduced junction capacitance making it suitable for use in high bandwidth applications. The reduced capacitance is achieved through the introduction of a deep base region. The deep base region has a graded doping concentration which reduces with depth into the substrate. The thyristor is useful for protecting sensitive electrical equipment from transient surges.

Abstract: A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured to provide a trigger current to the dual-direction silicon controlled rectifier when a desired voltage between the first and second grounds is reached.

Abstract: Provided is a semiconductor bistable switching device that includes a thyristor portion including an anode layer, a drift layer, a gate layer and a cathode layer, the gate layer operable to receive a gate trigger current that, when the anode layer is positively biased relative to the cathode layer, causes the thyristor portion to latch into a conducting mode between the anode and the cathode. The device also includes a transistor portion formed on the thyristor portion, the transistor portion including a source, a drain and a transistor gate, the drain coupled to the cathode of the thyristor portion.

Abstract: Bipolar power semiconductor component comprising a p-type emitter and more highly doped zones in the p-type emitter, and production method. The invention relates to a bipolar power semiconductor component comprising a semiconductor body (1), in which a p-doped emitter (8), an n-doped base (7), a p-doped base (6) and an n-doped main emitter (5) are arranged successively in a vertical direction (v). The p-doped emitter (8) has a number of heavily p-doped zones (82) having a locally increased p-type doping.

Abstract: An electronic device having an LV-well element trigger structure that reduces the effective snapback trigger voltage in MOS drivers or ESD protection devices. A reduced triggering voltage facilitates multi-finger turn-on and thus uniform current flow and/or helps to avoid competitive triggering issues.

Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.

Abstract: A SGPMOS transistor includes a base, a P-type diffusion layer, a gate electrode, and a LOCOS oxide film. The base includes at least one of a N-type semiconductor substrate, a P-type semiconductor substrate, and a N-type well. The P-type diffusion layer includes a P-type source and a P-type drain. At least the P-type drain includes a double diffusion structure including first and second P-type drain diffusion layers. The LOCOS oxide film is provided on the first P-type drain diffusion layer and covered by an end of the gate electrode. The first and the second P-type drain diffusion layers satisfy a relation of Y<Xj, in which Y represents a distance of the first P-type drain diffusion layer between the second P-type drain diffusion layer and the channel, and Xj represents a difference between depths of the second P-type drain diffusion layer and the first P-type drain diffusion layer.

Abstract: Techniques associated with providing multiple gate insulator thickness for a semiconductor device are generally described. In one example, an apparatus includes a semiconductor fin having an impurity introduced to at least a first side of the fin, a first oxide having a first thickness coupled with the first side of the fin, and a second oxide having a second thickness coupled with a second side of the fin, the second thickness being different from the first thickness as a result of the impurity introduced to the first side of the fin.

Abstract: An HF control bi-directional switch component of the type having its gate referenced to the rear surface formed in the front surface of a peripheral well of the component, including two independent gate regions intended to be respectively connected to terminals of a transformer having a midpoint connected to the rear surface terminal of the component.

Abstract: A main thyristor (1) has a recovery protection which is integrated into a drive thyristor (2) whose n-doped emitter (25) is electrically connected to a main thyristor control terminal (140). Moreover, the p-doped emitter (28) of the drive thyristor (2) is electrically connected to the p-doped emitter (18) of the main thyristor (1). Various optional measures for realizing a recovery protection are provided in this case. A method for producing a thyristor system having a main thyristor and a drive thyristor, the drive thyristor (2) having anode short circuits (211) involves introducing particles (230) into a target region (225) of the semiconductor body (200) of the drive thyristor (2), the distance between the target region (225) and a front side (201) of the semiconductor body (200) opposite to the rear side (202) being less than or equal to the distance between the p-doped emitter (28) and the front side (201).

Abstract: A microelectronic device includes a die having an active surface and a non-active surface. To assemble the microelectronic device, the active surface of the die is placed on a substrate. A first material is dispensed between the active surface of the die and the substrate. A second material is dispensed on at least a portion of the non-active surface of the die. The second material is different than the first material and the first material and the second material are simultaneously cured.

Abstract: A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured to provide a trigger current to the dual-direction silicon controlled rectifier when a desired voltage between the first and second grounds is reached.

Abstract: An optoelectronic circuit includes a resonant cavity formed on a substrate and into which is injected an input digital optical signal that encodes bits of information (each bit representing an OFF logic level or an ON logic level). A heterojunction thyristor device, formed in the resonant cavity, produces an output digital electrical signal corresponding to the input digital optical signal. A sampling clock defines sampling periods that overlap the bits (e.g., ON/OFF pulse durations) in the input digital optical signal. The sampling clock can be in the form of electrical pulses supplied to the n-channel injector terminal(s) and/or p-channel injector terminals of the heterojunction thyristor device. Alternatively, the sampling clock can be in the form of optical pulses that are part of the Optical IN signal that is resonantly absorbed by the device. The heterojunction thyristor device operates in an OFF state and an ON state.

Abstract: A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded.

Abstract: A semiconductor device may include at least one memory cell comprising a negative differential resistance (NDR) device and a control gate coupled thereto. The NDR device may include a superlattice including a plurality of stacked groups of layers, with each group of layers of the superlattice including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A thyristor having a semiconductor body in which a p-doped emitter, an n-doped base, a p-doped base and an n-doped main emitter are arranged successively in a vertical direction starting from a rear face toward a front face. For buffering of the transient heating, a metallization is applied to the front face and/or to the rear face and includes at least one first section which has an area-specific heat capacity of more than 50 J·K?1·m?2 at each point.

Abstract: In an operational amplifier including first and second power supply terminals, first and second input terminals, and a first and second output terminals, a first differential amplifier circuit includes first and second MOS transistors with a common source connected to a first tail current source, first and second load resistors and a first non-doped MOS transistor connected between the first and second resistors and the second power supply terminal. A second differential amplifier circuit includes third and fourth MOS transistors with a common source connected to a second tail current source, third and fourth load resistors and a second non-doped MOS transistor connected between the third and fourth load resistors and the second power supply terminal.

Abstract: A thyristor and family of high speed transistors and optoelectronic devices are obtained on a monolithic substrate (149) with an epitaxial layer structure comprised of two modulation doped transistor structures inverted with respect to each other. The transistor structures are obtained by adding planar doping to the Pseudomorphic High Electron Mobility Transistor (PHEMT) structure. For one transistor, two sheets of planar doping of the same polarity separated by a lightly doped layer are added which are opposite to the modulation doping of the PHEMT. The combination is separated from the PHEMT modulation doping by undoped material. The charge sheets are thin and highly doped. The top charge sheet (168) achieves low gate contact resistance and the bottom charge sheet (153) defines the capacitance of the field-effect transistor (FET) with respect to the modulation doping layer of the PHEMT. For the other transistor, only one additional sheet is added.

Abstract: A thyristor and a method for manufacturing the thyristor that includes a gate region extending from the first major surface into a semiconductor substrate and an anode region extending from the second major surface into the semiconductor substrate. A cathode region extends into a portion of the gate region. Optionally, enhanced doped regions extend into the gate and anode regions. A mesa structure having a height HG is formed from the first major surface and a mesa structure having a height HA is formed from the second major surface. The gate region extends under the first major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HG. The anode region extends under the second major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HA.

Abstract: The present invention is directed to improve high frequency characteristics by reducing inductance of a source. In an HEMT assembled in a power amplifier device, each of a drain electrode, a source electrode, and a gate electrode is constructed by a base portion and a plurality of fingers projected in a comb-teeth shape from the base portion, and the fingers of the electrodes mesh with each other. In the source electrode, a width of the fingers positioned at both ends of the plurality of fingers is wider than a width of each of the fingers positioned between both ends. The width of each of the fingers positioned at both ends is a width equal to or larger than a sum of the widths of the plurality of fingers positioned between both ends, and the width of the base portion is wider than that of each of the fingers positioned at both ends. An electrode pad provided for the source base portion and an external electrode terminal are connected to each other via a conductive wire.

Abstract: A semiconductor system includes a self arc-extinguishing device, and an IGBT that works as a thyristor when a current between a first terminal and a second terminal connected to a second well electrode is small, and as a bipolar transistor when that current is large, and automatically switches between them according to the magnitude of the current. The IGBT is formed with a first conductivity-type semiconductor substrate. On a surface layer of the substrate is a second conductivity-type well region to which a first well electrode is connected. A first conductivity-type emitter region, to which an emitter electrode is connected, is disposed on a surface layer in the well region. A control electrode is disposed through an insulating film partially covering the well and emitter regions. A second conductivity-type well layer, to which the second well electrode is connected, is disposed on a back surface side of the substrate.

Abstract: A vertical SCR switch to be controlled by a high-frequency signal having at least four main alternated layers. The switch includes a gate terminal and a gate reference terminal connected via integrated capacitors to corresponding areas. In the case of a thyristor, having on its front surface side a main P-type semiconductor area formed in an N-type gate semiconductor area, a first portion of the main area being connected to one of the main areas, a second portion of the main area is connected to one of the control terminals via a first integrated capacitor, and a portion of the gate area being connected to the other of the control terminals via a second integrated capacitor.

Abstract: A light-emitting element including a light-emitting thyristor and a schottky barrier diode is provided. A schottky barrier diode is formed by contacting a metal terminal to a gate layer of a three-terminal light-emitting thyristor consisting of a PNPN-structure. A self-scanning light-emitting element array may be driven at 3.0 V by using such a schottky barrier diode as a coupling diode of a diode-coupled self-scanning light-emitting element array.

Abstract: The invention concerns a voltage-controlled triac-type component, formed in a N-type substrate (1) comprising first and second vertical thyristors (Th1, Th2), a first electrode (A2) of the first thyristor, on the front side of the component, corresponding to a first N-type region (6) formed in a first P-type box (5), the first box corresponding to a first electrode (A2) of the second thyristor, the first box containing a second N-type region (8); and a pilot structure comprising, above an extension of a second electrode region (4) of the second thyristor, a second P-type box (11) containing third and fourth N-type regions, the third region (12) and a portion of the second box (11) being connected to a gate terminal (G), the fourth region (13) being connected to the second region (8).

Abstract: A semiconductor component is arranged in a semiconductor body and has at least one integrated radially symmetrical lateral resistance having a location-dependent sheet resistance, the radial dependence of which is preferably configured such that the differential resistance dR is radially constant or the power dissipated in the resistance is radially constant.

Abstract: A family of emitter turn-off thyristors compres a gate turn-on (GTO) thyristor, a first switch, the drain of the first switch being connected to the cathode of the GTO thyristor, and a second switch connected between the gate of the GTO thyristor and the source of the first switch. The first switch consists of a number of paralleled metal oxide semiconductor field effect transistors (MOSFETs). The anode of the GTO thyristor and the source of the first switch serve as the annode and the cathode, respective, of the emitter turn-off thyristor. The emitter turn-off thyristor has four control electrodes; the gate of the GTO thyristor, the control electrode of the second switch, the gate of the first switch, and the cathode of the GTO thyristor.

Abstract: A monolithic bidirectional switch formed in a semiconductor substrate of type N, including a first main vertical thyristor, the rear surface layer of which is of type P, a second main vertical thyristor, the rear surface layer of which is of type N, an auxiliary vertical thyristor, the rear surface layer of which is of type P and is common with that of the first main thyristor, a peripheral region of type P especially connecting the rear surface layer of the auxiliary thyristor to the layer of this thyristor located on the other side of the substrate, a first metallization on the rear surface side, a second metallization on the front surface side connecting the front surface layers of the first and second thyristors. An additional region has a function of isolating the rear surface of the auxiliary thyristor and the first metallization.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. Devices may be formed in the silicon wafer prior to growing the high quality epitaxial layers. Then, to achieve the formation of a compliant substrate, an accommodating buffer layer is grown on silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Compound devices are then formed on the overlying monocrystalline layer.

Abstract: A gate turn-off thyristor includes a substrate formed of n-type silicon carbide; a growth buffer formed of n-type silicon carbide and positioned to overlie said substrate; a field buffer region formed of p-type silicon carbide and positioned to overlie said growth buffer; a drift region formed of p-type silicon carbide and positioned to overlie said field buffer region; a gated base region formed of n-type silicon carbide and positioned to overlie said drift region; a modified anode region formed of first, second and third layers of silicon carbide and positioned to overlie said gated base region, said first layer comprising p-type silicon carbide and disposed adjacent said gated base region, said second layer comprising n-type silicon carbide and disposed adjacent said first layer, said third layer comprising p-type silicon carbide and disposed adjacent said second layer; an anode contact disposed on said third layer of said modified anode region; a cathode contact disposed on said substrate; and a gate cont

Abstract: A semiconductor device comprising a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.

Abstract: A sensor 1 produces an output that changes linearly with absolute temperature. In response to the output, a reference voltage generator 13 produces reference voltages Vhigh and Vlow that change linearly with absolute temperature. A Schmidt trigger 14 compares the output signal from a sensor signal amplifier 12 with the reference voltages for performing on-off output. A sensor signal amplifier 12 with a temperature-independent amplification factor amplifies the output signal from the sensor 1 while performing offset compensation. A sensor signal processing circuit 2 is formed out of thin-film silicon disposed on an insulating substrate. The output from the sensor 1 undergoes accurate temperature compensation over a wide temperature range from a low temperature to a high temperature, achieving a reliable operation with accuracy at high temperature.

Abstract: A monolithic type active matrix semiconductor device comprises a substrate having an insulating surface, a first plurality of thin film transistors formed on the substrate, each having a first channel region comprising an amorphous silicon semiconductor film, and a second plurality of thin film transistors, each having a second channel region comprising a crystalline semiconductor film. The crystalline semiconductor film of the second plurality of thin film transistors has a substantially single crystalline structure (mono-domain structure) and is doped with a recombination center neutralizer at a concentration of 1×1016 to 1×1020 atoms/cm3. The crystalline semiconductor film of the second plurality of thin film transistors contains a catalyst element which is capable of promoting crystallization of silicon.

Abstract: A method for forming a conductive contact having an atomically flat interface is disclosed. A layer containing cobalt and titanium is deposited on a silicon substrate and the resulting structure annealed in a nitrogen containing atmosphere at about 500.degree. C. to about 700.degree. C. A conductive material is deposited on top of the structure formed on anneal. A flat interface, which prevents diffusion of conductive materials into the underlying silicon substrate is formed. The method can be used to form contacts for very small devices and shallow junctions, such as are required for ULSI shallow junctions.

Abstract: Given too great a dU/dt load of a thyristor, this can trigger in uncontrolled fashion in the region of the cathode surface. Since the plasma only propagates poorly there and the current density consequently reaches critical values very quickly, there is the risk of destruction of the thyristor due to local overheating. The proposed thyristor has a centrally placed BOD structure and a plurality of auxiliary thyristors (1.-5. AG) annularly surrounding the BOD structure. The resistance of the cathode-side base (8) is locally increased under the emitter region (11) allocated to the innermost auxiliary thyristor (1. AG). Since the width (L) and the sheet resistivity of this annular zone (15) critically influences the dU/dt loadability of the first auxiliary thyristor (1.

Abstract: A semiconductor component has a semiconductor body with at least one integrated lateral resistor. The lateral resistor is formed with a dopant concentration in the resistor region. The resistor region is located in a region which is accessible from the surface of the semi-conductor component and it has a defined dopant concentration. Scattering centers are provided in the region of the lateral resistor which reduce a temperature dependency of the lateral resistor.

Abstract: An amplifying-gate thyristor having an increased integrated circuit includes a main thyristor and an amplifying thyristor. The amplifying thyristor is of the gate turnoff-type. The main thyristor and the amplifying thyristor are such that the amplifying thyristor remains in the conductive state while the main thyristor is conductive. A control circuit turns off the amplifying thyristor when the current through the main thyristor is approximately its hold current.