Transistor As Amplifier Patents (Class 257/159)
  • Patent number: 8941765
    Abstract: An imaging device includes a plurality of first pixels, each of which outputs a first pixel signal, a plurality of second pixels, each of which outputs a second pixel signal, a ramp wave generator that outputs a ramp signal that monotonously increases or monotonously decreases over time, a phase shift pulse generator that outputs first to n-th phase shift pulse signals, a first pixel latch group that latches the first to n-th phase shift pulse signals when the first pixel signal and the ramp signal have a predetermined relationship, a second pixel latch group that latches the first to n-th phase shift pulse signals when the second pixel signal and the ramp signal have the predetermined relationship, first to n-th power source lines to supply a power source and first to n-th phase shift pulse supply lines to supply the phase shift pulses.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: January 27, 2015
    Assignee: Olympus Corporation
    Inventor: Masashi Saito
  • Patent number: 8675107
    Abstract: Each pixel has a photoelectric conversion unit configured to convert light into electrical charges and to store the electrical charges, an amplifying unit configured to amplify a signal based on the electrical charges stored in the photoelectric conversion unit and to output the signal to an output line, and a reset unit configured to reset a input part of the amplifying unit. A clip unit, which is configured to limit an electric voltage of the output line, includes an amplifying circuitry for amplifying a signal based on the electric voltage of the output line and an MOS transistor for limiting the electric voltage of the output line based on the difference in electric potential between the gate and source. The clip unit controls the electric potential of the gate of the MOS transistor by the amplifying circuitry.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: March 18, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yuichiro Yamashita, Satoshi Kato, Toshiaki Ono, Hidekazu Takahashi
  • Patent number: 8637898
    Abstract: Embodiments of circuits, methods and systems for a voltage-controlled current source are disclosed. In some embodiments, the voltage-controlled current source may be a three-terminal device having separated gate structures. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: January 28, 2014
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: Haoyang Yu
  • Patent number: 8610237
    Abstract: A semiconductor apparatus includes a semiconductor chip, a lead frame that has a first surface having the semiconductor chip mounted thereover and a second surface opposite to the first surface, a bonding wire that couples the semiconductor chip and the lead frame, and a high dielectric constant layer that is disposed over a surface of the lead frame opposite to a surface having the semiconductor chip mounted thereover and that has a relative permittivity of 5 or more. The lead frame includes a source electrode lead coupled to the source of a semiconductor device formed over the semiconductor chip and a source-wire junction at which the source electrode lead and the bonding wire are coupled together. The high dielectric layer is disposed in a region including at least a position corresponding to the source-wire junction over the second surface of the lead frame.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: December 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Naoki Sakura
  • Patent number: 8482552
    Abstract: A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Gerhard Schrom, Peter Hazucha, Vivek De, Tanay Karnik
  • Patent number: 8134548
    Abstract: A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: March 13, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Gerhard Schrom, Peter Hazucha, Vivek De, Tanay Karnik
  • Patent number: 8093954
    Abstract: A high-frequency input circuit. The input circuit includes an input node, a bond pad, and a signal conversion resistor coupled in series between the input node and the bond pad to convert substantially all of a signal voltage at the input node to a signal current at the bond pad.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: January 10, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventor: Carel J. Lombaard
  • Patent number: 8080831
    Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: December 20, 2011
    Assignees: Renesas Electronics Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Fumitaka Nakayama, Masatoshi Morikawa, Yutaka Hoshino, Tetsuo Uchiyama
  • Patent number: 7990452
    Abstract: Various embodiments comprise apparatus, methods, and systems that include an amplification apparatus comprising a first input, a second input, and an output, a first plurality of series-connected transistors including a first transistor having a first channel ratio and a first gate coupled to the first input, and a second plurality of series-connected transistors including a second transistor having a second channel ratio that is greater than the first channel ratio, the second transistor including a second gate coupled to the second input.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: August 2, 2011
    Assignee: Aptina Imaging Corporation
    Inventor: Hai Yan
  • Patent number: 7842988
    Abstract: A noise generated by a constitution of widening an incident aperture of light of a photoelectric conversion element is reduced. In a manufacturing method of a photoelectric conversion device, first electroconductor arranged in a first hole arranged in the first interlayer insulation layer electrically connects a first semiconductor region to a gate electrode of an amplifying MOS transistor not through wirings included in a wiring layer. Moreover, a second electroconductor electrically connects a second semiconductor region different from the first semiconductor region to a wiring. In a constitution of that second electroconductor, a third electroconductor arranged in a second hole arranged in the first interlayer insulation layer and a fourth electroconductor arranged in a third hole arranged in the second interlayer insulation layer are stacked and electrically connected to each other.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: November 30, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takashi Okagawa, Hiroaki Naruse, Hiroshi Yuzurihara, Shigeru Nishimura, Takeshi Aoki, Yuya Fujino
  • Patent number: 7817199
    Abstract: Each pixel has a photoelectric conversion unit configured to convert light into electrical charges and to store the electrical charges, an amplifying unit configured to amplify a signal based on the electrical charges stored in the photoelectric conversion unit and to output the signal to an output line, and a reset unit configured to reset a input part of the amplifying unit. A clip unit, which is configured to limit an electric voltage of the output line, includes an amplifying circuitry for amplifying a signal based on the electric voltage of the output line and an MOS transistor for limiting the electric voltage of the output line based on the difference in electric potential between the gate and source. The clip unit controls the electric potential of the gate of the MOS transistor by the amplifying circuitry.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: October 19, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yuichiro Yamashita, Satoshi Kato, Toshiaki Ono, Hidekazu Takahashi
  • Patent number: 7741656
    Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: June 22, 2010
    Assignees: Renesas Technology Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Fumitaka Nakayama, Masatoshi Morikawa, Yutaka Hoshino, Tetsuo Uchiyama
  • Patent number: 7714354
    Abstract: A method is provided for electroforming metal integrated circuit structures. The method comprises: forming an opening such as a via or line through an interlevel insulator, exposing a substrate surface; forming a base layer overlying the interlevel insulator and substrate surface; forming a strike layer overlying the base layer; forming a top layer overlying the strike layer; selectively etching to remove the top layer overlying the substrate surface, exposing a strike layer surface; and, electroforming a metal structure overlying the strike layer surface. The electroformed metal structure is deposited using an electroplating or electroless deposition process. Typically, the metal is Cu, Au, Ir, Ru, Rh, Pd, Os, Pt, or Ag. The base, strike, and top layers can be deposited using physical vapor deposition (PVD), evaporation, reactive sputtering, or metal organic chemical vapor deposition (MOCVD).
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: May 11, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: David R. Evans, John W. Hartzell
  • Patent number: 7671381
    Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: March 2, 2010
    Assignees: Renesas Eastern Japan Semiconductor, Inc., Renesas Technology Corporation
    Inventors: Fumitaka Nakayama, Masatoshi Morikawa, Yutaka Hoshino, Tetsuo Uchiyama
  • Patent number: 7453104
    Abstract: In an operational amplifier including first and second power supply terminals, first and second input terminals, and a first and second output terminals, a first differential amplifier circuit includes first and second MOS transistors with a common source connected to a first tail current source, first and second load resistors and a first non-doped MOS transistor connected between the first and second resistors and the second power supply terminal. A second differential amplifier circuit includes third and fourth MOS transistors with a common source connected to a second tail current source, third and fourth load resistors and a second non-doped MOS transistor connected between the third and fourth load resistors and the second power supply terminal.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: November 18, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Toshiyuki Etoh
  • Patent number: 7312482
    Abstract: The present invention is directed to improve high frequency characteristics by reducing inductance of a source. In an HEMT assembled in a power amplifier device, each of a drain electrode, a source electrode, and a gate electrode is constructed by a base portion and a plurality of fingers projected in a comb-teeth shape from the base portion, and the fingers of the electrodes mesh with each other. In the source electrode, a width of the fingers positioned at both ends of the plurality of fingers is wider than a width of each of the fingers positioned between both ends. The width of each of the fingers positioned at both ends is a width equal to or larger than a sum of the widths of the plurality of fingers positioned between both ends, and the width of the base portion is wider than that of each of the fingers positioned at both ends. An electrode pad provided for the source base portion and an external electrode terminal are connected to each other via a conductive wire.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: December 25, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Akishige Nakajima, Hidenori Suenaga, Eigo Tange
  • Patent number: 7224232
    Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: May 29, 2007
    Assignee: Silicon Laboratories Inc.
    Inventors: Susanne A. Paul, Timothy J. Dupuis, John Blake Pavelka
  • Patent number: 6730945
    Abstract: Three or more MESFETs are fabricated side by side on a semiconductor chip. A transmission line substantially identical in width with an area within which the MESFETS are fabricated is formed in parallel with the row of MESFETs. The MESFETs are connected to the transmission line at a side, constituting one edge of the transmission line. Further, regulation circuits are connected in shunt with the transmission line, and outputs of the MESFESTS are merged while being matched by the transmission line and the regulation circuits.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: May 4, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shin Chaki
  • Publication number: 20040075104
    Abstract: A semiconductor integrated circuit is composed of a memory array, sense amplifiers, a first and second drive circuits, and a sense amplifier control circuit. The memory cell array has memory cells arranged in matrix form. The sense amplifiers amplify a signal read from the memory cells. The sense amplifiers include N channel sense amplifiers each composed of an N channel MOS transistor and P channel sense amplifiers each composed of a P channel MOS transistor. The first and second drive circuits each include an N channel MOS transistor that drives the N channel sense amplifiers or the P channel sense amplifiers, respectively. The first and second drive circuits are arranged adjacent to the sense amplifiers. The sense amplifier control circuit supplies a common control signal to both gate electrodes of the N channel MOS transistors included in the first and second drive circuits.
    Type: Application
    Filed: September 22, 2003
    Publication date: April 22, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takahiko Hara, Masahiro Yoshihara
  • Publication number: 20030213972
    Abstract: A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV=2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV=0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively.
    Type: Application
    Filed: November 5, 2002
    Publication date: November 20, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuichiro Ichiguchi, Tsutomu Nagasawa, Tadaaki Yamauchi, Zengcheng Tian, Makoto Suwa, Junko Matsumoto, Takeo Okamoto, Hideki Yonetani
  • Patent number: 6593600
    Abstract: A monolithic bidirectional switch formed in a semiconductor substrate of type N, including a first main vertical thyristor, the rear surface layer of which is of type P, a second main vertical thyristor, the rear surface layer of which is of type N, an auxiliary vertical thyristor, the rear surface layer of which is of type P and is common with that of the first main thyristor, a peripheral region of type P especially connecting the rear surface layer of the auxiliary thyristor to the layer of this thyristor located on the other side of the substrate, a first metallization on the rear surface side, a second metallization on the front surface side connecting the front surface layers of the first and second thyristors. An additional region has a function of isolating the rear surface of the auxiliary thyristor and the first metallization.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: July 15, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Franck Duclos, Jean-Michel Simonnet, Olivier Ladiray
  • Publication number: 20030057436
    Abstract: Three or more MESFETs are fabricated side by side on a semiconductor chip. A transmission line substantially identical in width with an are a within which the MESFETS are fabricated is formed in parallel with the row of MESFETs. The MESFETs are connected to the transmission line by way of a side constituting one edge of the transmission line. Further, regulation circuits are connected in shunt with the transmission line, whereby outputs are merged while being matched by means of the transmission line and the regulation circuits.
    Type: Application
    Filed: July 15, 2002
    Publication date: March 27, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shin Chaki
  • Publication number: 20020005525
    Abstract: A semiconductor device comprising a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.
    Type: Application
    Filed: May 24, 2001
    Publication date: January 17, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Hiroyuki Takazawa, Tohru Oka, Isao Ohbu, Yoshinori Imamura
  • Publication number: 20010040241
    Abstract: A sensor 1 produces an output that changes linearly with absolute temperature. In response to the output, a reference voltage generator 13 produces reference voltages Vhigh and Vlow that change linearly with absolute temperature. A Schmidt trigger 14 compares the output signal from a sensor signal amplifier 12 with the reference voltages for performing on-off output. A sensor signal amplifier 12 with a temperature-independent amplification factor amplifies the output signal from the sensor 1 while performing offset compensation. A sensor signal processing circuit 2 is formed out of thin-film silicon disposed on an insulating substrate. The output from the sensor 1 undergoes accurate temperature compensation over a wide temperature range from a low temperature to a high temperature, achieving a reliable operation with accuracy at high temperature.
    Type: Application
    Filed: June 14, 2001
    Publication date: November 15, 2001
    Inventors: Shuichi Nagano, Horst-Lothar Fiedler
  • Patent number: 6271540
    Abstract: The present invention provides a thin film transistor (TFT) and a fabrication method thereof which suppresses the back channel effects in which a leakage current flows between a source electrode and a drain electrode at times during a turn off state of the TFT. A thin silicon oxynitride film 90 having a thickness preferably equal to or less than 50 Å is formed between an amorphous silicon layer 40 and a channel passivation film 50 (a silicon nitride film) above a back channel region 100 between a source electrode and a drain electrode of an inverted staggered type TFT to cause Si—O bonds to exist in an upper interface of the amorphous silicon layer. The Si—O bonds increase the Density of States in the back channel region and has an effect for suppressing the leakage current through the back channel region 100 at times during the turn off of the TFT.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: August 7, 2001
    Assignee: International Business Machines Corporation
    Inventors: Takashi Miyamoto, Takatoshi Tsujimura
  • Patent number: 5998812
    Abstract: An amplifying-gate thyristor having an increased integrated circuit includes a main thyristor and an amplifying thyristor. The amplifying thyristor is of the gate turnoff-type. The main thyristor and the amplifying thyristor are such that the amplifying thyristor remains in the conductive state while the main thyristor is conductive. A control circuit turns off the amplifying thyristor when the current through the main thyristor is approximately its hold current.
    Type: Grant
    Filed: January 19, 1998
    Date of Patent: December 7, 1999
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Eric Bernier, Denis Berthiot