Surface Feature (e.g., Guard Ring, Groove, Mesa, Etc.) Patents (Class 257/170)
  • Patent number: 11114526
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. The semiconductor substrate includes a first semiconductor region of a second conductivity type at a surface thereof, a second semiconductor region of the second conductivity type at the surface and surrounding the first semiconductor region, a third semiconductor region of the second conductivity type provided in the second semiconductor region at the surface and surrounding the first semiconductor region. The third semiconductor region has a concentration of a second conductivity type impurity higher than that of the second semiconductor region. A first insulating film is provided on a part of the first surface at which the second semiconductor region is provided. the first insulating film having an opening that exposes. A first electrode is provided on the first insulating film and electrically connected to the third semiconductor region via the opening.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: September 7, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenichi Matsushita
  • Patent number: 11056603
    Abstract: Resonant cavity photodetector structures which integrate photodetection and filtering capabilities is described. A resonant cavity photodetector structure generally can comprise a region including a resonator, and an absorption region that can be integrated into a cavity of the resonator. The resonator can perform filtering that is suitable for high-bandwidth optical communications, such as Dense Wavelength Multiplexing (DWDM). In some cases, the resonator is a microring resonator. An absorption region can include a photodiode which performs optical energy detection acting as a photodetector, such as an avalanche photodiode (APD) wherein the photodiode. A coupling distance between the resonator region and the absorption region can be controlled, which allows control of a coupling strength between an optical mode of the resonator and the absorption region such that a quality factor (Q-factor) can be tuned.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: July 6, 2021
    Inventors: Zhihong Huang, Xiaoge Zeng, Wayne Victor Sorin
  • Patent number: 10879348
    Abstract: The present disclosure relates to a semiconductor device and an electronic apparatus that make it possible to provide a higher voltage resistance. An outer-peripheral structure region is provided in an n-type well on a surface of a semiconductor substrate, the outer-peripheral structure region being arranged to surround an outer periphery of a region in which a plurality of semiconductor elements is formed. Further, an anode is arranged in an innermost in the outer-peripheral structure region, and a plurality of guard rings is multiply arranged on an outside of the anode. Furthermore, a field plate covering the anode and a field plate covering a guard ring adjacent to the anode are formed to be electrically connected to each other so as to be combined. The present technology is applicable to, for example, various semiconductor devices.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 29, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Takaaki Tatsumi
  • Patent number: 10546795
    Abstract: The present application relates to a power semiconductor device, including a substrate having a first side and a second side, the first side and the second side being located opposite to each other, wherein the first side includes a cathode and the second side includes an anode, wherein a junction termination of a p/n-junction is provided at at least one surface of the substrate, preferably at at least one of the first side and the second side, the junction termination is coated by a passivating coating, the passivating coating including at least one material selected from the group consisting of an inorganic-organic composite material, parylene, and a phenol resin comprising polymeric particles.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: January 28, 2020
    Assignee: ABB Schweiz AG
    Inventors: Lise Donzel, Juergen Schuderer, Jagoda Dobrzynska, Jan Vobecky
  • Patent number: 10546780
    Abstract: An example integrated circuit die includes: a plurality of lower level conductor layers, a plurality of lower level insulator layers between the plurality of lower level conductor layers, a plurality of lower level vias extending vertically through the lower level insulator layers, a plurality of upper level conductor layers overlying the lower level conductor layers, a plurality of upper level insulator layers between and surrounding the upper level conductor layers, a plurality of upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: January 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Subhashish Mukherjee, Raja Selvaraj, Venugopal Gopinathan
  • Patent number: 10505033
    Abstract: An electronic device is integrated on a chip of semiconductor material having a main surface and a substrate region with a first type of conductivity. The electronic device has a vertical MOS transistor, formed in an active area having a body region with a second conductivity type.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Angelo Magrí, Giacomo Barletta
  • Patent number: 10438905
    Abstract: Apparatuses and methods for providing inductance are disclosed. In one embodiment, a method for providing an inductor includes forming an electrical circuit on a substrate, forming a seal ring around the perimeter of the electrical circuit, providing a break in at least one layer of the seal ring, and electrically connecting the seal ring such that the seal ring operates as an inductor.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 8, 2019
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Fikret Altunkilic, Haki Cebi
  • Patent number: 10347713
    Abstract: A semiconductor device according to an embodiment includes a semiconductor layer having first and second planes; first and second electrodes; a first semiconductor region of a first conductivity type in the semiconductor layer; a second semiconductor region of a second conductivity type between the first semiconductor region and the first plane; and a third semiconductor region of the second conductivity type surrounding the second semiconductor region. The third semiconductor region includes a first region, a second region, and a third region. A first region, a second region, and a third region are closer to the second semiconductor region in this order. An amount of second-conductivity-type impurities in the first region, the second region, and the third region is less than that of the second semiconductor region. An amount of second-conductivity-type impurities in the second region is higher than that in the first region and the third region.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: July 9, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Tomohiro Tamaki
  • Patent number: 10134798
    Abstract: An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: November 20, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 10103242
    Abstract: In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the <111> direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: October 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sanghoon Lee, Effendi Leobandung, Renee Mo, Brent A. Wacaser
  • Patent number: 10074974
    Abstract: An arrangement for protecting an electrical facility from overvoltages having an overcurrent protection facility arranged in a first series circuit and a shunt circuit arranged between the overcurrent protection facility and the electrical facility to be protected, the shunt series resulting in a second series circuit, wherein a diode for discharging transient overvoltages is arranged in the shunt circuit, which is conductive if a voltage threshold is exceeded, as a result of which the current resulting from the overvoltage can be passed through the shunt circuit to the facility to be protected into the second shunt circuit, where a first inductor is arranged in a series connection to the diode, the diode is connected here to a first diode terminal on the first series circuit and is connected to a second diode terminal on the first inductor, and where the overcurrent protection facility is not triggered prematurely by temporary overvoltages.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: September 11, 2018
    Assignee: Siemens Aktiengesellschaft
    Inventor: Dirk Prochaska
  • Patent number: 10069000
    Abstract: The invention relates to a bipolar non-punch-through power semiconductor device and a corresponding manufacturing method. The device comprises a semiconductor wafer and a first electrode formed on a first main side of the wafer and a second electrode formed on a second main side of the wafer opposite the first main side. The wafer comprises a pair of layers of different conductivity types, such as a drift layer of a first conductivity type, and a first layer of a second conductivity type arranged on the drift layer towards the first main side and contacting the first electrode. The wafer comprises an inner region wand an outer region surrounding the inner region. The drift layer has a thickness in the inner region greater or equal than a thickness in the outer region. A thickness of the first layer increases in a transition region between the inner region and the outer region from a thickness in the inner region to a maximum thickness in the outer region.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: September 4, 2018
    Assignee: ABB Schweiz AG
    Inventors: Virgiliu Botan, Jan Vobecky, Karlheinz Stiegler
  • Patent number: 10068870
    Abstract: A semiconductor device includes a plurality of semiconductor units each including a laminated substrate formed by laminating an insulating board and a circuit board and a semiconductor element joined to the circuit board using a joining material which irreversibly makes a phase transition into a solid-phase state. In addition, the semiconductor device may include a base plate to which each of the plurality of semiconductor units is joined using solder and a connection unit which electrically connects the plurality of semiconductor units in parallel.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 4, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Norihiro Nashida, Hideyo Nakamura, Yoko Nakamura
  • Patent number: 10056501
    Abstract: Provided is a device with improved reverse-recovery immunity of a diode element. The device includes: a first conductivity-type drift layer; a second conductivity-type anode region provided in an upper portion of the drift layer; a second conductivity-type extraction region in contact with and surrounding the anode region; and a second conductivity-type field limiting ring region surrounding and separated from the extraction region at the upper portion of the drift layer, wherein the extraction region has a greater depth than the anode region and the field limiting ring region.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: August 21, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Mitsuhiro Kakefu
  • Patent number: 9994936
    Abstract: Embodiments described herein provide processes for forming and removing epitaxial films and materials from growth wafers by epitaxial lift off (ELO) processes. In some embodiments, the growth wafer has edge surfaces with an off-axis orientation which is utilized during the ELO process. The off-axis orientation of the edge surface provides an additional variable for controlling the etch rate during the ELO process- and therefore the etch front may be modulated to prevent the formation of high stress points which reduces or prevents stressing and cracking the epitaxial film stack. In one embodiment, the growth wafer is rectangular and has an edge surface with an off-axis orientation rotated by an angle greater than 0° and up to 90° relative to an edge orientation of <110> at 0°.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: June 12, 2018
    Assignee: Alta Devices, Inc.
    Inventors: Thomas Gmitter, Gang He, Melissa Archer, Siew Neo
  • Patent number: 9859383
    Abstract: A semiconductor component includes a semiconductor body of a first conduction type and a metal layer on the semiconductor body, wherein the metal layer forms with the semiconductor body a Schottky contact along a contact surface. A doping concentration of the first conduction type on the contact surface varies along a direction of the contact surface.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: January 2, 2018
    Assignee: Infineon Technologies AG
    Inventors: Jens Peter Konrath, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 9824985
    Abstract: A semiconductor device is provided. The semiconductor device includes a seal ring and a noise-absorbing circuit. The noise-absorbing circuit is electrically connected between the seal ring and a ground pad. The noise-absorbing circuit includes at least one capacitor and at least one inductor to form a first noise-absorbing path, a second noise-absorbing path and a third noise-absorbing path.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shuo-Chun Chou, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang
  • Patent number: 9741872
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region. The first semiconductor region is provided between the first and second electrodes. The second semiconductor region is provided between the first semiconductor region and the second electrode. The third semiconductor region is provided between the first semiconductor region and the second electrode, is provided beside the second semiconductor region in a second direction crossing a first direction from the first electrode toward the second electrode, and a portion of the first semiconductor region is positioned between the third and second semiconductor regions. The fourth semiconductor region is provided between the portion of the first semiconductor region and the second electrode and has a greater impurity concentration than the second and third semiconductor regions.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: August 22, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Tomoko Matsudai
  • Patent number: 9728638
    Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 8, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jin-Ku Lee, Young-Ho Lee, Mi-Ri Lee
  • Patent number: 9627430
    Abstract: A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chun-Chieh Chuang, Shuang-Ji Tsai, Jeng-Shyan Lin
  • Patent number: 9621058
    Abstract: A synchronous rectifier is described that includes a transistor device that has a gate terminal, a source terminal, a drain terminal, and a field-plate electrode. The field-plate electrode of the transistor device includes an integrated diode. The integrated diode is configured to discharge a parasitic capacitance of the transistor device during each switching operation of the synchronous rectifier. In some examples, the integrated diode is also configured to charge the parasitic capacitance of the transistor device during each switching operation of the synchronous rectifier.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Cesar Augusto Braz, David Laforet
  • Patent number: 9515594
    Abstract: A wind turbine comprises a wind rotor, a generator driven by the wind rotor, a converter, wherein the generator and the converter generate electrical energy output via a connecting line with an inductively acting line reactor to a grid, and an overvoltage protection device comprising a plurality of different active modules, which are designed in such a way that they each effect, in different ways, a reduction in the voltage at the output of the converter, a switching matrix, which connects and disconnects the different active modules, and a selector comprising an overvoltage classifier, which is designed to select a predetermined stage depending on the overvoltage and to actuate the switching matrix in such a way that successive ones of the active modules are disconnected, wherein the overvoltage classifier defines a plurality of overvoltage ranges by virtue of in each case the selector setting different switching groups.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: December 6, 2016
    Assignee: SENVION SE
    Inventors: Heinz-Hermann Letas, Steffen Pingel
  • Patent number: 9496231
    Abstract: An integrated circuit (IC) comprises a plurality of metal layers; a seal ring arranged around a perimeter of the IC and included in at least a portion of the plurality of metal layers; a first coil included in the IC; and a bypass conductor included in at least one metal layer of the plurality of metal layers and having at least a first end and a second end electrically coupled to the seal ring to form a bypass ring around the first coil.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: November 15, 2016
    Assignee: Intel IP Corporation
    Inventors: Chi-Taou Robert Tsai, Curtiss D. Roberts, Lillian G. Lent
  • Patent number: 9484404
    Abstract: An electronic device is integrated on a chip of semiconductor material having a main surface and a substrate region with a first type of conductivity. The electronic device has a vertical MOS transistor, formed in an active area having a body region with a second conductivity type.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: November 1, 2016
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Giacomo Barletta, Angelo Magrí
  • Patent number: 9455355
    Abstract: An n?-type semiconductor substrate (1) includes an active region and a terminal region disposed outside the active region. A p+-type anode layer (2) is formed in a portion of an upper surface of the n?-type semiconductor substrate (1) in the active region. A plurality of p+-type guard ring layers (3) are formed in a portion of the upper surface of the n?-type semiconductor substrate (1) in the terminal region. An n+-type cathode layer (5) is formed in a lower surface of the n?-type semiconductor substrate (1). An anode electrode (6) is connected to the p+-type anode layer (2). A metallic cathode electrode (7) is connected to the n+-type cathode layer (5). A recess (8) is formed by trenching the n+-type cathode layer (5) in the terminal region. The cathode electrode (7) is also formed in the recess (8).
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: September 27, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Eiko Otsuki, Koji Sadamatsu, Yasuhiro Yoshiura
  • Patent number: 9385183
    Abstract: The termination region includes a ring region (LNFLR). A plurality of ring-shaped P-type ring layers are regularly arranged in the ring region (LNFLR). The ring region (LNFLR) is divided into a plurality of units which include the plurality of P-type ring layers respectively. A width of each unit is constant. A total number of P-type impurities in the ring region (LNFLR) is N, the target withstand voltage is BV [V], a width of each unit is SandL [?m], and the number of the plurality of units is num, following relationships are satisfied. N?(M×BV)?, M=104 to 105, ?=0.55 to 1.95, SandL×num×Ecri?2×?×BV, Ecri=2.0 to 3.0×105 [V/cm], ?=100 to 101. Widths of the P-type ring layers of the plurality of units linearly decrease toward an outside of the termination region.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: July 5, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Ze Chen, Tsuyoshi Kawakami, Katsumi Nakamura
  • Patent number: 9384983
    Abstract: A method for producing a vertical semiconductor device includes providing a semiconductor substrate having a first surface and comprising an n-doped first semiconductor layer, forming a hard mask on the first surface, the hard mask comprising openings defining first zones in the n-doped first semiconductor layer, implanting acceptor ions of a first maximum energy through the hard mask into the first zones, replacing the hard mask by an inverted mask comprising openings that are substantially complementary to the openings of the hard mask; implanting acceptor ions of a second maximum energy different to the first maximum energy through the inverted mask into second zones of the n-doped first semiconductor layer, and carrying out at least one temperature step to activate the acceptor ions in the first zones and the second zones.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: July 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Jens Peter Konrath
  • Patent number: 9263575
    Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: February 16, 2016
    Assignee: SK Hynix Inc.
    Inventors: Jin-Ku Lee, Young-Ho Lee, Mi-Ri Lee
  • Patent number: 9041143
    Abstract: The semiconductor device includes a first semiconductor layer of the first conductive type, a second semiconductor layer having the cubic crystalline structure formed on the first semiconductor layer, an electrode formed on the second semiconductor layer, and a reactive region formed between the second semiconductor layer and the electrode. The second semiconductor layer includes an upper surface that is tilted from the (100) plane. The reactive region includes at least one element constituting the second semiconductor layer, at least one element constituting the electrode, and forming a protuberance extending toward the second semiconductor layer.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukie Nishikawa, Nobuhiro Takahashi, Hironobu Shibata
  • Patent number: 9029980
    Abstract: A semiconductor device includes a semiconductor substrate, an element isolating trench structure that includes an element isolating trench formed in one main surface of the semiconductor substrate, an insulating material that is formed within the element isolating trench, element formation regions that are surrounded by the element isolating trench, and semiconductor elements that are respectively formed in the element formation regions. The element isolating trench includes first element isolating trenches extending in a first direction, second element isolating trenches extending in a second direction that are at a right angle to the first direction, and third element isolating trenches extending in a third direction inclined at an angle ? (0°<?<90°) from the first direction.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: May 12, 2015
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventors: Takao Kaji, Katsuhito Sasaki, Takaaki Kodaira, Yuuki Doi, Minako Oritsu
  • Patent number: 8994066
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: March 31, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Kenichi Yoshimochi
  • Patent number: 8963212
    Abstract: In one general aspsect, a semiconductor device can include at least a first device region and a second device region disposed at a surface of a semiconductor region where the second device region is adjacent to the first device region and spaced apart from the first device region. That semiconductor device can include a connection region disposed between the first device region and the second device region, and a trench extending into the semiconductor region and at least extending from the first device region, through the connection region, and to the second device region. The semiconductor device can include a dielectric layer lining opposing sidewalls of the trench, an electrode disposed in the trench, and a conductive trace disposed over a portion of the trench in the connection region and electrically coupled to a portion of the electrode disposed in the connection region.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: February 24, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Ashok Challa, Daniel M. Kinzer, Dean E. Probst, Daniel Calafut
  • Patent number: 8921943
    Abstract: Methods and apparatus for ESD structures. A semiconductor device includes a first active area containing an ESD cell coupled to a first terminal and disposed in a well; a second active area in the semiconductor substrate, the second active area comprising a first diffusion of the first conductivity type for making a bulk contact to the well; and a third active area in the semiconductor substrate, separated from the first and second active areas by another isolation region, a portion of the third active area comprising an implant diffusion of the first conductivity type within a first diffusion of the second conductivity type and adjacent a boundary with the well of the first conductivity type; wherein the third active area comprises a diode coupled to the terminal and reverse biased with respect to the well of the first conductivity type.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ying Hsu, Tzu-Heng Chang, Jen-Chou Tseng, Ming-Hsiang Song, Johannes Van Zwol, Taede Smedes
  • Patent number: 8901604
    Abstract: Semiconductor devices with guard rings are described. The semiconductor devices may be, e.g., transistors and diodes designed for high-voltage applications. A guard ring is a floating electrode formed of electrically conducting material above a semiconductor material layer. A portion of an insulating layer is between at least a portion of the guard ring and the semiconductor material layer. A guard ring may be located, for example, on a transistor between a gate and a drain electrode. A semiconductor device may have one or more guard rings.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: December 2, 2014
    Assignee: Transphorm Inc.
    Inventors: Umesh Mishra, Srabanti Chowdhury, Yuvaraj Dora
  • Patent number: 8878236
    Abstract: In a first embodiment, an ultra-fast breakover diode has a turn on time TON that is less than 0.3 microseconds, where the forward breakover voltage is greater than +400 volts and varies less than one percent per ten degrees Celsius change. In a second embodiment, a breakover diode has a reverse breakdown voltage that is greater, in absolute magnitude, than the forward breakover voltage, where the forward breakover voltage is greater than +400 volts. In a third embodiment, a string of series-connected breakover diode dice is provided, along with a resistor string, in a packaged circuit. The packaged circuit acts like a single breakover diode having a large forward breakover voltage and a comparably large reverse breakdown voltage, even though the packaged circuit includes no discrete high voltage reverse breakdown diode. The packaged circuit is usable to supply a triggering current to a thyristor in a voltage protection circuit.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: November 4, 2014
    Assignee: IXYS Corporation
    Inventor: Subhas Chandra Bose Jayappa Veeramma
  • Patent number: 8847278
    Abstract: A semiconductor device includes an active section for a main current flow and a breakdown withstanding section for breakdown voltage. An external peripheral portion surrounds the active section on one major surface of an n-type semiconductor substrate. The breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring. The ring-shaped semiconductor protrusion has a p-type region therein, is sandwiched between a plurality of concavities deeper than the p-type region, and has an electrically conductive film across an insulator film on the surface thereof. Because of this, it is possible to manufacture at low cost a breakdown withstanding structure with which a high breakdown voltage is obtained in a narrow width, wherein there is little drop in breakdown voltage, even when there are variations in a patterning process of a field oxide film.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: September 30, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Manabu Takei, Yusuke Kobayashi
  • Patent number: 8829568
    Abstract: An insulating layer, an undoped first GaN layer and an AlGaN layer are laminated in this order on a surface of a semiconductor substrate. A surface barrier layer formed by a two-dimensional electron gas is provided in an interface between the first GaN layer and the AlGaN layer. A recess (first recess) which reaches the first GaN layer but does not pierce the first GaN layer is formed in a surface layer of the AlGaN layer. A first high withstand voltage transistor and a control circuit are formed integrally on the aforementioned semiconductor substrate. The first high withstand voltage transistor is formed in the first recess and on a surface of the AlGaN layer. The control circuit includes an n-channel MOSFET formed in part of the first recess, and a depression type n-channel MOSFET formed on a surface of the AlGaN layer.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: September 9, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Katsunori Ueno
  • Patent number: 8809961
    Abstract: An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Che Tsai, Jam-Wem Lee, Yi-Feng Chang
  • Patent number: 8779555
    Abstract: The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Long-Shih Lin, Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Po-Tao Chu
  • Patent number: 8772092
    Abstract: A method for forming an integrated circuit. The method includes forming a first guard ring around at least one transistor over a substrate, the first guard ring having a first type dopant. The method further includes forming a second guard ring around the first guard ring, the second guard ring having a second type dopant. The method includes forming a first doped region adjacent to the first guard ring, the first doped region having the second type dopant. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having the first type dopant, wherein the first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: July 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Song Sheu, Jian-Hsing Lee, Yu-Chang Jong, Chun-Chien Tsai
  • Patent number: 8772827
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: July 8, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Kenichi Yoshimochi
  • Patent number: 8742500
    Abstract: A semiconductor device is disclosed wherein a peripheral region with a high breakdown voltage and high robustness against induced surface charge is manufactured using a process with high mass productivity. The device has n-type drift region and p-type partition region of layer-shape deposited in a vertical direction to one main surface of n-type semiconductor substrate with high impurity concentration form as drift layer, alternately adjacent parallel pn layers in a direction along one main surface. Active region through which current flows and peripheral region enclosing the active region include parallel pn layers.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: June 3, 2014
    Assignee: Fuji Electric Co., Ltd
    Inventor: Yasuhiko Onishi
  • Patent number: 8742456
    Abstract: An integrated trench-MOS-controlled-thyristor plus trench gated diode combination, in which the trenches are preferably formed at the same time. A backside polarity reversal process permits a backside p+ region in the thyristor areas, and only a backside n+ region in the diode areas (for an n-type device). This is particularly advantageous in motor control circuits and the like, where the antiparallel diode permits the thyristor to be dropped into existing power MOSFET circuit designs. In power conversion circuits, the antiparallel diode can conveniently serve as a freewheeling diode.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: June 3, 2014
    Assignee: Pakal Technologies LLC
    Inventors: Hidenori Akiyama, Richard A. Blanchard, Woytek Tworzydlo
  • Patent number: 8686508
    Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam, Robert Robison
  • Patent number: 8643146
    Abstract: A carrier is prevented from being stored in a guard ring region in a semiconductor device. The semiconductor device has an IGBT cell including a base region and an emitter region formed in an n? type drift layer, and a p type collector layer arranged under the drift layer with a buffer layer interposed therebetween. A guard ring region having a guard ring is arranged around the IGBT cell. A lower surface of the guard ring region has a mesa structure provided by removing the collector layer.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: February 4, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hitoshi Uemura
  • Patent number: 8643104
    Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: February 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Shan Liao, An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang
  • Patent number: 8633543
    Abstract: An electro-static discharge protection circuit includes: a PNPN junction, a P-type side of the PNPN junction being coupled to a terminal, an N-type side of the PNPN junction being coupled to ground; and a P-type metal oxide semiconductor transistor, a source and a gate of the P-type metal oxide semiconductor transistor being coupled to an N-type side of a PN junction whose P-type side coupled to the ground, and a drain of the P-type metal oxide semiconductor transistor being coupled to the terminal.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: January 21, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazutoshi Ohta, Kenji Hashimoto
  • Patent number: 8587071
    Abstract: An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Che Tsai, Jam-Wem Lee, Yi-Feng Chang
  • Patent number: 8587023
    Abstract: A guard ring system is disclosed for protecting an integrated circuit comprising. It has a first guard ring area formed by a well in the substrate, a capacitor area formed within the first guard ring area which further includes two well contacts formed into the well and biased by a first supply voltage, and a dielectric layer placed between the two contacts on the well with its first side in contact with the well. A second supply voltage complementary to the first supply voltage is applied to a second side of the dielectric layer so that a voltage difference across the dielectric layer provides a local capacitance embedded therein.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Cheng Hung Lee
  • Patent number: 8564024
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: October 22, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Ashok Challa, Daniel M. Kinzer, Dean E. Probst