Abstract: A termination region of a semiconductor die is provided, which includes one or more field rings arranged in the termination region, one or more metal field plates, and an insulation layer disposed to prevent direct electrical contact between the field rings and the field plate such that the at least one field ring is capacitively coupled with the at least one field plate. Such a termination region may also include a polysilicon plate capacitively coupled with a diffusion region laterally spaced from the field rings, the polysilicon plate being located at an outer surface or directly under a passivation layer at an outer surface of the die. The termination region may also include floating field rings. The insulation layer may be a field oxide layer.

Abstract: A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process.

Abstract: A semiconductor device, including: a semiconductor substrate of the first conductivity type having a first surface and a second surface; a base region of the second conductivity type formed on the first surface of the semiconductor substrate; a guard ring region of the second conductivity type formed around the base region, and having the second type impurity of which concentration is lower than that of the base region; a first electrode formed on the base region; and a second electrode formed on the second surface of the semiconductor substrate, further including a base peripheral region formed around the base region and being connected to the base region, wherein the base peripheral region is deeper than the base region and has the substantially constant depth, and the concentration of the second conductivity type impurity included in the base peripheral region is lower than that included in the base region.

Abstract: The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement of the steady loss of the wide-gap bipolar semiconductor element corresponding to the decrement of the built-in voltage lowering depending on the temperature rising of the wide-gap bipolar semiconductor element is larger than the increment of the steady loss corresponding to the increment of the ON resistance increasing depending on the temperature rising.

Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.

Abstract: A method of avoiding substrate noise in an integrated circuit includes steps of receiving as input an integrated circuit design that includes at least a portion of a block for placement and routing on a substrate and an outer boundary of the block. An end cell is selected from a set of end cells for terminating the block in an outer area that extends from the outer boundary to an end cell boundary outside the block. The selected end cell is placed in the outer area to isolate the block electrically from the substrate.

Abstract: In a conventional semiconductor device, there was a problem that, in a guard ring region, a shape of a depletion layer is distorted and stable withstand voltage characteristics cannot be obtained. In a semiconductor device of the present invention, a thermal oxide film in an actual operation region and a thermal oxide film in a guard ring region are formed in the same process. Thereafter, the thermal oxide film is once removed and is formed again. Thus, a film thickness of the thermal oxide film on the upper surface of the guard ring region is set to, for example, about 8000 to 10000 ?. Accordingly, a CVD oxide film including moving ions is formed in a position distant from a surface of an epitaxial layer. Consequently, distortion of a depletion layer, which is influenced by the moving ions, is suppressed and desired withstand voltage characteristics can be maintained.

Abstract: A semiconductor device has a semiconductor device chip with upper and lower terminal electrodes, and upper and lower frames bonded to the upper and lower terminal electrodes, respectively, with solder material, wherein the semiconductor device chip includes: a semiconductor layer of a first conductivity type; a diffusion layer of a second conductivity type, which is selectively formed in the semiconductor layer; a plurality of guard-ring layers of the second conductivity type, which are formed outside of the diffusion layer in the semiconductor layer; an insulating film formed on the semiconductor layer; and a field plate formed of a poly-crystalline silicon film embedded in the insulating film.

Abstract: An ion-through region 100, 102 is provided as a first opening in a passivation film 90 on a source electrode 70 and a drain electrode 80. The passivation film 90 is coated with a sealing resin to package the semiconductor device. At this point, the ion-through region 100, 102 is filled with the sealing resin to put the sealing resin into direct contact with the source electrode 70 and the drain electrode 80. With this structure, movable ions accumulated at an interface of the sealing resin with the passivation film 90 in a high temperature and high humidity atmosphere are discharged to the source electrode 70 and the drain electrode 80 via the ion-through region 100, 102 and thus do not influence an N?-type extended drain region 30. Therefore, the drain breakdown voltage can be improved.

Abstract: A structure formed in a semiconductor substrate having at least one area having a high concentration of atoms of a metal such as platinum or gold, in which the area is surrounded with at least one first trench penetrating into the substrate.

Abstract: A retaining ring for use with electrochemical mechanical processing is described. The retaining ring has a generally annular body formed with a conductive portion and a non-conductive portion. The non-conductive portion contacts the substrate during polishing. The conductive portion is electrically biased during polishing to reduce the edge effect that tends to occur with conventional electrochemical mechanical processing systems.

Abstract: A trench transistor has a cell array, in which at least one cell array trench (2) is provided, and an edge structure framing the cell array. An edge trench (15) spaced apart from the cell array trenches (2) is provided in the edge structure.

Abstract: There is here disclosed a film forming ring including a ring main body being made of an insulating material and formed in an annular shape along an edge of a substrate on which a film forming process by using a material gas in a plasma state is applied, and an inner rim of the ring main body being formed higher than its outside portion.

Abstract: A silicon controlled rectifier is provided, including: a first conducting-type substrate; two second conducting-type deep wells separately disposed inside the first conducting-type substrate; a gate above the first conducting-type substrate and between the two second conducting-type deep wells; a first source/drain inside one of the two second conducting-type deep wells and at one side of the gate; a second source/drain inside the other of the two second conducting-type deep wells and at the other side of the gate; a first conducting-type doped region inside the first conducting-type substrate; and a first conducting-type doped floating region inside the one of the two second conducting-type deep wells and adjacent to the first source/drain. The first conducting-type doped floating region and the first source/drain constitute an equivalent Zener diode so that the modified silicon controlled rectifier can have a higher holding voltage.

Abstract: A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer such as a floating gate. A dummy stack ring is formed around the memory array. An insulating layer is formed over the memory array. The dummy stack ring has a composition and height substantially the same as a composition and height of the gate stack to insure that a CMP of the insulating layer is uniform across the memory array.

Abstract: A semiconductor device having improved breakdown voltage is provided. A diode device of the present invention includes relay diffusion layers provided between guard ring portions. Therefore, a depletion layer expanded outward from the guard ring portions except the outermost one reaches these relay diffusion layers, and then the outer guard ring portions. The width of the distance between the guard ring portions is shorter where the relay diffusion layers are provided. For the width of the relay diffusion layers, the depletion layer reaches the outer guard ring portions with a lower voltage than the conventional structure.

Abstract: The present invention is generally directed to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of making same. In one illustrative embodiment, an integrated circuit is provided that comprises a plurality of voltage supply structures formed above a substrate, the plurality of voltage supply structures being at differing voltage levels, and a guard band comprised of at least one doped region formed in the substrate under each of the plurality of voltage supply regions, each of the guard bands being comprised of a plurality of fingers extending from each end of the guard bands.

Abstract: In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel region (61). A doped gate region (59) is then formed on the sidewalls and the bottom surface of the second trench (34). Source regions (26) are formed on opposite sides of the double trench structure (28). Localized gate contact regions (79) couple individual doped gate regions (59) together. Contacts (84,85,87) are then formed to the localized gate contact regions (79), the source regions (26), and an opposing surface (21) of the body of semiconductor material (13). The structure provides a compound semiconductor vertical FET device (11, 41, 711, 712, 811, 812) having enhanced blocking capability and improved switching performance.

Abstract: An ESD protection circuit for low temperature poly-silicon thin film transistor panel and a display panel using the same. The feature of the ESD protection circuit comprises an ESD detection circuit disposed between a first power line and a second power line, for outputting an enable signal when an ESD event occurs in the first power line; and a discharge device having a control terminal coupled to the output of the ESD detection circuit, for providing a discharge path between the first and second power lines when the control terminal receives the enable signal.

Abstract: The present invention provides an optoelectronic device and a method of manufacture thereof. In one embodiment, the method of manufacturing the optoelectronic device may include creating a multilayered optical substrate and then forming a self aligned dual mask over the multilayered optical substrate. The method may further include etching the multilayered optical substrate through the self aligned dual mask to form a mesa structure.

Abstract: A substrate contact and semiconductor chip, and methods of forming the same. The substrate contact is employable with a semiconductor chip formed from a semiconductor substrate and includes a seal ring region about a periphery of an integrated circuit region. In one embodiment, the substrate contact includes a contact trench extending through a shallow trench isolation region and an insulator overlying the semiconductor substrate and outside the integrated circuit region. The contact trench is substantially filled with a conductive material thereby allowing the semiconductor substrate to be electrically connected with a metal interconnect within the seal ring region.

Abstract: A high withstand voltage semiconductor device does not show any significant fall of its withstand voltage if the impurity concentration of the RESURF layer of a low impurity concentration semiconductor region thereof varies from the optimal level and/or influenced by the fixed electric charge.

Abstract: In a power semiconductor component produced in a planar technique, a near-surface structure having at least one depression is formed in a surface region of an edge termination adjacent a main surface of the semiconductor body. The structure lies inside a space charge region formed when a voltage is applied at a junction between semiconductor regions of opposite conduction type. Dielectric material may fill the depression and form a passivation layer on the surface region. The depression may be an annular trench having a width to depth ratio ?1. Alternatively, the structure may be waffle-shaped with multiple depressions.

Abstract: A method to protect a low-K IMD layer underlying a fuse link during a fuse blowing process including a guarded fuse and method for forming the same including forming a fuse portion comprising two metal fuse interconnect structures and a guard ring comprising a metal interconnect structure surrounding the fuse portion in an uppermost IMD layer comprising a dielectric constant of less than about 3.2; forming a protective metal portion electrically isolated in the uppermost IMD layer to cover at least a portion of an area extending between the fuse portions; forming at least one overlying dielectric insulating layer over the uppermost layer to include extended portions of the fuse portion and the guard ring; and, forming a metal fuse link portion to electrically interconnect the fuse portion wherein the fuse portion overlies at least a portion of the protective metal portion.

Abstract: The invention concerns a vertical component with a four-layered structure comprising a thick lightly-doped zone (1) of a first type of conductivity providing the component voltage strength, enclosed with a peripheral wall (2) of a second type of conductivity extending vertically from one surface to the other of the component, and highly doped layer (3) of the second type of conductivity extending over the entire rear surface of the component. A lightly-doped layer (21) of the second type of conductivity extends over the entire surface of the component at the interface between the lightly-doped thick zone of the first type of conductivity and the highly-doped layer of the second type of conductivity.

Abstract: A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selected region and separate from the selected region; selectively forming at least one pattern on the selected region; and causing a re-flow of the pattern, wherein a part of an outwardly re-flowed pattern is flowed into the re-flow stopper groove, and then an outward re-flow of the pattern is restricted by the re-flow stopper groove extending outside of the pattern, thereby to form a deformed pattern with at least an outside edge part defined by an outside edge of the re-flow stopper groove.

Abstract: A semiconductor device has a guard ring in a multilayer interconnection structure, wherein the guard ring includes a conductive wall extending zigzag in a plane parallel with a principal surface of a substrate.

Abstract: The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106) generally surrounds the drain region (104). The source region (106) serves as both the source for the MOS device (100) and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region (110) generally surrounds the drain region (104) and is electrically insulated from the drain region (104) and electrically connected to the source region (106). An annular P-type bulk region (108) generally surrounds the source region (106) and is electrically connected to the source region (106).

Abstract: A semiconductor integrated circuit device has a semiconductor integrated circuit chip, a package enclosing the chip, and a plurality of conductors connecting the bonding pads of the chip to the leads of the package. The chip has an internal circuit, a plurality of bonding pads having signal paths formed between themselves and the internal circuit, and a switching circuit provided in a predetermined signal path so as to perform a switching operation to allow the internal circuit to be connected selectively to one of different bonding pads. The switching circuit is fed with an external signal to perform its switching operation in such a way as to prevent the signals passing through mutually adjacent conductors from affecting each other.

Abstract: The invention relates to a high voltage resistant edge structure in the edge region of a semiconductor component which has floating guard rings of the first conductivity type and inter-ring zones of the second conductivity type which are arranged between the floating guard rings, wherein the conductivities and/or the inter-ring zones are set such that their charge carriers are totally depleted when blocking voltage is applied. The inventive edge structure achieves a modulation of the electrical field both at the surface and in the volume of the semiconductor body. If the inventive edge structure is suitably dimensioned, the field intensity maximum can easily be situated in the depth; that is, in the region of the vertical p-n junction. Thus, a suitable edge construction which permits a “soft” leakage of the electrical field in the volume can always be provided over a wide range of concentrations of p and n doping.

Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.

Abstract: In one embodiment of the invention, a semiconductor component includes a semiconductor substrate (110), a first dielectric layer (120) above the semiconductor substrate, a first ohmic contact region (410) and a second ohmic contact region (420) above the semiconductor substrate, a gate electrode (1120) above the semiconductor substrate and between the first ohmic contact region and the second ohmic contact region, a field plate (210) above the first dielectric layer and between the gate electrode and the second ohmic contact region, a second dielectric layer (310) above the field plate, the first dielectric layer, the first ohmic contact region, and the second ohmic contact region, and a third dielectric layer (910) between the gate electrode and the field plate and not located above the gate electrode or the field plate.

Abstract: A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at least partially filled with a dielectric material and a control port adapted to capacitively couple to the at least one thyristor body region in the substrate. In a more specific implementation, the dielectric material includes deposited dielectric material that is adapted to exhibit resistance to voltage-induced stress that thermally-grown dielectric materials generally exhibit. In another implementation, the dielectric material includes thermally-grown dielectric material, and when used in connection with highly-doped material in the trench, grows faster on the highly-doped material than on a sidewall of the trench that faces the at least on thyristor body region in the substrate.

Abstract: A semiconductor diode structure is provided which includes a substrate; a fin formed of a semiconducting material positioned vertically on the substrate, the fin includes a first heavily-doped region of a first doping type on one side and a second heavily-doped region of a second doping type on an opposite side; and a first conductor contacting the first heavily-doped region and a second conductor contacting the second heavily-doped region.

Abstract: A method is provided for forming one or more doped layers using ion-implantation in the fabrication of thyristor devices. For example, these thyristors may be made from single crystalline silicon carbide. According to one aspect of the invention, one of the required layers is formed by introducing dopants after crystal growth as opposed to conventional methods which involve doping during crystal growth. Specifically, impurities may be introduced by using the technique of ion implantation.

Abstract: A phase change memory may be made using an isolation diode in the form of a Shottky diode between a memory cell and a word line. To reduce the leakage currents associated with the Shottky diode, a guard ring may be utilized.

Abstract: A structure that reduces signal cross-talk through the semiconductor substrate for System-On-Chip (SOC) (2) applications, thereby facilitating the integration of digital circuit blocks (6) and analog circuit blocks (8) onto a single IC. Cross-circuit interaction through a substrate (4) is reduced by strategically positioning the various digital circuit blocks (6) and analog circuit blocks (8) in an isolated wells (10), (12), (16) and (20) over a resistive substrate (4). These well structures (10), (12), (16), and (20) are then surrounded with a patterned low resistivity layer (22) and optional trench region (24). The patterned low resistivity region (22) is formed below wells (10) and (12) and functions as a low resistance AC ground plane. This low resistivity region (22) collects noise signals that propagate between digital circuit blocks (6) and analog circuit blocks (8).

Abstract: A power semiconductor component having a mesa edge termination is described. The component has a semiconductor body with first and second surfaces. An inner zone of a first conductivity type is disposed in the semiconductor body. A first zone is disposed in the semiconductor body and is connected to the inner zone. An edge area outside of the first zone has areas etched out. A second zone of a second conductivity type is disposed in the semiconductor body and is connected to the inner zone, and a boundary area between the second zone and the inner zone defines a pn junction. A field stop zone is adjacent the first surface in the edge area. The field stop zone is formed of the first conductivity type and is embedded in the semiconductor body, and the field stop zone is connected to the first zone and to the inner zone.

Abstract: A semiconductor device is formed including a substrate having an upper surface, a thyristor region in the substrate and a control port adapted for capacitively coupling to at least a portion of the thyristor region via a dielectric material. According to an example embodiment of the present invention, a trench is formed in the substrate and subsequently filled with materials including dielectric material and a control port. The control port is adapted for capacitively coupling to the thyristor via the dielectric material for controlling current flow in the thyristor (e.g., for causing an outflow of minority carriers from a portion of the thyristor for switching the thyristor from conducting state to a blocking state). A portion of the substrate adjacent to the upper surface is implanted with a species of ions, and the dielectric material via which the control port capacitively couples to the thyristor does not include the species of ions.

Abstract: A semiconductor device has: a semiconductor substrate having a surface which has a predetermined pattern, in which an insulating layer is embedded; an interlayer insulator film formed on the substrate, the interlayer insulator film having a protective coat for protecting the substrate; and an electrode formed on the interlayer insulator film. In addition, a method for manufacturing a semiconductor device comprises the steps of: forming a semiconductor substrate having a surface which has a groove in which an insulating layer is embedded; forming a protective coat for protecting the surface of the semiconductor substrate, on the upper surface of the insulating layer embedded in the groove; and forming an electrode on the protective coat.

Abstract: A high voltage semiconductor device includes a drain region disposed within a semiconductor substrate. The semiconductor device further includes a field oxide layer disposed outwardly from the drain region of the semiconductor substrate. The semiconductor device also includes a floating ring structure disposed inwardly from at least a portion of the field oxide layer. In one particular embodiment, a device parameter degradation associated with the semiconductor device comprises one (1) percent or less after approximately five hundred (500) seconds of accelerated lifetime operation.

Abstract: A semiconductor device includes an electronic circuit, a metal guard ring surrounding the electronic circuit, and a passivation layer covering the electronic circuit and guard ring. The passivation layer has a slot extending from the surface of the device down to the guard ring. The slot prevents cracks that may form in the passivation layer at the edges of the device from propagating to the area inside the guard ring. Locating the slot over the guard ring enables the size of the device to be reduced, and enables the guard ring to keep moisture and contaminants that enter the slot from reaching lower layers of the device.

Abstract: A power component formed in an N-type silicon substrate, the lower and upper surfaces of which respectively include a first and a second P-type region that do not extend to the component periphery, a high voltage being capable of existing between the first and second regions and having to be withstood by the junctions between the first and second regions and the substrate. A deep insulating region that does not join the first region is provided at the lower periphery of the component, the lower surface of the substrate between said deep insulating region and the first region being coated with an insulating layer, the height of the deep insulating region being greater than that of a possible soldering upward extension formed during the soldering of the lower surface on a heat sink.

Abstract: A semiconductor memory device comprises a semiconductor substrate having a memory cell region and a periphery circuit region. The memory cell region includes first and second conductivity type wells and an array of memory cell formed on the first and second conductivity type wells. The periphery circuit region comprises a guard ring that is formed at a location next to a second conductivity type well and to surround a side portion of the array of memory cells. The guard ring is formed with a depth different from that of the second conductivity type well.

Abstract: A first guard ring formed by high concentration ion diffusion is established around the transistor formation region of the semiconductor substrate. A second guard ring is established around the first guard ring with a prescribed gap therebetween. A metal film is formed opposing to each guard ring with an insulating film interposed therebetween; these metal films are connected to the opposing guard rings by interlayer wires. The metal films are each connected to external terminals providing a standard potential by individual metal wires from their respective electrodes.

Abstract: The forward and reverse blocking voltage capability of a thyristor in accordance with the invention is substantially independent of the active thyristor area (Aa), thereby facilitating its design and its manufacture. This is achieved by means of a concentric arrangement of a deep inner lower-doped perimeter zone (42) of the forward base region (2) with a deep outer perimeter zone (43) of the same conductivity type, doping profile and depth (A4xj=Axj). The outer perimeter zone (43) brings the reverse blocking p-n junction (34) to the front surface (11) at a lateral distance (D3) around the forward blocking p-n junction (32). The outer perimeter zone (43) extends in depth to a lower perimeter zone (44) of the underlying region (4) that forms the reverse blocking junction with the high-resistivity base region (3) of opposite conductivity type. All these perimeter zones (42-44) together provide the thyristor with a deep peripheral termination which surrounds the active thyristor area (Aa).

Abstract: A method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel junction field effect transistors on a single wafer or die, such that the produced devices may have pinchoff voltages of either positive or negative polarities. A first layer of either p-type or n-type is formed as a base. An alternating, channel layer of either n-type or p-type is then formed, followed by another layer of the same type as the first layer. Etching is used to provide contacts for the gates, source, and drain of the device. In one variation, pinchoff voltage is controlled via dopant level and thickness the channel region. In another variation, pinchoff voltage is controlled by variation of dopant level across the channel layer; and in another variation, pinchoff voltage is controlled by both thickness and variation of dopant level.

Abstract: A semiconductor light emitting device is disclosed in which a semiconductor multilayer structure including a light emitting layer is formed on a substrate and light is output from the opposite surface of the semiconductor multilayer structure from the substrate. The light output surface is formed with a large number of protrusions in the form of cones or pyramids. To increase the light output efficiency, the angle between the side of each protrusion and the light output surface is set to between 30 and 70 degrees.

Abstract: A semiconductor device comprises a first semiconductor layer of a first conductivity type provided on a semiconductor substrate of the first conductivity type, a base layer of a second conductivity type provided in the first semiconductor layer, for defining a vertical MISFET including source regions and a gate electrode on a gate insulation film, a Schottky barrier diode (SBD)-forming region provided in the first semiconductor layer around the base layer, a guard ring region of the second conductivity type provided around SBD-forming region, a first main electrode disposed above the first semiconductor layer and provided in common as both a source electrode of the MISFET and an anode of the SBD, a surface gate electrode disposed above the first semiconductor layer, and a second main electrode provided in common as a drain electrode of the MISFET and a cathode of the SBD.

Abstract: A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR which may induce latch-up phenomenon. Thus, the parasitic SCR is thus not easily to be conducted with a higher resistance to noise. Therefore, the latch-up immunity can be improved. In addition, the ion implantation process can be performed to achieve the objective of preventing latch-up effect without consuming more area for layout, thus greatly enhances the flexibility in circuit design.