Device Protection (e.g., From Overvoltage) Patents (Class 257/173)
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Publication number: 20100301389Abstract: An electrostatic discharge protection structure includes a first vertical bipolar junction transistor; a second vertical bipolar junction transistor, wherein the second vertical bipolar junction transistor has a common collector with the first vertical bipolar junction transistor, and the common collector has a first conductivity; a horizontal bipolar junction transistor wherein the collector of the horizontal bipolar junction transistor has a second conductivity that is a different conductivity than the first conductivity, and the base of the horizontal bipolar junction transistor is electrically coupled to the common collector of the first vertical bipolar junction transistor and the second vertical bipolar junction transistor; a first avalanche diode electrically coupled to the base and the collector of the first vertical bipolar junction transistor; and a second avalanche diode electrically coupled to the base and the collector of the second vertical bipolar junction transistor.Type: ApplicationFiled: May 29, 2009Publication date: December 2, 2010Inventors: Vadim A. Kushner, Amaury Gendron, Chai Ean E. Gill
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Patent number: 7842969Abstract: In one embodiment, an ESD device is configured to include a zener diode and a P-N diode and to have a conductor that provides a current path between the zener diode and the P-N diode.Type: GrantFiled: July 10, 2008Date of Patent: November 30, 2010Assignee: Semiconductor Components Industries, LLCInventors: David D. Marreiro, Sudhama C. Shastri, Ali Salih, Mingjiao Liu, John Michael Parsey, Jr.
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Patent number: 7842970Abstract: An electrostatic discharge (ESD) protective device structure is disclosed. The ESD protection device includes: at least a first conductive type metal-oxide semiconductor (MOS), in which the drain and source of the first conductive type MOS are electrically connected to a first power terminal and a second power terminal separately; at least a second conductive type diffusion region; and at least a dummy gate disposed between the first conductive type MOS and the second conductive type diffusion region, wherein the gate length of the dummy gate is less than the gate length of the first conductive type MOS gate, such that the junction between the second conductive type diffusion region and the drain of the first conductive type MOS have a low breakdown voltage.Type: GrantFiled: February 4, 2009Date of Patent: November 30, 2010Assignee: United Microelectronics Corp.Inventor: Ching-Hung Kao
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Patent number: 7842971Abstract: A silicon-controlled rectifier (SCR) device having a high holding voltage includes a PNP transistor and an NPN transistor, each transistor having both p-type and n-type dopant regions in their respective emitter areas. The device is particularly suited to high voltage applications, as the high holding voltage provides a device which is more resistant to latchup subsequent to an electrostatic discharge event compared to devices having a low holding voltage.Type: GrantFiled: February 5, 2009Date of Patent: November 30, 2010Assignees: Intersil Americas Inc., University of Central Florida Research Foundation, Inc.Inventors: Zhiwei Liu, Juin J. Liou, James E. Vinson
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Publication number: 20100295094Abstract: An ESD protection apparatus includes a substrate, a transistor structure arranged in the substrate, and a diode structure arranged in the substrate, a high-resistance electrical connection being provided between the transistor structure and the diode structure in the substrate.Type: ApplicationFiled: August 2, 2010Publication date: November 25, 2010Inventors: Sven Albers, Klaus Diefenbeck, Bernd Eisener, Gernot Langguth, Christian Lehrer, Karl-Heinz Malek, Eberhard Rohrer
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Patent number: 7838941Abstract: Disclosed is an electrostatic discharge protection device that has a low trigger voltage and protects an internal circuit from electrostatic discharge. The ESD protection device includes an NMOS transistor in which a first pad and a drain are connected to each other and a second pad and a source are connected to each other. A capacitor in which an end is connected to the first pad and the other end is connected to a gate of the NMOS transistor and a substrate contact of the NMOS transistor. The ESD protection devices also includes a resistor in which an end is connected to the second pad and the other end is connected to the capacitor. The first pad may be a power pad and the second pad may be a ground pad. Alternately, the first pad may be an input/output pad and the second pad may be a ground pad.Type: GrantFiled: December 24, 2007Date of Patent: November 23, 2010Assignee: Hynix Semiconductor Inc.Inventor: Kook Whee Kwak
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Patent number: 7833857Abstract: An ESD protecting circuit and a manufacturing method thereof are provided. The ESD protecting circuit includes a device isolation layer, first and second high-concentration impurity regions, a third high-concentration impurity region of a complementary type, first and second conductive wells, and a fourth conductive impurity region. The ESD protecting circuit is configured as a field transistor without a gate electrode, and the high breakdown voltage characteristics of the field transistor are lowered by implanting impurity ions, providing an ESD protecting circuit with a low breakdown voltage and low leakage current. Because the leakage current is reduced, the ESD protecting circuit can be used for an analog I/O device that is sensitive to current fluxes. Also, an N-type well may protect a junction of the field transistor.Type: GrantFiled: September 1, 2009Date of Patent: November 16, 2010Assignee: Dongbu Electronics Co., Ltd.Inventor: San Hong Kim
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Patent number: 7834378Abstract: A composite dual SCR circuit that acts to protect the Vcc node as well as an I/O node or pin. The dual SCR uses the Vcc to control or program the triggering point of the SCR connected to an I/O node. When Vcc is low, the SCR protecting an I/O node triggers a few volts above ground, but when Vcc is high the trigger point of the SCR protecting the I/O node is much higher. The dual SCR incorporates added diffusions to an existing first SCR structure between the power node and the ground node thereby forming a second SCR. The first and second SCRs share a common cathode transistor. In one illustrative embodiment, only one SCR is constructed incorporating the Vcc to control the triggering of the SCR.Type: GrantFiled: August 28, 2007Date of Patent: November 16, 2010Assignee: Fairchild Korea Semiconductor LtdInventors: Junhyeong Ryu, Taeghyun Kang, Moonho Kim
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Patent number: 7825431Abstract: A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.Type: GrantFiled: December 31, 2007Date of Patent: November 2, 2010Assignee: Alpha & Omega Semicondictor, Ltd.Inventors: Anup Bhalla, Xiaobin Wang, Wei Wang, Yi Su, Daniel Ng
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Patent number: 7825480Abstract: The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal.Type: GrantFiled: June 4, 2008Date of Patent: November 2, 2010Assignee: Renesas Electronics CorporationInventors: Hiroki Arai, Nobuyuki Shirai, Tsuyoshi Kachi
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Patent number: 7825429Abstract: A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured to provide a trigger current to the dual-direction silicon controlled rectifier when a desired voltage between the first and second grounds is reached.Type: GrantFiled: January 14, 2010Date of Patent: November 2, 2010Assignee: Intersil Americas Inc.Inventor: James E. Vinson
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Publication number: 20100270549Abstract: A semiconductor device has an integrated passive device (IPD) formed over a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed over the first side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed over the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed over the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed over the substrate and electrically connects the conductive layer to a ground point.Type: ApplicationFiled: July 6, 2010Publication date: October 28, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Robert C. Frye, Yaojian Lin, Rui Huang
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Patent number: 7821029Abstract: An electrostatic protection element relating to the present invention comprises a P-type semiconductor and an N-type first impurity layer provided in the semiconductor substrate. The first impurity layer comprises a P-type second impurity layer functioning as a gate. The second impurity layer comprises an N-type third impurity layer functioning as a cathode. Further, the first impurity layer comprises an N-type fourth impurity layer spaced apart from the second impurity layer at a distance. The fourth impurity layer comprises a P-type fifth impurity layer functioning as an anode and an N-type sixth impurity layer. Then, in the electrostatic protection element, an impurity concentration of the fourth impurity layer is higher than that of the first impurity layer, and a bottom of the fourth impurity layer is deeper than that of the second impurity layer.Type: GrantFiled: August 18, 2009Date of Patent: October 26, 2010Assignee: Panasonic CorporationInventor: Manabu Imahashi
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Publication number: 20100264457Abstract: An electrostatic discharge (ESD) protection circuit for protecting an integrated circuit (IC) having a first voltage potential, a first power supply potential and a second power supply potential. The ESD circuit includes a first NPN bipolar transistor having a first N-doped junction, a second N-doped junction and a third P-doped base junction. The first N-doped junction is coupled to the first voltage potential and the second N-doped junction is coupled to the first power supply potential. The ESD circuit also includes a first PNP bipolar transistor having a first P-doped junction, a second P-doped junction and a third N-doped base junction. The first P-doped junction is coupled to the first voltage potential and the second P-doped junction is coupled to the second power supply potential. The third P-doped base junction of the first NPN bipolar transistor is coupled to the third N-doped base junction of the first PNP bipolar transistor.Type: ApplicationFiled: April 15, 2010Publication date: October 21, 2010Inventors: Bart Sorgeloos, Benjamin Van Camp
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Patent number: 7812367Abstract: In one embodiment, a two terminal multi-channel ESD device is configured to include a zener diode and a plurality of P-N diodes.Type: GrantFiled: October 15, 2008Date of Patent: October 12, 2010Assignee: Semiconductor Components Industries, LLCInventors: Ali Salih, Mingjiao Liu, Thomas Keena
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Publication number: 20100244095Abstract: A dual triggered silicon controlled rectifier (DTSCR) comprises: a semiconductor substrate; an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region, a third P+ diffusion region, positioned in one side of the DTSCR and across the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and across the N-well and the P-well; a first gate, positioned above the N-well between the second P+ diffusion region and the third P+ diffusion region, for use as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first N+ diffusion region and the third N+ diffusion region, for use as an N-type trigger node to receive a second trigger current or a second trigger voltage.Type: ApplicationFiled: June 9, 2010Publication date: September 30, 2010Inventor: Kei-Kang Hung
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Publication number: 20100244094Abstract: A dual triggered silicon controlled rectifier (DTSCR) comprises: a semiconductor substrate; a well region, a first N+ diffusion region, a first P+ diffusion region, a second N+ diffusion region, a second P+ diffusion region, a third P+ diffusion region, positioned in one side of the DTSCR and across the well region and semiconductor substrate; a third N+ diffusion region, positioned in another side of the DTSCR and across the well region and the semiconductor substrate; a first gate, positioned above the semiconductor substrate between the first P+ diffusion region and the third P+ diffusion region, utilized as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the well region between the second N+ diffusion region and the third N+ diffusion region, utilized as an N-type trigger node to receive a second trigger current or a second trigger voltage.Type: ApplicationFiled: June 8, 2010Publication date: September 30, 2010Inventor: Kei-Kang Hung
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Patent number: 7804671Abstract: An electrostatic discharge protection circuit has a substrate; a first P-well installed on the substrate and having a first P+-doped region and a first N+-doped region, both of which are connected to ground; a second P-well installed on the substrate and having a second P+-doped region and a second N+-doped region, both of which are connected to a power supply voltage; and a third P-well installed on the substrate and having a third N+-doped region, a third P+-doped region, and a fourth N+-doped region, all of which are for input/output signals.Type: GrantFiled: November 8, 2007Date of Patent: September 28, 2010Assignee: VIA Technologies Inc.Inventors: Bob Cheng, Tony Ho, Bouryi Sze
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Publication number: 20100237356Abstract: An electronic device includes a silicon carbide layer having a first conductivity type and having a first surface and a second surface opposite the first surface, and first and second silicon carbide Zener diodes on the silicon carbide layer. Each of the first and second silicon carbide Zener diodes may include a first heavily doped silicon carbide region having a second conductivity type opposite the first conductivity type on the silicon carbide layer, and an ohmic contact on the first heavily doped silicon carbide region.Type: ApplicationFiled: March 20, 2009Publication date: September 23, 2010Inventors: Sarah Kay Haney, Sei-Hyung Ryu
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Publication number: 20100237386Abstract: An electrostatic discharge (ESD) structure for a 3-dimensional (3D) integrated circuit (IC) through-silicon via (TSV) device is provided. The ESD structure includes a substrate, a TSV device which is formed through the substrate and is equivalent to a resistance-inductance-capacitance (RLC) device, and at least one ESD device which is disposed in the substrate and electrically connected to one end of the TSV device. The ESD structure can protect the 3D IC TSV device.Type: ApplicationFiled: September 22, 2009Publication date: September 23, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Sheng Lin, Chih-Wen Hsiao, Keng-Li Su
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Patent number: 7800127Abstract: In an ESD device for fast switching applications based on a BSCR or NLDMOS-SCR, an anode junction control electrode is provided by not connecting the anode electrode to the collector of the BSCR or to the drain of the NLDMOS-SCR, and a cathode junction control electrode is provided by forming an additional n+ region in the BSCR or an additional p+ region in the p-well of the NLDMOS-SCR. The triggering voltage of the ESD device is adjusted after a time delay by controlling one or both of the control electrodes using an RC-timer-driver circuit.Type: GrantFiled: August 14, 2006Date of Patent: September 21, 2010Assignee: National Semiconductor CorporationInventors: Vladislav Vashchenko, Alexander Burinskiy, Peter J. Hopper, Vladimir Kuznetsov
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Patent number: 7800128Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.Type: GrantFiled: June 12, 2008Date of Patent: September 21, 2010Assignee: Infineon Technologies AGInventors: Krzysztof Domanski, Cornelius Christian Russ, Kai Esmark
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Patent number: 7800180Abstract: A semiconductor device is disclosed. The semiconductor device includes an internal circuit having a high breakdown voltage transistor, and a first electrostatic protection circuit in which electrostatic protection elements are connected in series. The sum of the breakdown voltage values of the electrostatic protection elements in the first electrostatic protection circuit is almost equal to the breakdown voltage value of the high breakdown voltage transistor. The first electrostatic protection circuit is connected between an input/output terminal and a ground terminal of the semiconductor device to which terminals the internal circuit is connected.Type: GrantFiled: June 4, 2007Date of Patent: September 21, 2010Assignee: Mitsumi Electric Co., Ltd.Inventors: Atsushi Watanabe, Yasuhisa Ishikawa
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Publication number: 20100230719Abstract: In an aspect of the present invention, an ESD (Electrostatic Discharge) protection element includes a bipolar transistor comprising a collector diffusion layer connected with a first terminal and an emitter diffusion layer; and current control resistances provided for a plurality of current paths from a second terminal to the collector diffusion layer through the emitter diffusion layer, respectively. The bipolar transistor further includes a base diffusion region connected with the second terminal through a first resistance which is different from the current control resistances.Type: ApplicationFiled: March 11, 2010Publication date: September 16, 2010Applicant: NEC Electronics CorporationInventor: Kouichi SAWAHATA
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Patent number: 7795637Abstract: The present invention relates a technique using a silicon controlled rectifier (SCR) in a rail based non-breakdown (RBNB) ESD protection device that protects a micro chip from ESD stress.Type: GrantFiled: December 24, 2008Date of Patent: September 14, 2010Assignee: MagnaChip Semiconductor, Ltd.Inventor: Jeong Sik Hwang
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Patent number: 7791102Abstract: Methods and devices are provided for protecting semiconductor devices against electrostatic discharge events. An electrostatic discharge protection device comprises a silicon substrate, a P+-type anode region disposed within the silicon substrate, and an N-well device region disposed within the silicon substrate in series with the P+-type anode region. A first P-well device region is disposed within the silicon substrate in series with the first N-well device region and an N+-type cathode region is disposed within the silicon substrate. A gate electrode is disposed at least substantially overlying the first N-well and P-well device regions of the silicon substrate.Type: GrantFiled: October 16, 2006Date of Patent: September 7, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Akram Salman, Stephen Beebe
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Patent number: 7786507Abstract: A 2-terminal (i.e., anode, cathode) symmetrical bi-directional semiconductor electrostatic discharge (ESD) protection device is disclosed. The symmetrical bi-directional semiconductor ESD protection device design comprises a first and second shallow wells symmetrically spaced apart from a central floating well. Respective shallow wells comprise a first and second highly doped contact implant with opposite doping types (e.g., n-type, p-type). One or more field plates, connected to the central floating well, extend laterally outward from above the central well. The device can be used as an ESD protection device at a bi-directional I/O (e.g., in parallel with a symmetrical MOS to be protected). Upon an ESD event at an input node comprising the first and second shallow wells, a coupled npn-pnp bipolar component comprising the center well, the first and second shallow wells, and the first and second contact implants, is triggered, thereby shunting current from the first to the second shallow well.Type: GrantFiled: January 6, 2009Date of Patent: August 31, 2010Assignee: Texas Instruments IncorporatedInventors: Marie Denison, Pinghai Hao
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Patent number: 7786504Abstract: The present invention discloses a bidirectional PNPN silicon-controlled rectifier comprising: a p-type substrate; a N-type epitaxial layer; a P-type well and two N-type wells all formed inside the N-type epitaxial layer with the two N-type wells respectively arranged at two sides of the P-type well; a first semiconductor area, a second semiconductor area and a third semiconductor area all formed inside the P-type well and all coupled to an anode, wherein the second semiconductor area and the third semiconductor area are respectively arranged at two sides of the first semiconductor area, and wherein the first semiconductor area is of first conduction type, and the second semiconductor area and the third semiconductor area are of second conduction type; and two P-type doped areas respectively formed inside the N-type wells, wherein each P-type doped area has a fourth semiconductor area neighboring the P-type well and a fifth semiconductor area, and wherein both the fourth semiconductor area and the fifth semicoType: GrantFiled: March 20, 2008Date of Patent: August 31, 2010Assignee: Amazing Microelectronic Corp.Inventors: Wen-Yi Chen, Ryan Hsin-Chin Jiang, Ming-Dou Ker
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Patent number: 7781769Abstract: A transistor array panel includes switching elements provided in intersecting portions between gate and data lines, and display electrodes connected to the switching elements. A conductive film pattern is provided to be electrically insulated from the gate and data lines, and display electrodes, and to be overlapped on the display electrodes, thereby forming a storage capacitance between each of the display electrodes and the conductive film pattern. A protection circuit is electrically connected to the gate and data lines, and disposed in an outer peripheral portion of a display region in which the switching elements and the display electrodes are formed on the one side of the substrate. A common line is insulated from the protection circuit, connected to the conductive film pattern, and provided to be insulated from the protection circuit and to be at least partially overlapped on the protection circuit, in the outer peripheral portion of the display region.Type: GrantFiled: September 29, 2008Date of Patent: August 24, 2010Assignee: Casio Computer Co., Ltd.Inventor: Yayoi Nakamura
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Publication number: 20100207163Abstract: A semiconductor device includes a protected circuit and an electrostatic-discharge protection circuit. The electrostatic-discharge protection circuit includes a first well of a first conductivity type and a second well of a second conductivity type formed in contact with each other in a semiconductor substrate, a first impurity diffusion layer of the first conductivity type and a third impurity diffusion layer of the second conductivity type formed apart from each other in the first well, and a second impurity diffusion layer of the second conductivity type and a fourth impurity diffusion layer of the first conductivity type formed apart from each other in the second well. The second and the third impurity diffusion layers are formed adjacent to each other interposing an element isolation region provided across a border between the first and the second wells.Type: ApplicationFiled: April 30, 2010Publication date: August 19, 2010Applicant: PANASONIC CORPORATIONInventors: Hiroaki YABU, Katsuya Arai, Toshihiro Kougami
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Publication number: 20100208405Abstract: A semiconductor device includes an ESD device region disposed within a semiconductor body of a first semiconductor type, an isolation region surrounding the ESD device region, a first doped region of a second conductivity type disposed at a surface of the semiconductor body within the ESD region, and a second doped region of the first conductivity type disposed between the semiconductor body within the ESD region and at least a portion of the first doped region, where the doping concentration of the second doped region is higher than the semiconductor body. A third doped region of the second semiconductor type is disposed on the semiconductor body and a fourth region of the first conductivity type is disposed over the third doped region. A fifth doped region of the second conductivity type is disposed on the semiconductor body. A trigger device and an SCR is formed therefrom.Type: ApplicationFiled: April 28, 2010Publication date: August 19, 2010Inventors: Cornelius Christian Russ, Kai Esmark, David Alvarez, Jens Schneider
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Patent number: 7777999Abstract: An electrostatic discharge (ESD) protection device includes an I/O terminal structure and a current discharge structure. The current discharge structure includes a conductive region separated from a bridge region by a gate electrode, a well region formed below the conductive region, another well region separated from the well region by another conductive region, and multiple additional conductive regions implementing dual current discharge paths through another well region.Type: GrantFiled: January 7, 2008Date of Patent: August 17, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Myoung-Gon Kang, Ki-Whan Song
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Patent number: 7777277Abstract: The present invention provides a dual triggered silicon controlled rectifier (DTSCR) including: a semiconductor substrate, an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region; a third P+ diffusion region, positioned in one side of the DTSCR and across the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and across the N-well and the P-well; a first gate, positioned above the N-well between the second and the third P+ diffusion regions, utilized as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first and the third N+ diffusion regions, utilized as an N-type trigger node to receive a second trigger current or a second trigger voltage.Type: GrantFiled: June 26, 2008Date of Patent: August 17, 2010Assignee: Raydium Semiconductor CorporationInventor: Kei-Kang Hung
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Patent number: 7772680Abstract: The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts the electrically conductive plate as a separate region relative to the other links, and the region where a link makes contact to the electrically conductive plate is a fuse. The invention also includes methods of forming semiconductor fuse arrangements.Type: GrantFiled: August 18, 2005Date of Patent: August 10, 2010Assignee: Micron Technology, Inc.Inventor: H. Montgomery Manning
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Patent number: 7768034Abstract: An electrostatic discharge (ESD) protection network for power MOSFETs includes parallel branches, containing polysilicon zener diodes and resistors, used for protecting the gate from rupture caused by high voltages caused by ESD. The branches may have the same or independent paths for voltage to travel across from the gate region into the semiconductor substrate. Specifically, the secondary branch has a higher breakdown voltage than the primary branch so that the voltage is shared across the two branches of the protection network. The ESD protection network of the device provides a more effective design without increasing the space used on the die. The ESD protection network can also be used with other active and passive devices such as thyristors, insulated-gate bipolar transistors, and bipolar junction transistors.Type: GrantFiled: October 1, 2007Date of Patent: August 3, 2010Assignee: Fairchild Semiconductor CorporationInventors: Daniel S. Calafut, Hamza Yilmaz, Steven Sapp
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Patent number: 7763940Abstract: An electronic device having an LV-well element trigger structure that reduces the effective snapback trigger voltage in MOS drivers or ESD protection devices. A reduced triggering voltage facilitates multi-finger turn-on and thus uniform current flow and/or helps to avoid competitive triggering issues.Type: GrantFiled: December 15, 2005Date of Patent: July 27, 2010Assignee: Sofics BVBAInventors: Markus Paul Josef Mergens, Bart Keppens, Koen Verhaege, John Armer, Cong Son Trinh
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Patent number: 7763908Abstract: A silicon-controlled rectifier apparatus, comprising a substrate upon which a low-voltage triggered silicon-controlled rectifier is configured. A plurality of triggering components (e.g., NMOS fingers) are formed upon the substrate and integrated with the low-voltage triggered silicon-controlled rectifier, wherein the plurality of triggering components are inserted into the low-voltage triggered silicon-controlled rectifier in order to permit the low-voltage triggered silicon-controlled rectifier to protect against electrostatic discharge during human-body model and charged-device model stress events.Type: GrantFiled: July 25, 2005Date of Patent: July 27, 2010Assignee: LSI CorporationInventor: Jau-Wen Chen
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Publication number: 20100181597Abstract: A protection device of programmable semiconductor surge suppressor having deep-well structure is provided comprising one, two or four protection units, each of which is composed of a PN-junction diode, a PNPN-type thyristor and a NPN-type triode connected with each other. It is characterized in that in the diode area on the frontal side of the N-type semiconductor base is formed a PN junction with impurity concentration changed gradiently from top to bottom according to the order of P+, P, N and N+; and a group of deep-wells with P-type impurities are positioned at the interface of the PN junction, making the PN junction form a concave-convex type interface. The present invention can be used in the program-controlled switchboard to protect the Subscriber Line Interface Circuit (SLIC) board. The above improvement can further improve the anti-lightning and anti-surge performance and the energy discharge capability of the whole device.Type: ApplicationFiled: September 25, 2009Publication date: July 22, 2010Applicant: SEMITEL ELECTRONICS CO., LTD.Inventors: Walance Sun, Ken Ou, Shouming Zhang, Man Ng
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Patent number: 7755143Abstract: A semiconductor device is described. The semiconductor device comprises a protected device in a protected device area of a substrate. An electrostatic discharge power clamp device comprising an outer first guard ring and an inner second guard ring is in a guard ring area of the substrate, enclosing the protected device. The first guard ring comprises a first well region having a first conductive type. A first doped region having the first conductive type and a second doped region having a second conductive type are in the first well region. The second guard ring comprises a second well region having a second conductive type. A third doped region has the second conductive type in the second well region. An input/output device is in a periphery device area, coupled to the electrostatic discharge power clamp device.Type: GrantFiled: July 22, 2008Date of Patent: July 13, 2010Assignee: Vanguard International Semiconductor CorporationInventors: Yeh-Ning Jou, Geeng-Lih Lin
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Patent number: 7755102Abstract: A multiple layer overvoltage protection device is provided. The method begins by providing a substrate having a first impurity concentration of a first conductivity type to define a mid-region layer. A dopant of a second conductivity type is introduced into the substrate with a second impurity concentration less than the first impurity concentration. An upper base region having a second type of conductivity is formed on the upper surface of the mid-region layer. A lower base region layer having a second type of conductivity is formed on a lower surface of the mid-region layer. A first emitter region having a first type of conductivity is formed on a surface of the upper base region layer. A first metal contact is coupled to the upper base region layer and a second metal contact is coupled to the lower base region layer.Type: GrantFiled: October 3, 2006Date of Patent: July 13, 2010Assignee: Vishay General Semiconductor LLCInventors: Lung-Ching Kao, Pu-Ju Kung
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Publication number: 20100171149Abstract: A 2-terminal (i.e., anode, cathode) symmetrical bidirectional semiconductor electrostatic discharge (ESD) protection device is disclosed. The symmetrical bidirectional semiconductor ESD protection device design comprises a first and second shallow wells symmetrically spaced apart from a central floating well. Respective shallow wells comprise a first and second highly doped contact implant with opposite doping types (e.g., n-type, p-type). One or more field plates, connected to the central floating well, extend laterally outward from above the central well. The device can be used as an ESD protection device at a bidirectional I/O (e.g., in parallel with a symmetrical MOS to be protected). Upon an ESD event at an input node comprising the first and second shallow wells, a coupled npn-pnp bipolar component comprising the center well, the first and second shallow wells, and the first and second contact implants, is triggered, thereby shunting current from the first to the second shallow well.Type: ApplicationFiled: January 6, 2009Publication date: July 8, 2010Applicant: Texas Instruments IncorporatedInventors: Marie Denison, Pinghai Hao
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Patent number: 7750408Abstract: Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements.Type: GrantFiled: March 29, 2007Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Zhong-Xiang He, Robert M. Rassel, Steven H. Voldman
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Publication number: 20100155774Abstract: A bidirectional transient voltage suppression device is disclosed. The bi-directional transient voltage suppression device comprises a semiconductor die. The semiconductor die has a multi-layer structure comprising a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type, an epitaxial layer, and five diffused regions. The buried layer and the semiconductor substrate form a first semiconductor junction. The first diffused region of the second conductivity type and the semiconductor substrate form a second semiconductor junction. The fourth diffused region of the first conductivity type and the third diffused region of the second conductivity type form a third semiconductor junction. The fifth diffused region of the first conductivity type and the second diffused region of the second conductivity type form a fourth semiconductor junction.Type: ApplicationFiled: December 23, 2008Publication date: June 24, 2010Applicant: AMAZING MICROELECTRONIC CORP.Inventors: Tang Kuei TSENG, Kun Hsien LIN, Hsin Chin JIANG
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Publication number: 20100155775Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. Further, the first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.Type: ApplicationFiled: December 23, 2008Publication date: June 24, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert J. GAUTHIER, JR., Junjun LI, Ankit SRIVASTAVA
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Publication number: 20100155776Abstract: A method of forming an electrostatic discharging (ESD) device includes forming a first and a second semiconductor fin over a substrate and adjacent to each other; epitaxially growing a semiconductor material on the first and the second semiconductor fins, wherein a first portion of the semiconductor material grown from the first semiconductor fin joins a second portion of the semiconductor material grown from the second semiconductor fin; and implanting a first end and a second end of the semiconductor material and first end portions of the first and the second semiconductor fins to form a first and a second implant region, respectively. A P-N junction is formed between the first end and the second end of the semiconductor material. The P-N junction is a junction of an ESD diode, or a junction in an NPN or a PNP BJT.Type: ApplicationFiled: February 26, 2010Publication date: June 24, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jam-Wem Lee
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Publication number: 20100140713Abstract: A transistor-type protection device includes: a semiconductor substrate; a well of a first-conductivity-type formed in the semiconductor substrate; a source region of a second-conductivity-type formed in the well; a gate electrode formed on the well via a gate insulating film at one side of the source region; plural drain regions of a second-conductivity-type formed apart from each other and respectively separated at a predetermined distance from a well part immediately below the gate electrode film; and a resistive connection part connecting between the plural drain regions with a predetermined electric resistance.Type: ApplicationFiled: November 18, 2009Publication date: June 10, 2010Applicant: SONY CORPORATIONInventors: Tsutomu IMOTO, Toshio KOBAYASHI
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Publication number: 20100140659Abstract: An ESD protection device comprises a P-type substrate, a first substrate-triggered silicon controlled rectifiers (STSCR) disposed in the P-type substrate and a second STSCR disposed in the P-type substrate. The first STSCR comprises a first N-well, a first P-well, a first N+ diffusion region, a first P+ diffusion region, and a first trigger node. The second STSCR comprises a second N-well electrically connected to the first N-well, a second P-well electrically connected to the first P-well, a second N+ diffusion region electrically connected to the first P+ diffusion region, a second P+ diffusion region electrically connected to the first N+ diffusion region, and a second trigger node. A layout area of an integrated circuit and a pin-to-pin ESD current path can be reduced.Type: ApplicationFiled: December 8, 2008Publication date: June 10, 2010Inventors: Ming-Dou Ker, Yuan-Wen Hsiao, Chang-Tzu Wang
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Patent number: 7732834Abstract: A semiconductor device includes an ESD device region disposed within a semiconductor body of a first semiconductor type, an isolation region surrounding the ESD device region, a first doped region of a second conductivity type disposed at a surface of the semiconductor body within the ESD region, and a second doped region of the first conductivity type disposed between the semiconductor body within the ESD region and at least a portion of the first doped region, where the doping concentration of the second doped region is higher than the semiconductor body. A third doped region of the second semiconductor type is disposed on the semiconductor body and a fourth region of the first conductivity type is disposed over the third doped region. A fifth doped region of the second conductivity type is disposed on the semiconductor body. A trigger device and an SCR is formed therefrom.Type: GrantFiled: January 26, 2007Date of Patent: June 8, 2010Assignee: Infineon Technologies AGInventors: Cornelius Christian Russ, Kai Esmark, David Alvarez, Jens Schneider
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Publication number: 20100133583Abstract: Disclosed herein is a semiconductor integrated circuit including a protected circuit; and a protection element formed on the same semiconductor substrate as the protected circuit and adapted to protect the protected circuit, wherein the protection element includes two diodes having their anodes connected together to form a floating node and two cathodes connected to the protected circuit, the two diodes are formed in a well-in-well structure on the semiconductor substrate, and the well-in-well structure includes a P-type well forming the floating gate, an N-type well which surrounds the surfaces of the P-type well other than that on the front side of the substrate with the deep portion side of the substrate so as to form the cathode of one of the diodes, and a first N-type region formed in the P-type well so as to form the cathode of the other diode.Type: ApplicationFiled: November 2, 2009Publication date: June 3, 2010Applicant: Sony CorporationInventors: Kouzou Mawatari, Motoyasu Yano
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Patent number: 7728385Abstract: A device structure is disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process was found to cause the gate oxide damage before. The present invention structure includes a semiconductor substrate having an active area and a termination area; numerous trench MOSFET cells disposed in the active area; numerous electrostatic discharge (ESD) diodes disposed above the semiconductor substrate in the termination area; and an insulation layer comprising Oxide/Nitride/Oxide (ONO) sandwiched between the ESD diodes and the semiconductor substrate. In one embodiment, the active area does not contain the ONO insulation layer.Type: GrantFiled: July 22, 2009Date of Patent: June 1, 2010Assignee: Alpha & Omega Semiconductor, Ltd.Inventors: Mengyu Pan, Zengyi He, Kaiyu Chen