Abstract: A semiconductor device has an integrated passive device (IPD) formed over a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed over the first side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed over the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed over the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed over the substrate and electrically connects the conductive layer to a ground point.

Abstract: A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal.

Abstract: Static electricity generated in each data line 3 at the time of manufacturing a TFT active matrix substrate 10 is discharged to a common line 110 through a bidirectional diode 30A. Since the bidirectional diode 30A is configured to have a first allowable level higher than a second allowable level of a protection circuit 112, a leak current that are generated in each data line 3 when being driven is discharged to common lines 111A, 111B through the protection circuit 112.

Abstract: An electrostatic discharge (ESD) protection element includes a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type.

Abstract: A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A1?A2 and B1<B2 where the LDMOS transistor formation region has an overlap length A1 of the gate electrode and the element isolation film and a distance B1 between the gate electrode and the drain region, and the ESD protection element formation region has an overlap length A2 of the gate electrode and the element isolation film and a distance B2 between the gate electrode and the anode region.

Abstract: Disclosed is a power supply line in which a voltage drop generated in a resistance component of a metal line which delivers a power voltage is minimized so that the level of the power supply voltage delivered to a semiconductor chip becomes constant in the entire area of the semiconductor chip. The semiconductor chip includes: at least two power supply pads to which a power voltage applied from an external unit of the semiconductor chip is supplied; power supply main metal lines connected to each of the power supply pads; power supply branch metal lines extended from each of the power supply main metal lines to deliver a power voltage to a circuit in the semiconductor chip; and at least an electrostatic discharge (ESD) improvement dummy pad, wherein the ESD improvement dummy pad is electrically connected to the corresponding power supply main metal line and the corresponding power supply branch metal line to minimize a voltage drop.

Abstract: One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.

Abstract: An electrostatic protection circuit in a semiconductor device includes a first first-conductivity type well extending in a first direction over a semiconductor substrate, a second first-conductivity type well extending in a second direction over the semiconductor substrate and perpendicular to the first direction with one end coupled to a first long side of the first first-conductivity type well, and a second-conductivity type well formed around the first first-conductivity type well and the second first-conductivity type well. It also includes a first high-concentration second-conductivity type region extending in the second direction on a surface of the second first-conductivity type well and a first high-concentration first-conductivity type region extending in the second direction on a surface of the second-conductivity type well while facing the first high-concentration second-conductivity type region.

Abstract: A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications.

Abstract: An IGBT, which is capable of reducing on resistance by reducing channel mobility, includes: an n type substrate made of SiC and having a main surface with an off angle of not less than 50° and not more than 65° relative to a plane orientation of {0001}; a p type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; an n type well region formed to include a second main surface of the reverse breakdown voltage holding layer; an emitter region formed in the well region to include the second main surface and including a p type impurity at a concentration higher than that of the reverse breakdown voltage holding layer; a gate oxide film formed on the reverse breakdown voltage holding layer; and a gate electrode formed on the gate oxide film. In a region including an interface between the well region and the gate oxide film, a high-concentration nitrogen region is formed to have a nitrogen concentration higher than those of the well region and the gate oxide film.

Abstract: Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises a well having an emitter and a collector region. The well has a doping of a first type, and the emitter and collector regions have a doping of a second type. The emitter region, well, and collector region are configured to operate as an emitter, base, and collector for a first transistor, respectively. The collector region is spaced away from the emitter region to define a spacing. A first spacer and a second spacer are positioned adjacent the well between the emitter and the collector. A conductive plate is positioned adjacent the well and between the first spacer and the second spacer, and a doping adjacent the first spacer, the second spacer, and the plate consists essentially of the first type.

Abstract: An electrostatic discharge (ESD) protected device may include a substrate, an N-type well region disposed corresponding to a first portion of the substrate and having two N+ segments disposed at a surface thereof, an a P-type well region disposed proximate to a second portion of the substrate and having a P+ segment and an N+ segment. The two N+ segments may be spaced apart from each other and each may each be associated with an anode of the device. The N+ segment may be associated with a cathode of the device. A contact may be positioned in a space between the two N+ segments and connected to the P+ segment. The contact may form a parasitic capacitance that, in connection with a parasitic resistance formed in association with the N+ segment, provides self detection for high voltage ESD protection.

Abstract: An electrostatic discharge (ESD) protection element using an NPN bipolar transistor, includes: a trigger element connected at one end with a pad. The NPN bipolar transistor includes: a first base diffusion layer; a collector diffusion layer connected with the pad; a trigger tap formed on the first base diffusion layer and connected with the other end of the trigger element through a first wiring; and an emitter diffusion layer and a second base diffusion layer formed on the first base diffusion layer and connected in common to a power supply through a second wiring which is different from the first wiring.

Abstract: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.

Abstract: A electrostatic protection element (101) includes: a substrate (1) of a first conductivity type; a first low-concentration diffusion region (2) of a second conductivity type and a second low-concentration diffusion region (3) of the first conductivity type which are formed on said substrate (1), the second conductivity type being different from the first conductivity type; a first high-concentration diffusion region (4) of the second conductivity type and a second high-concentration diffusion region (5) of the first conductivity type which are (i) formed in said first low-concentration diffusion region (2), and (ii) electrically connected with each other; a third high-concentration diffusion region (9) of the first conductivity type and a fourth high-concentration diffusion region (8) of the second conductivity type which are (i) formed in said second low-concentration diffusion region (3), and (ii) electrically connected with each other; a fifth high-concentration diffusion region (6) of the first conductivi

Abstract: A MOSFET, which is capable of reducing on resistance by reducing channel mobility even when a gate voltage is high, includes: an n type substrate made of SiC and having a main surface with an off angle of 50°-65° relative to a {0001} plane; an n type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; a p type well region formed in the reverse breakdown voltage holding layer distant away from a first main surface thereof; a gate oxide film formed on the well region; an n type contact region disposed between the well region and the gate oxide film; a channel region connecting the n type contact region and the reverse breakdown voltage holding layer; and a gate electrode disposed on the gate oxide film. In a region including an interface between the channel region and the gate oxide film, a high-concentration nitrogen region is formed.

Abstract: A first first-conductivity-type diffusion layer, a first second-conductivity-type diffusion layer, a second first-conductivity-type diffusion layer, and a second second-conductivity-type diffusion layer are arranged in this order. In a region where the second second-conductivity-type diffusion layer and the first-conductivity-type layer are in contact with each other, impurity concentrations thereof are higher in a part in contact with a side face of the second second-conductivity-type diffusion layer than in a part at a bottom surface of the second second-conductivity-type diffusion layer.

Abstract: A device comprising a two-dimensional electron gas that includes an active region located in a portion of the electron gas is disclosed. The active region comprises an electron concentration less than an electron concentration of a set of non-active regions of the electron gas. The device includes a controlling terminal located on a first side of the active region. The device can comprise, for example, a field effect transistor (FET) in which the gate is located and used to control the carrier injection into the active region and define the boundary condition for the electric field distribution within the active region. The device can be used to generate, amplify, filter, and/or detect electromagnetic radiation of radio frequency (RF) and/or terahertz (THz) frequencies.

Abstract: A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier (SCR) that is electrically coupled to the output of a power amplifier; an ESD detection circuit that triggers the SCR responsive to detect an electrostatic discharge on an ESD bus; and an ESD clamp circuit that is coupled to the first voltage line.

Abstract: A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap.

Abstract: An electrostatic discharge (ESD) protection device includes a well region formed from semiconductor material with a first doping type and a floating base formed from semiconductor material with a second doping type. The floating base is disposed vertically above the well region. The ESD also includes a first terminal receiving region formed from semiconductor material with a third doping type. The first terminal receiving region is disposed vertically above the floating base. The ESD further includes a second terminal receiving region. The second terminal receiving region is laterally spaced apart from the first terminal receiving region by silicon trench isolation (STI) region. In some embodiments, the second terminal receiving region is formed from semiconductor material with the third doping type to form a bipolar junction transmitter (BJT) or with a fourth doping type to form a silicon controlled rectifier (SCR).

Abstract: A semiconductor device and its method of fabrication are described. A trench formed in a semiconductor substrate is partially filling said trench with a semiconductor material that lines a bottom and sides of the trench, leaving a gap in a middle of the trench running lengthwise along the trench. A first portion of the semiconductor material located below the gap is doped with dopants of a first conductivity type. The gap is filled with a dielectric material. Second portions of the semiconductor material located on the sides of the trench on both sides of the dielectric material are doped with dopants of a second conductivity type. The doping forms a P-N-P or N-P-N structure running lengthwise along the trench with differently doped regions located side by side across a width of the trench.

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.

Abstract: A silicon-controlled-rectifier (SCR) with adjustable holding voltage is disclosed, which comprises a heavily doped semiconductor layer and an epitaxial layer formed on the heavily doped semiconductor layer. A first N-well having a first P-heavily doped area is formed in the epitaxial layer. A second N-well or a first P-well is formed in the epitaxial layer. When the second N-well is formed in the epitaxial layer, a P-doped area is located between the first N-well and the second N-well. Besides, a first N-heavily doped area is formed in the second N-well or the first P-well. At least one deep isolation trench is formed in the epitaxial layer and located between the first P-heavily doped area and the first N-heavily doped area. A distance between the deep isolation trench and the heavily doped semiconductor layer is larger than zero.

Abstract: An allowable current amount of a ballast resistance is increased without increasing the width of the ballast resistance. At least one of resistances included in a ballast resistance has a first resistance and a second resistance. The first resistance extends in a first direction (X direction in FIG. 1) in which current flows in a protection element. The second resistance element is coupled in parallel to the first resistance element and extends in the first direction. The second resistance element and the first resistance element are located on the same straight line.

Abstract: Embodiments include methods for forming an electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, where the ESD protection device includes first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first and second widths. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vt1, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.

Abstract: An ESD protection device is manufactured such that its ESD characteristics are easily adjusted and stabilized. The ESD protection device includes an insulating substrate, a cavity provided in the insulating substrate, at least one pair of discharge electrodes each including an exposed portion that is exposed in the cavity, and external electrodes provided on a surface of the insulating substrate and connected to the discharge electrodes. Supporting electrodes obtained by dispersing conductive powder in an insulating material defining the insulating substrate are provided along a bottom surface and a top surface that define the cavity between the exposed portions of the at least one pair of discharge electrodes.

Abstract: An ESD protection device including second P-type wells, first P+-type doped regions, first N+-type doped regions and a P-type substrate having a first P-type well, an N-type well and an N-type deep well is provided. The second P-type wells are disposed in the N-type deep well. The first P+-type doped regions and the first N+-type doped regions are respectively disposed in the first P-type well, the N-type well and the second P-type wells in alternation. The first P+-type doped region in the N-type well and the N-type deep well are electrically connected to the first connection terminal. The doped regions in the first P-type well and the P-type substrate are electrically connected to the second connection terminal. The second P-type wells and the first N+-type doped regions therein form a diode string connected in series between the first N+-type doped region of the N-type well and the second connection terminal.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, including a first main surface and a second main surface opposite to each other. A power semiconductor element includes a first electrode in a first region at the first main surface of the semiconductor substrate, and a second electrode at the second main surface. A current flows between the first electrode and the second electrode. The semiconductor device also includes a guard ring of a second conductivity type, in a second region at the first main surface, at a more outer circumference than the first region. A semi-insulating insulation film covers the second region. A dielectric film in the second region covers the semi-insulating insulation film. A flow block portion in a third region at the first main surface, at a more outer circumference than the second region, prevents a flow out of the dielectric film.

Abstract: In a wireless tag with which a wireless communication system whose electric power of a carrier wave from a R/W is high, an overvoltage protection circuit is provided to prevent from generating excessive electric power in the wireless tag when the wireless tag receives excessive electric power. However, as noise is generated by operation of the overvoltage protection circuit, an error of reception occurs in receiving a signal whose modulation factor is small. To solve the problem, the maximum value of generated voltage in the wireless tag is held in a memory circuit after the overvoltage protection circuit operates, then the overvoltage protection circuit is controlled in accordance with the maximum value of generated voltage. The voltages at which the overvoltage protection circuit starts and stops operating are different from each other, and hysteresis occurs between the timing when the overvoltage protection circuit starts and stops operating.

Abstract: A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications.

Abstract: An optoelectronic device article comprises a substrate containing at least one electrically conductive microvia, at least one emitter diode and at least one ESD diode, optionally formed in situ, disposed in or on the substrate, and an electrically conductive path between the foregoing elements. A reflector cavity may be defined in the substrate for receiving the emitter diode(s), with retention elements on the substrate used to retain a lens material. High flux density and high emitter diode spatial density may be attained. Thermal sensors, radiation sensors, and integral heat spreaders comprising one or more protruding fins may be integrated into the article.

Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.

Abstract: In one embodiment, a bi-directional ESD device is formed to have a third harmonic at frequencies no less than about one gigahertz wherein the third harmonic has a magnitude that is no greater than about minus thirty five dBm.

Abstract: An ESD protection device is manufactured such that its ESD characteristics are easily adjusted and stabilized. The ESD protection device includes an insulating substrate, a cavity provided in the insulating substrate, at least one pair of discharge electrodes each including a portion exposed in the cavity, the exposed portions being arranged to face each other, and external electrodes provided on a surface of the insulating substrate and connected to the at least one pair of discharge electrodes. A particulate supporting electrode material having conductivity is dispersed between the exposed portions of the at least one pair of discharge electrodes in the cavity.

Abstract: A semiconductor device having a transistor and a rectifier includes: a current path; a first main electrode having a rectifying function and arranged on one end of the current path; a second main electrode arranged on the other end of the current path; an auxiliary electrode arranged in a region of the current path between the first main electrode and the second main electrode; a third main electrode arranged on the one end of the current path apart from the first main electrode along a direction intersecting the current path; and a control electrode arranged in a region of the current path between the second main electrode and the third main electrode. The transistor includes the current path, the second main electrode, the third main electrode, and the control electrode. The rectifier includes the current path, the first main electrode, the second main electrode, and the auxiliary electrode.

Abstract: A structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. The first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.

Abstract: In a gated diode ESD protection structure, the gate is split into two parts to divide the total reverse voltage between two gate regions.

Abstract: An electrostatic discharge (ESD) protection circuit includes at least one bipolar transistor. At least one isolation structure is disposed in a substrate. The at least one isolation structure is configured to electrically isolate two terminals of the at least one bipolar transistor. At least one diode is electrically coupled with the at least one bipolar transistor, wherein a junction interface of the at least one diode is disposed adjacent the at least one isolation structure.

Abstract: A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

Abstract: A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.

Abstract: A low voltage protection device that includes a silicon substrate comprises an inner layer of a first dopant type. The device also includes a first outer layer of a second dopant type disposed adjacent a first surface of the inner layer and a second outer layer of the second dopant type disposed adjacent a second surface of the inner layer opposite the first surface. The device further includes a first mesa region disposed in a peripheral region of a first side of the low voltage protection device. The first mesa region includes a first area that includes a peripheral portion of a cathode of the low voltage protection device, the cathode formed by diffusing a high concentration of dopant species of the first type on a first surface of the silicon substrate, and a second area comprising a high concentration of diffused dopant species of the second type.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.

Abstract: Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well.

Abstract: A semiconductor wafer including an electrostatic discharge (ESD) protective device, and methods for fabricating the same. In one aspect, the method includes forming a first semiconductor device in a first semiconductor die region on the semiconductor wafer; forming a second semiconductor device in a second semiconductor die region on the semiconductor wafer; and forming a protective device in a scribe line region between (i) the first semiconductor die region and (ii) the second semiconductor die region.

Abstract: A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.