Abstract: A protection structure against electrostatic discharges for a semiconductor electronic device that is integrated inside a well is disclosed, wherein the well is formed on a SOI substrate and isolated dielectrically by a buried oxide layer and an isolation structure, which isolation structure includes in turn at least a dielectric trench filled with a filler material. Advantageously, the protection structure is formed at the isolation structure.

Abstract: A multi-level metal interconnect structure and method for forming the same for improving a resistance of CMOS transistors to electrostatic discharge (ESD) transient events is disclosed. A semiconductor device including at least one NMOS transistor electrically connected along at least one circuit pathway to an input/output signal source and a reference voltage potential; and, electrically connecting at least the input/output signal source to the at least one NMOS transistor with a metal interconnect line extended in length by compacting at least a portion of the metal interconnect line length portion into a serpentine shape within a predetermined volume of the semiconductor device.

Abstract: An ESD protection device encompassing a vertical bipolar transistor that is connected as a diode and has an additional displaced base area. The assemblage has a space-saving configuration and a decreased difference between snapback voltage and breakdown voltage.

Abstract: ESD protection devices and methods of forming them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process and breakdown-enhanced layers, ESD protection devices with a lower trigger voltage are provided. The NMOS structure for ESD protection according to the present invention has islands, a control gate and breakdown-enhanced layers. These islands as well as the breakdown-enhanced layers overlapping the drain region of the NMOS reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

Abstract: In a high power input/output SOI semiconductor structure, the transistors thereof are laid out in a manner so that the high current density transistors, subject to the greatest heat buildup, are spaced apart in a manner as to avoid significant heat buildup.

Abstract: An n− type layer 12 is epitaxially grown on one main surface (front surface) of an n+ type silicon substrate 11 and an anode electrode 13 is electrically in contact with the other main surface (rear surface) thereof. A p type region 14 is selectively formed in a surface layer of the n− type layer 12 and a n+ type region 15 is selectively formed in a surface layer of the p type region 14. A cathode electrode 17 is electrically in contact with a surface of the n+ type region 15.

Abstract: A LSI has a plurality of separate power source systems, and an ESD protection circuit connected between ground lines of two of the power source systems. The protection circuit includes a pair of thyristors connected parallel to one another in opposite directions between the ground lines.

Abstract: A semiconductor thyristor device incorporates buried regions to achieve low breakover voltage devices, and the buried regions are offset laterally with respect to the emitter regions. The low voltage thyristor devices can be incorporated into five-pin protection modules for protecting customer circuits.

Abstract: A semiconductor device includes a grounded-gate n-channel field effect transistor (FET) between an I/O pad and ground (Vss) and/or Vcc for providing ESD protection. The FET includes a tap region of grounded p-type semiconductor material in the vicinity of the n+-type source region of the FET, which is also tied to ground, to make the ESD protection device less sensitive to substrate noise. The p-type tap region comprises either (i) a plurality of generally bar shaped subregions disposed in parallel relation to n+ source subregions, or, (ii) a region that is generally annular in shape and surrounds the n+ source region. The p-type tap region functions to inhibit or prevent snapback of the ESD device, particularly inadvertent conduction of a parasitic lateral npn bipolar transistor, resulting from substrate noise during programming operations on an EPROM device or in general used in situations where high voltages close to but lower than the snapback voltage are required in the pin.

Abstract: A semiconductor integrated device is provided which consists of a plurality of circuit blocks. Each circuit block is connected to a power supply terminal and a ground terminal. Signal interface sections connect signal circuits among the circuit blocks. A plurality of first diodes are serially connected to one another in a first direction between the ground terminal of a first one of the circuit blocks and the ground terminal of another of the circuit blocks. A plurality of second diodes are serially connected to one another in a second direction that is opposite to the first direction between the ground terminal of the first circuit block and the ground terminal of the another circuit block.

Abstract: The present invention provides an electrostatic discharge-protection device located between a pad and a specific voltage point. The electrostatic discharge-protection device has a P-type substrate. Then a first N-type well, a first P-type doped region, and a first N-type doped region, are formed on the P-type substrate, wherein the first P-type doped region and the first N-type doped region are coupled to the specific voltage point, respectively. A second P-type doped region and a second N-type doped region are formed on the first N-type well and are coupled to the pad, respectively. Moreover, a third N-type doped region and a fourth N-type doped region are formed on the P-type substrate. The third N-type doped region is coupled to the pad, and a second N-type well is formed between the third N-type doped region and the fourth N-type doped region.

Abstract: A protection circuit for protecting a semiconductor device from being damaged due to an excessively high applied voltage, includes a P-type MOS transistor provided between an external input-output terminal and a power supply line, an N-type MOS transistor provided between the P-type MOS transistor and a ground line, a first thyristor provided between the external input-output terminal and the ground line, the anode portion being connected to the external input-output terminal side, and the cathode portion being connected to the ground line, a second thyristor provided between the power supply line and the ground line, the anode portion being connected to the power supply line, and the cathode portion being connected to the ground line, and a resistance portion provided at a predetermined location of a conductor extending from a branch node between the P-type and N-type MOS transistors to the power supply line via the P-type MOS transistor.

Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure of the present invention uses a resistance capacitance (RC) circuit to distinguish an overshoot phenomenon caused by the instantaneous power-on from an ESD event, so as to prevent the ESD protection device, such as a P-type modified lateral silicon controlled rectifier (MLSCR), from being triggered unexpectedly by an overshoot phenomenon which results from the power-on under normal operation, and thereby the efficiency of the ESD protection device is promoted.

Abstract: An electrostatic discharge (ESD) protection circuit for protecting an internal device from an ESD is disclosed. The ESD protection circuit includes an NMOS transistor connected to a ground voltage terminal having silicide layers on a gate electrode and on source/drain regions thereof; and a PMOS transistor having a gate electrode connected to a ground voltage terminal and connecting the NMOS transistor to a pad.

Abstract: Edges of a slit and cut to length foil having a dielectric oxide film on at least one surface are edge formed by comprising anodizing the foil in an aqueous oxalic acid electrolyte, further edge a forming the foil in an aqueous citrate electrolyte, preferably dibasic ammonium citrate electrolyte, depolarizing the foil, and then edge forming the foil in an aqueous phosphate electrolyte, preferably an ammonium dihydrogen phosphate.

Abstract: A semiconductor device has a PN junction between first and second regions of the device in which in the intended operation of the device reverse breakdown of the junction occurs. The first region is of lower impurity concentration than the second region and a first buried region of the same conductivity type as and of higher impurity concentration than the first region is provided in the first region adjacent to the junction. A second buried region of the same conductivity type as and of higher impurity concentration than the first buried region is provided in the first buried region and one of the first and second buried regions is formed with a plurality of separate regions of small area arranged so that reverse breakdown of the junction preferentially occurs through the second buried region.

Abstract: A high voltage electrostatic discharge protection circuit having a virtual N+ region additionally formed according to the invention is disclosed. Due to the formation of the virtual N+ region, the distance between the base and collector of a parasitic bipolar junction transistor is greatly increased to keep its holding voltage always greater than its operation voltage, thereby preventing a problem of latch up.

Abstract: A semiconductor device with an electrostatic discharge (ESD) protective circuit is disclosed. In this semiconductor device with an ESD protective circuit, an n-well guard ring is formed around an NMOS field transistor of a data input buffer or around an NMOS transistor of a data output buffer. The n-well guard ring is strapped to an n-well of a PMOS field transistor and to an n-well of a PMOS transistor, and thus a PNPN path is formed toward the PMOS transistor at a positive mode of the ground voltage. Therefore, the electrical resistance between the wells of the NMOS transistors and the PMOS transistors can be reduced, thereby improving the characteristics of the ESD protective circuit and a latch-up device. Further the layout area is reduced, and thus, the characteristics and the reliability of the semiconductor device are improved.

Abstract: On a semiconductor integrated circuit chip, multiple equipotential power-line conductors are provided to supply power to circuit elements. First protecting elements are provided for interconnecting the power-line conductors for protecting the circuit elements. A number of input/output pads are also connected to the power-line conductors via second protecting elements. The arrangement is such that the contact positions of any of the first protecting elements and any of the second protecting elements on the power-line conductors are nearer to respective end portions of the conductors than the contact position of any of the circuit elements on the conductors. Each of the contact positions serves as a dividing point for dividing a high potential electrostatic charge into at least two low potential charges.

Abstract: A semiconductor device having a SOI structure in which an ESD resistance can be enhanced is obtained. The semiconductor device comprises PMOS transistors Q21 and Q22 which are brought into a forward bias state if a positive high voltage is applied as a surge voltage to a signal terminal 30, and NMOS transistors Q11 and Q12 which are brought into the forward bias state if a negative high voltage is applied as the surge voltage to the signal terminal 30. Furthermore, if a normal operation signal is applied from the signal terminal 30, all the NMOS transistors Q11 and Q12 and the PMOS transistors Q21 and Q22 are brought into an OFF state.

Abstract: A trench gate type semiconductor device with a current sensing cell is composed so that the orientation of crystal face at side walls of trenches forming channels of trench gates in a main cell is equal or almost equal, or equivalent or almost equivalent to the orientation of crystal face at side walls of trenches forming channels of trench gates in a current sensing cell, which brings the same performance to the main and sense cells, whereby the high accuracy current sensing can be realized.

Abstract: A voltage-driven power semiconductor device includes a voltage-driven IEGT chip, a collector electrode plate, an emitter electrode plate, and an inductance material. The collector electrode plate is connected to the collector of the IEGT chip, and press-contacts the IEGT chip from its collector side. The emitter electrode plate press-contacts the IEGT chip from its emitter side. The inductance material has an inductance component and connects the emitter of the IEGT chip and the emitter electrode plate. In the voltage-driven power semiconductor device having this arrangement, an induced electromotive force is generated in the inductance material arranged between the emitter of the IEGT chip and the emitter electrode plate. This induced electromotive force can suppress a steep current change (di/dt) upon an OFF operation, and can further suppress a steep voltage change (dv/dt) caused by the current change (di/dt).

Abstract: A static self-locking micro-circuit-breaker includes a first MOS depletion transistor of a first type connected by its drain to a first main terminal and by its gate to a second main terminal, a second MOS depletion transistor of second type connected by its drain to the second main terminal and by its source to the source of the first transistor, a third MOS depletion transistor of the first type connected by its drain to the first main terminal, by its gate to the second main terminal, and by its source to the gate of the second transistor.

Abstract: The present invention relates to a component protecting against electric overloads likely to occur on a conductor in series with which is placed a detection resistor. The component includes a first cathode-gate thyristor and a second anode-gate thyristor, of the gate current or forward break-over type. The anode region of the first thyristor, formed on the lower surface side, is separate from the isolating wall surrounding the thyristor and the rear surface of the isolating wall is coated with a portion of an insulating layer.

Abstract: A semiconductor component has a semiconductor body with at least one integrated lateral resistor. The lateral resistor is formed with a dopant concentration in the resistor region. The resistor region is located in a region which is accessible from the surface of the semi-conductor component and it has a defined dopant concentration. Scattering centers are provided in the region of the lateral resistor which reduce a temperature dependency of the lateral resistor.

Abstract: Disclosed is a floating gate neuron MOS transistor that may be incorporated into devices such as low voltage silicon control rectifiers for protection of internal circuits against electrostatic discharge. The transistor includes two or more input gates capacitively coupled to the floating gate. By adjusting the coupling ratio of the input gates, it is possible to control the transistor drain turn-on voltage very precisely and thereby turn on the rectifier without relying on avalanche breakdown of the transistor.

Abstract: An electrostatic discharge protection circuit comprises a semiconductor layer of a first conductivity type, a floating semiconductor layer of a second conductivity type, a first doped region of the first conductivity type, a first doped region of the second conductivity type, a second doped region of the second conductivity type, a gate structure, and a second doped region of the first conductivity type. The floating semiconductor layer of a second conductivity type is in contact with the semiconductor layer of a first conductivity type to establish a junction therebetween. The first doped region of the first conductivity type is formed in the semiconductor layer of a second conductivity type and connected to a first node. The first doped region of the second conductivity type is formed in the semiconductor layer of a first conductivity type and connected to a second node. The second doped region of the second conductivity type spans the junction.

Abstract: A semiconductor device has a substrate bias generating circuit for generating a substrate bias to be applied to a p-type semiconductor substrate, a CMOS circuit formed on the semiconductor substrate, and a latch-up protection circuit. The latch-up protection circuit has an n-type first region, a highly doped n-type second region, a p-type third region apart from the second region, in the first region and an n-type fourth region surrounding said first region formed apart from the first region on the surface of the substrate. The second region is coupled with a power supply Vcc, the third region is coupled with an input line, the fourth region is coupled with a ground Vss, and the substrate is coupled with the substrate bias generating circuit.

Abstract: An ESD protected semiconductor circuit and the ESD protection circuit. The protected circuit includes a terminal, a semiconductor device coupled to the terminal and an ESD protection circuit. The ESD protection circuit includes a substrate of a first conductivity type and has a surface. A first well of conductivity type opposite to the first conductivity type is disposed within the substrate and extends to the surface. A second well of the first conductivity type is disposed within the first well and is spaced from the substrate and extending to the surface. A third region of the opposite conductivity type is disposed within the second well and is spaced from the first well and extending to the surface. At least one of the substrate or the third region is coupled to the terminal.

Abstract: An output buffer in a CMOS circuit includes an output pad; a VDD line which supplies a first supply voltage; a VSS line which supplies a second supply voltage; a first MOS device connected between the VDD line and the output pad; a second MOS device connected between the VSS line and the output pad; a lateral SCR device connected from the output pad to one of the VDD and VSS lines and in parallel with one of the first and second MOS devices; and a bypass diode connected to one of the VDD and VSS lines and in parallel with the lateral SCR device.

Abstract: In a diode, the backward length L of an anode electrode in a region, where a semiconductor layer of a p.sup.+ conductivity type and an anode electrode do not contact each other, is made longer than the diffusion length of holes in a semiconductor layer of an n.sup.- conductivity type for obtaining a large critical di/dt.

Abstract: A circuit for protecting a bonding pad of a semiconductor device from ESD voltages is located under the pad to permit the space otherwise used for a protection circuit to be used for normal operating components. The protection circuit has a compact layout that provides maximum ability to handle an ESD current within this limited space. The semiconductor structure for the circuit has separate parts for two SCR circuits, one for each polarity of ESD current. Each SCR circuit comprises two symmetrical SCR structures.

Abstract: In accordance with the invention, an integrated circuit has a first ESD protection circuit for each input pin which is not adjacent a non-wired IC pin and a second ESD protection circuit for each input pin which is adjacent a non-wired pin. The second ESD protection circuit has a greater ESD protection capability than the first ESD protection circuit. The second ESD protection circuit has a capability of protecting an input pin when an ESD stress occurs at an adjacent non-wired pin. The second ESD protection circuit includes, for example, additional ESD protection elements in comparison to the first ESD protection circuit. Alternatively, the second ESD protection circuit has one ESD protection element which is larger in size or is otherwise different than a corresponding ESD protection element in the first ESD protection circuit.

Abstract: It is an abject to stably and surely perform protection operation of devices. Since the gate threshold voltage V.sub.GE(th)S in a sense IGBT cell constituting a sensing circuit is set to have a higher value than the gate threshold voltage V.sub.GE(th)M in a main IGBT cell constituting a main circuit, a finite time .DELTA.t is required from when the gate voltage V.sub.GE reaches the gate threshold voltage V.sub.GE(th)M until when it reaches the gate threshold voltage V.sub.GE(th)S in the turn-on period. Accordingly, the rise of the main current Is of the sensing circuit is delayed from the main current Im of the main circuit. As a result, surge current does not appear in the current Is. As the surge current does not appear in the main current of the sensing circuit, a protection circuit of the device operates stably, and breakdown of the device is surely prevented.

Abstract: A gateless thyristor or a gateless triac with shorting holes having a sharp switching threshold and a high current value I.sub.H includes, a first area having a first density of shorting holes and a second area having a second density of shorting holes lower than the first density.

Abstract: A protection circuit against the electrostatic discharges that could appear at the terminals of a circuit, wherein said protection circuit comprises a first transistor made in a well whose potential is a floating potential and enabling the value of the discharge voltage to be limited to a value equal to minus the value of the threshold voltage of said first transistor and a second transistor made in a well whose potential is a floating potential and enabling the value of the discharge voltage to be limited to a value equal to the value of the threshold voltage of said second transistor. The disclosure can be applied to MOS technology integrated circuits.

Abstract: A current limiter component constituted by a semiconductor bar or wafer doped in four layers (P, N, P, N) between its anode and cathode. The doping characteristics and the dimensional characteristics of the bar are adjusted to obtain a characteristic current to voltage curve which initially increases as voltage and current increases in the manner of a diode followed by a part constituting a current limiting plateau wherein the plateau reflects that the current remains fixed until the voltage reaches a breakdown voltage.

Abstract: An integrated circuit device includes internal power supply buses V.sub.SSI, and V.sub.DDI, and output power supply buses V.sub.SSO, and V.sub.DDO. An output driver of the device has an active p-channel pull up, and n-channel pulldown complementary pair configuration with their outputs tied to a common node, which is in turn tied to an I/O pad. A protection circuit for protecting the device from ESD events includes a series resistor disposed between the source of the n-channel pulldown transistor, and power supply bus V.sub.SSO. The protection circuitry includes a diode having its cathode connected to the I/O pad, and its anode connected to power supply bus V.sub.SSI. The pulldown transistor includes an n.sup.+ drain region, which is shared with the diode, wherein the diode and transistor are merged. The resistor between the pulldown transistor source, and power supply V.sub.SSO permits maintaining this merged structure. In an alternate embodiment, an n-well may be formed to underlie the p.sup.

Abstract: A method of forming an ESD protection device with reduced breakdown voltage, simultaneously with an integrated circuit which includes FET devices, and the resultant device structure, are described. A silicon substrate is provided on which there are field oxide regions, gates, and active regions. A first ion implant of a conductivity-imparting dopant is performed in a vertical direction into the active regions of the ESD protection device and the FET devices. A first insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The first insulating layer is patterned to create spacers adjacent to the gates of both the ESD protection device and the FET devices. A second ion implant of a conductivity-imparting dopant with higher concentration than dopant from the first ion implant is performed into active regions of both the ESD protection device and the FET devices.

Abstract: An insulated-gate bipolar transistor is formed of a number of cells integrally formed on a semiconductor substrate. The cells includes main cells with emitter electrodes, and current detection sensing cells situated adjacent to the main cells. Emitter electrodes are formed in an area of the sensing cells to be separated from the emitter electrodes of the main cells, and an overcurrent protection circuit is connected to the emitter electrodes of the sensing cells. When shorting accident occurs, an overcurrent protecting operation is performed such that an overcurrent is accurately detected through the sensing cells and a main current flowing through the main cells is made smaller than a short-circuit withstanding capacity of the IGBT by gate control of the protection circuit.

Abstract: An ESD protection circuit which provides protection for CMOS devices against ESD potentials of up to about 10 kV is provided. The ESD protection circuit is able to provide protection against both positive-going and negative-going high energy electrical transients, and is able to maintain a high impedance state when driven to a voltage beyond the supply rails of CMOS integrated circuit, but less than tile breakdown voltage of the ESD protection circuit. The ESD protection circuit routes currents associated with ESD potentials to a predetermined arbitrary point which may be selected during the fabrication process to meet the needs of a particular application. The structure of the ESD protection circuit permits the holding current to be adjusted to accommodate the current capacity of various external circuits.

Abstract: A gateless thyristor or a gateless triac with shorting holes having a sharp switching threshold and a high current value I.sub.H includes, a first area having a first density of shorting holes and a second area having a second density of shorting holes lower than the first density.

Abstract: A MOS transistor for protection against electrostatic discharge includes a semiconductor substrate; an island including a source region and a drain region provided in the semiconductor substrate; an isolation region provided in the semiconductor substrate so as to surround the island; a gate insulating layer provided on the semiconductor substrate; a gate electrode provided on the gate insulating layer; and a distributing device for distributing an electric current generated by an electrostatic voltage applied to the drain region into the drain region.

Abstract: A readily manufacturable field controlled thyristor with a first semiconductor region of n-type conductivity, a second semiconductor region of p-type in contact with said first region, a void penetrating through said first and second semiconductor regions, a fourth semiconductor region of n-type forming a channel adjacent to said void, a fifth semiconductor region, of p-type, in contact with said third region. The device has a large tolerance for deviations in process parameter precision and accuracy, which enables the device to be produced at a low cost.

Abstract: A semi-insulating compound semiconductor device includes an input terminal portion having a protection diode connected thereto and an element formation region and which is provided with a conduction region having the highest potential in the semiconductor device disposed between the input terminal portion and the element formation region. With such an arrangement, low-frequency oscillation of the drain current I.sub.D or drain conductance g.sub.m due to a leak age current from the protection diode connected to the input terminal portion can be prevented from occurring and thus the semi-insulating compound semiconductor device can operate satisfactorily with stabilized characteristics.

Abstract: A protective circuit for connecting contacts of monolithic integrated circuits, particularly CMOS input/output stages. The protective circuit has a four-layer device (ta, ts) with a defined switching threshold in the area of each connecting contact (A) and a low-resistivity current path (sa) from the connecting contact (A) to a supply terminal (VSS, VDD). The protective circuit also contains devices (zw2, z5) which prevent or provide a bypass for any undesired flow of current (i3, i4) between at least parts of the four-layer device and triggerable circuit regions (W2).