Device Protection (e.g., From Overvoltage) Patents (Class 257/173)
  • Patent number: 10727327
    Abstract: Fabrication methods and device structures for a silicon controlled rectifier. A cathode is arranged over a top surface of a substrate and a well is arranged beneath the top surface of the substrate. The cathode is composed of a semiconductor material having a first conductivity type, and the well also has the first conductivity type. A semiconductor layer, which has a second conductivity type opposite to the first conductivity type, includes a section over the top surface of the substrate. The section of the semiconductor layer is arranged to form an anode that adjoins the well along a junction.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Rahul Mishra, Vibhor Jain, Ajay Raman, Robert J. Gauthier
  • Patent number: 10720422
    Abstract: A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: July 21, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 10700057
    Abstract: The disclosed embodiments include an ESD robust transistor with a compound-SCR protection. The transistor may include a semiconductor substrate having a first conductivity type, a drain region coupled with the semiconductor substrate having a drain SCR component with a first drain region of the first conductivity type and a second drain region of the second conductivity type. The transistor may also include a source coupled with the semiconductor substrate, a channel region of the second conductivity type, and a gate coupled with the channel region having SCR components with a first gate region of the first conductivity type and a second gate region of the second conductivity type. The drain SCR components and the gate SCR components may create a low resistance discharge path along the channel region that activates in response to the ESD such that the ESD discharges through the transistor without causing damage to the transistor.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: June 30, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Arash Elhami Khorasani, Mark Griswold
  • Patent number: 10685954
    Abstract: A silicon controlled rectifier includes a P-type substrate, an N-type doped well, a first P-type strip-shaped heavily-doped area arranged in the N-type doped well, a first N-type strip-shaped heavily-doped area arranged in the P-type substrate, and at least one N-type heavily-doped area arranged in the P-type substrate and the N-type doped well. The at least one N-type heavily-doped area is not arranged between the first P-type strip-shaped heavily-doped area and the first N-type strip-shaped heavily-doped area, thus the surface area of a semiconductor substrate can be reduced. The conductivity types of the abovementioned components are alternatively changed.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 16, 2020
    Assignee: Amazing Microelectronic Corp.
    Inventors: Yu-Shu Shen, Pin-Hui Lee
  • Patent number: 10665584
    Abstract: A well-less Transient Voltage Suppressor (TVS) Silicon-Controlled Rectifier (SCR) has a P+ anode region that is not in an N-well. The P+ anode region 20 is surrounded by N+ isolation regions near the surface, and a deep N+ region underneath that is formed in a p-substrate. A N+ cathode region is formed in the p-substrate. The deep N+ region has a doping of 5×1018 to 5×1019/cm3, compared to a doping of 1×1016/cm3 for a typical N-well, or a doping of 1×1013 to 1×1015/cm3 for the p-substrate. The high doping in the deep N+ region causes a recombination current that can shunt half of the anode current. Since the deep N+ region is much shallower than an N-well, the sidewall capacitance is greatly reduced, allowing for higher speed applications.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 26, 2020
    Assignee: Hong Kong Applied Science and Technology Research Insstitute Company, Limited
    Inventors: Chenyue Ma, Chun-Kit Yam, Xiao Huo
  • Patent number: 10573637
    Abstract: Various aspects of the disclosure are directed to circuitry that may be used to shunt current. As may be consistent with one or more embodiments a first circuit has a plurality of alternating p-type and n-type semiconductor regions with respective p-n junctions therebetween, arranged between an anode end and a cathode end. A second (e.g., bypass) circuit is connected to one of the alternating p-type and n-type semiconductor regions, and forms a further p-n junction therewith. The second circuit operates to provide carrier flow, which influences operation of the first circuit.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: February 25, 2020
    Assignee: Nexperia B.V.
    Inventors: Steffen Holland, Hans-Martin Ritter
  • Patent number: 10573712
    Abstract: The present disclosure relates to a super-junction structure, a method for manufacturing the super-junction structure and a semiconductor device including the super-junction structure. The super-junction structure includes an epitaxy layer of a first doping type and a plurality of first pillar regions of a second doping type which are formed in the epitaxy layer and are separated from each other. Each of the first pillar regions has a doping concentration that decreases from bottom to top. A portion of the epitaxy layer between adjacent ones of the first pillar regions is a second pillar region. The first pillar regions and the second pillar region are arranged alternatively to form the super-junction structure. The first pillar regions are characterized by the doping concentration that decreases from bottom to top so that the super-junction structure has a relatively high breakdown voltage and a relatively low on resistance.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: February 25, 2020
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventors: He Sun, Zhongping Liao
  • Patent number: 10546813
    Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, James J. Demarest, Christopher J. Penny, Christopher J. Waskiewicz
  • Patent number: 10497696
    Abstract: An electrostatic discharge (ESD) protection device includes a first bi-directional silicon controlled rectifier having a doped well of a first conductivity type, a buried doped layer having a second conductivity type opposite the first conductivity type, first and second highly doped regions of the second conductivity type in the doped well, and a third highly doped region of the first conductivity type in the doped well. The first, second and third highly doped regions are connected to a first node. A first transistor in the doped well includes an emitter coupled to the first highly doped region, a collector coupled to a conductive line in the buried doped layer, and a base coupled to the third highly doped region. A second transistor in the doped well includes an emitter coupled to the second highly doped region, a collector coupled to the conductive line in the buried doped layer, and a base coupled to the third highly doped region.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: December 3, 2019
    Assignee: NXP USA, Inc.
    Inventors: Rouying Zhan, Patrice Besse, Alain Salles
  • Patent number: 10475849
    Abstract: A device including a plurality of interconnected concentric coplanar diodes.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: November 12, 2019
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Hubert Bono, Jonathan Garcia
  • Patent number: 10453793
    Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, James J. Demarest, Christopher J. Penny, Christopher J. Waskiewicz
  • Patent number: 10453836
    Abstract: A method of forming a LDMOS with a self-aligned P+ implant and LVPW region at the source side and the resulting device are provided. Embodiments include forming a DNWELL in a p-sub; forming a PWHV in the DNWELL; forming an NW in the DNWELL; forming a LVPW in the PWHV; forming STI structures through the LVPW and through the DNWELL and NW, respectively; forming a gate over the PWHV; forming a first and a second P+ implant in the LVPW, an edge of the second P+ implant aligned with an edge of the gate; forming a first N+ implant in the LVPW between the first STI structure and the second P+ implant and a second N+ in the NW adjacent to the second STI structure; and forming contacts over the first and second P+ and N+ implants, respectively, and an electrical contact over the second N+ implant.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: October 22, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yohann Frederic Michel Solaro, Vvss Satyasuresh Choppalli, Chai Ean Gill
  • Patent number: 10447033
    Abstract: An electrostatic discharge (ESD) protection device with a high holding voltage is disclosed including at least an ESD clamp coupled to a holding voltage tuning circuit. The ESD clamp may be coupled to the holding voltage tuning circuit through a connection circuit such as a diode. The ESD clamp may be implemented by a first silicon controlled rectifier (SCR) and the holding voltage tuning circuit may be implemented as a second SCR.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: October 15, 2019
    Assignee: SOFICS BVBA
    Inventor: Sven Van Wijmeersch
  • Patent number: 10418806
    Abstract: A safety protection circuit is described, comprising a fuse, a first voltage detection circuit, a first Silicon-Controlled Rectifier, SCR, wherein the first SCR is triggered upon detection of a threshold voltage by the first voltage detection circuit, a second voltage detection circuit, and a second SCR, wherein the second SCR is triggered upon detection of a threshold voltage by the second voltage detection circuit.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: September 17, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Juan Luis Lopez Rodriguez, David Soriano Fosas, Marc Soler Jauma
  • Patent number: 10396174
    Abstract: A method for manufacturing a fin-type diode includes providing a substrate structure including a substrate, first and second sets of fins on the substrate, an isolation region between the first and second sets of fins and having an upper surface lower than an upper surface of the first and second set of fins, a well region partially in the substrate and overlapping the first and second sets of fins. The method also includes forming a dielectric layer on the first and second sets of fins, forming a dummy gate structure covering the dielectric layer on an end of the second set of fins and the upper surface of the isolation region, doping the first set of fins to form a first doped region, and doping the second set of fins and a portion of the well region below the second set of fins to form a second doped region.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 27, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10374234
    Abstract: A battery electrode assembly includes a current collector with conduction barrier regions having a conductive state in which electrical conductivity through the conduction barrier region is permitted, and a safety state in which electrical conductivity through the conduction barrier regions is reduced. The conduction barrier regions change from the conductive state to the safety state when the current collector receives a short-threatening event. An electrode material can be connected to the current collector. The conduction barrier regions can define electrical isolation subregions. A battery is also disclosed, and methods for making the electrode assembly, methods for making a battery, and methods for operating a battery.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: August 6, 2019
    Assignee: UT-BATTELLE LLC
    Inventors: Michael Naguib Abdelmalak, Srikanth Allu, Nancy J. Dudney, Jianlin Li, Srdjan Simunovic, Hsin Wang
  • Patent number: 10366974
    Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes a bipolar transistor device connected between a first node and a second node, a series protection device connected in series with the bipolar transistor device, and a diode device connected between the second node and a third node. A drain terminal of an NMOS device to be protected is connectable to the first node. A body of the NMOS device to be protected is connectable to the second node. A source terminal of the NMOS device to be protected is connectable to the third node. The diode device and the bipolar transistor device are configured to form a parasitic silicon controlled rectifier. Other embodiments are also described.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: July 30, 2019
    Assignee: NXP B.V.
    Inventors: Gijs Jan de Raad, Da-Wei Lai
  • Patent number: 10361247
    Abstract: A device including a plurality of interconnected concentric coplanar diodes.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: July 23, 2019
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Hubert Bono, Jonathan Garcia
  • Patent number: 10355019
    Abstract: A semiconductor device includes a substrate, a first transistor, a first diode structure, and a second diode structure. The first transistor is disposed on the substrate. The first transistor includes a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is connected to the substrate by the first diode structure. The first drain electrode is connected to the substrate by the second diode structure. The first diode structure and the second diode structure may be used to improve potential unbalance in the transistor, and operation performance and reliability of the semiconductor device may be enhanced accordingly.
    Type: Grant
    Filed: July 1, 2018
    Date of Patent: July 16, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Xiang Li, Ding-Lung Chen, Yu-Cheng Tung
  • Patent number: 10304820
    Abstract: An ESD protection apparatus includes first and second parasitic bipolar junction transistors having different majority carriers formed in a substrate and an ESD protection device having a grounding end and a connecting end connected to the first parasitic bipolar junction transistor. When an ESD voltage applied to the ESD protection apparatus is greater than a ground voltage, a first current is grounded by passing through one of a first assembled protecting circuit including the first parasitic bipolar junction transistor and the ESD protection device and a second assembled protecting circuit including the first and the second parasitic bipolar junction transistor; and when an ESD voltage applied to the ESD protection apparatus is less than a ground voltage, a second current coming from a ground is directed to a voltage source by passing through the other one of the first assembled protecting circuit and the second assembled protecting circuit.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 28, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Yu Wang, Wen-Tsung Huang
  • Patent number: 10283648
    Abstract: A fuse device is formed by a PN junction semiconducting region that is electrically insulated from other portions of an integrated circuit. The fuse device includes a first semiconducting zone having P type of conductivity and a second semiconducting zone having N type of conductivity in contact at a PN junction. First and second electrically conducting contact zones are provided on the first and second semiconducting zone, respectively, without making contact with the PN junction. One of the first and second semiconducting zones is configured with a non-homogeneous concentration of dopants, where a region with a lower value of concentration of dopant is located at the PN junction and a region with a higher value of concentration of dopant is locates at the corresponding electrically conducting contact zone.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 7, 2019
    Assignee: STMicroelectronic (Rousset) SAS
    Inventor: Pascal Fornara
  • Patent number: 10256338
    Abstract: A semiconductor device includes a semiconductor substrate, a first epitaxial layer of a first conductivity type, a first semiconductor region of the first conductivity type, a second epitaxial layer of a second conductivity type, a second semiconductor region of the first conductivity type, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode; and a gate electrode pad. The first semiconductor region is not provided beneath the gate electrode pad.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 9, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeharu Koga
  • Patent number: 10217738
    Abstract: A semiconductor device includes a semiconductor substrate, a base region formed in the semiconductor substrate on a front surface side thereof, a gate trench extending from a front surface side of the base region and penetrating thorough the base region, and a dummy trench extending from the front surface side of the base region and penetrating thorough the base region, where a portion of the dummy trench that extends beyond a back surface of the base region is longer than a portion of the gate trench that extends beyond the back surface of the base region.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 26, 2019
    Assignee: SMK Corporation
    Inventor: Tatsuya Naito
  • Patent number: 10211199
    Abstract: A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: February 19, 2019
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 10211198
    Abstract: Methods, circuits, devices, and systems for high voltage electrostatic discharge (ESD) protection are provided. An example ESD protection device includes: a base well of a first dopant type on a substrate, a first well of the first dopant type in the base well, a second well of a second dopant type in the base well, a first highly doped region of the first dopant type and a second highly doped region of the second dopant type in the first well, a third highly doped region of the second dopant type in the second well, and a fourth highly doped region of the first dopant type in the third highly doped region. The first highly doped region and the second highly doped region are coupled to a first voltage terminal, and the third highly doped region and the fourth highly doped region are coupled to a second voltage terminal.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: February 19, 2019
    Assignee: Macronix International Co., Ltd.
    Inventors: Tzu-Yi Hung, Hsin-Liang Chen
  • Patent number: 10211152
    Abstract: A semiconductor device includes a first line pattern and a second line pattern formed in parallel on a semiconductor substrate, third line patterns formed in parallel between the first line pattern and the second line pattern, fourth line patterns formed in parallel between the first line pattern and the second line pattern, a first connection structure configured to couple a first of the third line patterns with a first of the fourth lines patterns, which are adjacent to the first line pattern, and a second connection structure configured to couple a second of the first lines patterns with a second of the fourth lines patterns, which are adjacent to the second line pattern.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: February 19, 2019
    Assignee: SK Hynix Inc.
    Inventor: Yong Chul Shin
  • Patent number: 10211299
    Abstract: Provided is a semiconductor device including a semiconductor substrate; a gate trench portion formed in a front surface of the semiconductor substrate; a dummy trench portion formed in the front surface of the semiconductor substrate; and a first front-surface-side electrode that includes metal and is formed above the front surface of the semiconductor substrate. The gate trench portion includes a gate trench formed in the front surface of the semiconductor substrate; a gate conducting portion formed inside the gate trench; and a gate insulating portion that is formed above the gate conducting portion inside the gate trench and provides insulation between the gate conducting portion and the first front-surface-side electrode. The dummy trench portion includes a dummy trench formed in the front surface of the semiconductor substrate; and a dummy conducting portion that is formed inside the dummy trench and contacts the first front-surface-side electrode.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 19, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10205031
    Abstract: All resistors configuring a resistance voltage dividing circuit are formed by alternately arranging an N-type polycrystalline silicon and a P-type polycrystalline silicon and connecting the same in parallel or in series. The respective resistors themselves cancel a stress received from a resin upon packaging of the resistance voltage dividing circuit since the N-type polycrystalline silicon and the P-type polycrystalline silicon respectively indicate a shift amount in a reverse direction with respect to a stress. There can hence be provided a resistance voltage dividing circuit in which a variation in voltage division ratio at packaging is reduced than before.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: February 12, 2019
    Assignee: ABLIC Inc.
    Inventor: Yukimasa Minami
  • Patent number: 10199482
    Abstract: An apparatus includes an electrostatic discharge (ESD) protection device configured to protect a circuit from ESD conditions. The protection device includes an emitter region having a first diffusion polarity; a collector region laterally spaced apart from the emitter region, and having the first diffusion polarity; and a barrier region interposed laterally between the emitter region and the collector region while contacting the emitter region. The barrier region has a second diffusion polarity opposite from the first diffusion polarity. The device can further include a base region having the second diffusion polarity, and laterally surrounding and underlying the emitter region and the barrier region. The barrier region can have a higher dopant concentration than the base region, and block a lateral current flow between the collector and emitter regions, thus forming a vertical ESD device having enhanced ESD performance.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: February 5, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: David Clarke, Paul Daly, Patrick McGuinness, Bernard Stenson, Anne Deignan
  • Patent number: 10157816
    Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: December 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Mattias E. Dahlstrom
  • Patent number: 10157904
    Abstract: A transient voltage suppressor (TVS) is constructed as an NPN bipolar transistor including individually optimized collector-base and emitter-base junctions both with avalanche mode breakdown. The TVS device is constructed using a base that includes a lightly doped base region bordered by a pair of more heavily doped base regions. The two more heavily doped base regions are used to form the collector-base junction and the emitter-base junction both as avalanche breakdown junctions. The lightly doped base region between the collector-base and emitter-base doping regions ensures low leakage current in the TVS device. In this manner, the TVS bipolar transistor of the present invention provides high surge protection with robust clamping while ensuring low leakage current.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 18, 2018
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Shekar Mallikarjunaswamy, Ning Shi
  • Patent number: 10128202
    Abstract: Disclosed are an electrostatic protection structure, array substrate and display device. The electrostatic protection structure includes a first electrostatic protection unit and a second electrostatic protection unit which are disposed in sequence. One end of the first electrostatic protection unit is connected with a first electrostatic beginning end, and another end of the first electrostatic protection unit is connected with an electrostatic discharge end; the second electrostatic protection unit includes a first conduction structure, of which one end is connected with a second electrostatic beginning end and another end is connected with an electrostatic terminating end. The second electrostatic beginning end is a outflow end for static electricity, the first conduction structure is configured to disconnect from the second electrostatic beginning end and/or said electrostatic terminating end when static electricity passes the first conduction structure.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 13, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Pan Li, Hongfei Cheng, Yong Qiao, Jian Xu, Yongda Ma
  • Patent number: 10074567
    Abstract: A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer encapsulating the polycrystalline substrate, and a bonding layer coupled to the barrier layer. The method further includes forming a first silicon layer coupled to the bonding layer, forming a dielectric layer coupled to the first silicon layer, forming a second silicon layer coupled to the dielectric layer, forming a GaN layer coupled to the second silicon layer, forming a GaN based device coupled to the GaN layer, removing the engineered substrate to expose a back surface of the first silicon layer, forming a silicon based device coupled to the back surface of the first silicon layer, forming a via from the back surface of the first silicon layer, filling the via with a conducting material, and interconnecting the GaN based device and the silicon based device through the via.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: September 11, 2018
    Assignee: QROMIS, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens
  • Patent number: 10056340
    Abstract: An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and a dialectic layer formed on the top face of the chip beside and on top of said first metal layer; wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip; and wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: August 21, 2018
    Assignee: HRL Laboratories, LLC
    Inventors: Hasan Sharifi, Keisuke Shinohara, Mary C. Montes, Charles McGuire, Wonill Ha, Jason May, Hooman Kazemi, Jongchan Kang, Robert G. Nagele
  • Patent number: 10032861
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: July 24, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Madhur Bobde
  • Patent number: 10008489
    Abstract: An electrostatic discharge protection semiconductor device includes a substrate, a gate set positioned on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the drain region, and at least a second doped region formed in the substrate. The source region and the drain region include a first conductivity type, the first doped region and the second doped region include a second conductivity type, and the first conductivity and the second conductivity type are complementary to each other. The first doped region and the second doped region are electrically connected to each other.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Chen Chang
  • Patent number: 10002959
    Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a source contact, the source contact including a first and second source contact portion, and a gate electrode in a gate trench in the first main surface adjacent to a body region. The body region and a drift zone are disposed along a first direction parallel to the first main surface between the source region and a drain region. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region, the first source contact portion further including a portion of the semiconductor substrate between the source conductive material and the second source contact portion. The semiconductor device further includes a temperature sensor in the semiconductor substrate.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: June 19, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 9997454
    Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, James J. Demarest, Christopher J. Penny, Christopher J. Waskiewicz
  • Patent number: 9991336
    Abstract: An anode electrode and a cathode electrode formed on a silicon semiconductor substrate, p-type layer formed next to the anode electrode, an n-type layer formed next to the cathode electrode by a V-group element being diffused, an n? layer formed between the p-type layer and the n-type layer, and an n-buffer layer formed between the n? layer and the n-type layer and containing oxygen are provided and an oxygen concentration in an area of a width of at least 30 ?m from a surface on a side of the n-type layer of the cathode electrode toward the anode electrode is set to 1×1017 cm?3 or more and also the oxygen concentration of the n? layer in a position in contact with the p-type layer is set to less than 3×1017 cm?3.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: June 5, 2018
    Assignee: Hitachi Power Semiconductor Device Ltd.
    Inventors: Masatoshi Wakagi, Taiga Arai, Mutsuhiro Mori, Tomoyasu Furukawa
  • Patent number: 9978842
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first electrode, a second electrode, a control electrode and an insulating film. The first semiconductor region is of a first conductivity type and includes SiC. The second semiconductor region is provided on the first semiconductor region and has a first surface. The second semiconductor region is of a second conductivity type and includes SiC. The third semiconductor region is provided on the second semiconductor region, is of the first conductivity type and includes SiC. The first and second electrodes are electrically connected to the third semiconductor region. The control electrode is provided on the second semiconductor region. The insulating film is provided between the second semiconductor region and the control electrode. The insulating film contacts the first surface and the control electrode and includes nitrogen.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: May 22, 2018
    Assignees: Kabushiki Kaisha Toshiba, National Institute of Advanced Industrial Science and Technology, FUJI ELECTRIC CO., LTD.
    Inventors: Keiko Ariyoshi, Tatsuo Shimizu, Takashi Shinohe, Junji Senzaki, Shinsuke Harada, Takahito Kojima
  • Patent number: 9972615
    Abstract: A semiconductor device for ESD protection, includes a drain region, a first doped region, a second doped region and a source region. The drain region is disposed in a substrate at a first side of a gate and the drain region has a first conductivity type. The first doped region is disposed in a second doped well at a second side of the gate and has a second conductivity type. The source region is also disposed in the second doped well and has the first conductive type, and the source region surrounds the first doped region from a topview. The second doped region is disposed in the second doped well and has the second conductive type, and the second doped region is disposed between the gate and the source region, wherein a plurality of contacts is electrically connected to the second doped region.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 15, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jhih-Ming Wang, Li-Cih Wang, Tien-Hao Tang
  • Patent number: 9960251
    Abstract: An ESD protection structure comprising a first semiconductor region of a first doping type, a second semiconductor region of the first doping type, a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the first and second semiconductor regions of the first doping type, and a first contact region of the second doping type formed within a surface of the second semiconductor region. A thyristor structure is formed within the ESD protection structure comprising the first contact region of the second doping type, the second semiconductor region of the first doping type, the semiconductor structure of the second doping type, and the first semiconductor region of the first doping type. Wherein no contact region is formed within a surface of the semiconductor structure of the second doping type between the first and second semiconductor regions of the first doping type.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: May 1, 2018
    Assignee: NXP USA, Inc.
    Inventors: Jean Philippe Laine, Patrice Besse
  • Patent number: 9929141
    Abstract: In one aspect, a silicon-controlled rectifier (SCR) includes a Zener diode embedded in the SCR. In another aspect, a laterally diffused metal oxide semiconductor (LDMOS) includes a Zener diode embedded in the LDMOS. In a further aspect, a lateral insulated-gate bipolar transistor (IGBT) includes a Zener diode embedded in the IGBT.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: March 27, 2018
    Assignee: Allegro MicroSystems, LLC
    Inventors: Chung C. Kuo, Maxim Klebanov
  • Patent number: 9921443
    Abstract: A display device includes a substrate including an array area in which an image is displayed and a pad area in which an image is not displayed, gate lines in the array area and elongated in a first direction on the substrate, gate lines pads in the pad area and respectively electrically connected to the gate lines, floating patterns disposed in the pad area, a first shorting bar in the pad area and with which electrostatic energy from the floating patterns is dissipated; and first shorting bar lines in the pad area and defined by first lines respectively connected to the floating patterns and second lines spaced apart from the first lines and connected to the first shorting bar, wherein ends of the second lines respectively face ends of the first lines.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: March 20, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joo Hong Seo, Tae Hee Lee
  • Patent number: 9911682
    Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: March 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Mattias E. Dahlstrom
  • Patent number: 9905636
    Abstract: The present disclosure relates to a super-junction structure, a method for manufacturing the super-junction structure and a semiconductor device including the super-junction structure. The super-junction structure includes an epitaxy layer of a first doping type and a plurality of first pillar regions of a second doping type which are formed in the epitaxy layer and are separated from each other. Each of the first pillar regions has a doping concentration that decreases from bottom to top. A portion of the epitaxy layer between adjacent ones of the first pillar regions is a second pillar region. The first pillar regions and the second pillar region are arranged alternatively to form the super-junction structure. The first pillar regions are characterized by the doping concentration that decreases from bottom to top so that the super-junction structure has a relatively high breakdown voltage and a relatively low on resistance.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: February 27, 2018
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventors: He Sun, Zhongping Liao
  • Patent number: 9887446
    Abstract: A signal transmission cable including a high-Q value band-elimination filter includes a first signal line conductor pattern including a first capacitor conductor portion and an inductor conductor portion on a first base layer. The first capacitor conductor portion includes a flat conductor, and the inductor conductor portion has a spiral shape. A second signal line conductor pattern including a second capacitor conductor portion is provided on a second base layer. The inductor conductor portion constitutes an inductor, and the first and second capacitor conductor portions and the first base layer constitute a capacitor. The inductor and the capacitor are connected in parallel by transmission conductor portions on the first and second base layers and an interlayer-connector conductor on the first base layer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: February 6, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kuniaki Yosui
  • Patent number: 9881914
    Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: January 30, 2018
    Assignee: SOFICS BVBA
    Inventors: Bart Sorgeloos, Benjamin Van Camp, Sven Van Wijmeersch, Wim Vanhouteghem
  • Patent number: 9871031
    Abstract: A semiconductor device includes a P-type substrate, and an N-well in the P-type substrate. A first N+ diffusion region is located in the P-type substrate, and a first P+ diffusion region is located in the N-well. A second P+ diffusion region is located across a boundary between the P-type substrate and the N-well. A first gate electrode overlies the N-well between the first P+ diffusion regions and the second P+ diffusion region. A second gate electrode overlies the P-type substrate between the second P+ diffusion region and the first N+ diffusion region. The first P+ diffusion region, the N-well, the P-type substrate, and the first N+ diffusion region form an SCR (Silicon-Controlled rectifier) device. The first P+ diffusion region, the second P+ diffusion region, and the first gate electrode form a PMOS transistor. The second P+ diffusion region, the first N+ diffusion region, and the second gate electrode form a gated diode.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: January 16, 2018
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Yi Liu, Jun Wang, Ying Ma, Bin Lu, Huijuan Cheng
  • Patent number: RE47147
    Abstract: An ESD protection device is provided which experiences only small increases in discharge start voltage and discharge protection voltage and relatively free of scorching or peeling at the ends of the discharge electrodes thereof even if a discharge repeatedly occurs. The ESD protection device has an insulating substrate with a cavity, and in the cavity first and second discharge electrodes are so disposed that the ends thereof face each other with a gap therebetween. A first outer electrode is on the outer surface of the insulating substrate and electrically connected to the first discharge electrode, and a second outer electrode is on the outer surface of the insulating substrate and electrically connected to the second discharge electrode. The ends of the first and second discharge electrodes are thicker than any other portion of the first and second discharge electrodes.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: November 27, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yoshihito Otsubo