Device Protection (e.g., From Overvoltage) Patents (Class 257/173)
  • Patent number: 11437365
    Abstract: A semiconductor substrate of a first conductivity type is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is formed an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are provided in the semiconductor layer. A second region of the second conductivity type is formed in the first well. A third region of the second conductivity type is formed in the second well. The first well, the semiconducting layer, the second well and the third region form a first lateral thyristor. The second well, the semiconductor layer, the first well and the second region form a second lateral thyristor. The buried region and semiconductor substrate form a zener diode which sets the trigger voltage for the lateral thyristors.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: September 6, 2022
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Eric Laconde, Olivier Ory
  • Patent number: 11430781
    Abstract: In an embodiment, a semiconductor die includes a transistor device that has a cell field and an edge termination region, a source pad arranged on the cell field, a gate pad laterally arranged laterally adjacent the cell field and in the edge termination region, a shielding region laterally surrounding the cell field, the shielding region including a non-depletable doped. The polysilicon ESD protection diode is arranged laterally between the gate pad and the source pad and vertically above at least a portion of the shielding region, and includes at least two separate sections that are electrically coupled in parallel between the gate pad and the source pad. The sections are laterally spaced apart by a gap situated at a corner of the gate pad.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: August 30, 2022
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventor: Joachim Weyers
  • Patent number: 11362203
    Abstract: Electrical overstress protection for electronic systems subject to electromagnetic compatibility fault conditions are provided herein. In certain implementations, a stacked thyristor protection structure with a high holding voltage includes a protection device having a trigger voltage and a holding voltage. A trigger voltage of the stacked thyristor protection structure is substantially equal to the trigger voltage of the protection device. The stacked thyristor protection structure further includes at least one resistive thyristor electrically connected to the protection device and operable to increase a holding voltage of the stacked thyristor protection structure relative to the holding voltage of the protection device. The at least one resistive thyristor comprising a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and a conductor connecting a collector of the PNP bipolar transistor to a collector of the NPN bipolar transistor.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 14, 2022
    Assignee: Analog Devices, Inc.
    Inventors: Javier A. Salcedo, Linfeng He
  • Patent number: 11316063
    Abstract: According to various embodiments, there is provided a diode device including a semiconductor substrate of a first conductivity type, a first semiconductor region formed within the semiconductor substrate, an epitaxial region of the first conductivity type, and a second semiconductor region of a second conductivity type different from the first conductivity type. The first semiconductor region includes a chalcogen. The epitaxial region is formed over the first semiconductor region. The second semiconductor region is formed over the epitaxial region.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: April 26, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sandipta Roy, Khee Yong Lim, Lanxiang Wang, Kiok Boone Elgin Quek, Jing Hua Michelle Tng
  • Patent number: 11296072
    Abstract: A semiconductor substrate includes a doped region having an upper surface. The doped region may comprise a conduction terminal of a diode (such as cathode) or a transistor (such as a drain). A silicide layer is provided at the doped region. The silicide layer has an area that only partially covers an area of the upper surface of the doped region. The partial area coverage facilitates modulating the threshold voltage and/or leakage current of an integrated circuit device.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 5, 2022
    Assignee: STMicroelectronics SA
    Inventors: Thomas Bedecarrats, Louise De Conti, Philippe Galy
  • Patent number: 11296071
    Abstract: A device of protection against electrostatic discharges is formed in a semiconductor substrate of a first conductivity type that is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is positioned at an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are formed in the semiconductor layer and a region of the second conductivity type is formed in the second well. A stop channel region of the second conductivity type is provided in the semiconductor layer to laterally separating the first well from the second well, where no contact is present between this stop channel region and either of the first and second wells.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: April 5, 2022
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Eric Laconde, Olivier Ory
  • Patent number: 11233394
    Abstract: An electrostatic protection circuit that is electrically connected to a first terminal to which a first voltage signal is input, a second terminal to which a second voltage signal is input, and a connection terminal that is connected to an external circuit, and mitigates the influence of a surge voltage on an internal circuit, the electrostatic protection circuit including: a first protection circuit that is electrically connected to the first terminal and the second terminal; and a second protection circuit that is electrically connected to the first terminal and the connection terminal, and the second protection circuit including: a first diode element whose anode is electrically connected to the connection terminal, and whose cathode is electrically connected to the first terminal, a thyristor element whose cathode is electrically connected to the connection terminal, a voltage limiting element that is electrically connected to an anode of the thyristor element, and a trigger element that is electrically c
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: January 25, 2022
    Inventor: Masuhide Ikeda
  • Patent number: 11233045
    Abstract: A transient voltage suppression device includes a substrate; a first conductivity type well region disposed in the substrate and comprising a first well and a second well; a third well disposed on the substrate, a bottom part of the third well extending to the substrate; a fourth well disposed in the first well; a first doped region disposed in the second well; a second doped region disposed in the third well; a third doped region disposed in the fourth well; a fourth doped region disposed in the fourth well; a fifth doped region extending from inside of the fourth well to the outside of the fourth well, a portion located outside the fourth well being located in the first well; a sixth doped region disposed in the first well; a seventh doped region disposed below the fifth doped region and in the first well.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: January 25, 2022
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Shikang Cheng, Yan Gu, Sen Zhang
  • Patent number: 11221253
    Abstract: A semiconductor device may include a plurality of single-photon avalanche diodes (SPADs). The semiconductor device may include sensing single-photon avalanche diodes that are sensitive to incident light and dark single-photon avalanche diodes that are shielded from incident light. The dark single-photon avalanche diodes may be used to measure one or more parameters for the semiconductor device such as breakdown voltage, dark count rate, and quench resistance. Processing circuitry may optimize a bias voltage for the semiconductor device based on information regarding one or more sensor parameters obtained using the dark single-photon avalanche diodes.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: January 11, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jan Ledvina, Ivan Koudar, Dariusz Piotr Palubiak
  • Patent number: 11222888
    Abstract: An anti-static metal oxide semiconductor field effect transistor structure includes an anti-static body structure and a slave metal oxide semiconductor field effect transistor, the anti-static body structure includes: a main metal oxide semiconductor field effect transistor; a first silicon controlled rectifier, an anode thereof being connected to a drain of the main metal oxide semiconductor field effect transistor, a cathode and a control electrode thereof being connected to a source of the main metal oxide semiconductor field effect transistor; and a second silicon controlled rectifier, an anode thereof being connected to the drain of the main metal oxide semiconductor field effect transistor, a cathode thereof being connected to a gate of the main metal oxide semiconductor field effect transistor, a control electrode thereof being connected to the source or the gate of the main metal oxide semiconductor field effect transistor.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: January 11, 2022
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Jun Sun
  • Patent number: 11152352
    Abstract: A dual mode snap back circuit device is disclosed. The dual mode snap back device may be used for electrostatic discharge (ESD) protection, and may provide both positive ESD protection and negative ESD protection. The dual mode snap back device may implement both an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., a gate-grounded NMOS transistor, such as a gate-grounded extended drain NMOS (GGEDNMOS) transistor) to provide protection against positive ESD events and a bipolar junction transistor (BJT) (e.g., a PNP BJT) to provide protection against negative ESD events. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Akm Ahsan, Mark Armstrong, Guannan Liu
  • Patent number: 11139287
    Abstract: A transient voltage suppression (TVS) device including a TVS diode having a first electrode and a second electrode, an insulating plate disposed on the first electrode, a first terminal lead connected to the insulating plate, a second terminal lead connected to the second electrode, and an thermal cutoff element connecting the first terminal lead to the first electrode, the thermal cutoff element configured to melt and break an electrical connection between the first terminal lead and the first electrode when a temperature of the TVS diode exceeds a predetermined safety temperature.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: October 5, 2021
    Assignee: Littefluse Semiconductor (WUXI) Co., Ltd.
    Inventors: Chuanfang Chin, Kueir-Liang Lu, Lei Shi, Tsungwen Mou
  • Patent number: 11127733
    Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection lay
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: September 21, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andre Schmenn, Stefan Pompl, Damian Sojka, Katharina Umminger
  • Patent number: 11121126
    Abstract: An embodiment of a silicon controlled rectifier (SCR) includes a semiconductor body, an active device region, and a device isolation region configured to electrically insulate the active device region from neighboring active device regions. First SCR regions and a second SCR region of a first conductivity type are in the active device region. A first pn-junction or Schottky junction is formed at an interface between the first SCR regions and the second SCR region. A first plurality of the first SCR regions and sub-regions of the second SCR region are alternately arranged and directly adjoin one another. A second pn-junction is formed at an interface between the second SCR region and a third SCR region of a second conductivity type. A third pn-junction is formed at an interface between the third SCR region and a fourth SCR region of the first conductivity type.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: September 14, 2021
    Assignee: Infineon Technologies AG
    Inventors: Christian Cornelius Russ, Markus Eckinger, Kai Esmark
  • Patent number: 11114993
    Abstract: A high frequency multilayer filter may include a plurality of dielectric layers and a signal path having an input and an output. The multilayer filter may include an inductor including a conductive layer formed over a first dielectric layer. The inductor may be electrically connected at a first location with the signal path and electrically connected at a second location with at least one of the signal path or a ground. The multilayer filter may include a capacitor including a first electrode and a second electrode that is separated from the first electrode by a second dielectric layer. The multilayer filter has a characteristic frequency that is greater than about 6 GHz.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: September 7, 2021
    Assignee: AVX Corporation
    Inventors: Kwang Choi, Marianne Berolini
  • Patent number: 11107883
    Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 31, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Raja Selvaraj, Anant Shankar Kamath, Byron Lovell Williams, Thomas D. Bonifield, John Kenneth Arch
  • Patent number: 11088134
    Abstract: A symmetrical layout technique for an electrostatic discharge ESD device and a corresponding power supply network is presented. The ESD device protects an electronic circuit against an overvoltage or overcurrent and contains a first contact area to establish an electrical contact with a first supply rail, a second contact area to establish an electrical contact with a second supply rail, and a third contact area to establish an electrical contact with a third supply rail. The first and third supply rails provide a first supply voltage, and the second supply rail provides a second supply voltage. Within the ESD device, an axis of symmetry passes through the second contact area, and the first contact area and the third contact area are arranged on opposite sides with regard to the axis of symmetry. The symmetrical layout technique allows flipping the orientation of the ESD device with regard to the supply rails.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: August 10, 2021
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Marcus Peitz
  • Patent number: 11049853
    Abstract: An electronic device includes a silicon-on-insulator (SOI) structure, and an electrostatic discharge (ESD) protection device, with an isolation layer having a thickness and extending in a trench from a first implanted region. The ESD protection device includes a conductive field plate that extends over a portion of the first implanted region and past the first implanted region and over a portion of the isolation layer by an overlap distance that is 3.5 to 5.0 times the thickness of the isolation layer. In one example, the ESD protection device has a finger or racetrack shape, and the first implanted region and a second implanted region extend around first and second turn portions of the finger shape.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: June 29, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Christopher Boguslaw Kocon
  • Patent number: 11011304
    Abstract: A multilayer electronic component includes: a multilayer stack including a plurality of dielectric layers and a plurality of conductor layers stacked together; a plurality of terminals integrated with the multilayer stack; and a shield formed of a conductor and integrated with the multilayer stack. The multilayer stack has a top surface, a bottom surface, and four side surfaces connecting the top surface and the bottom surface. The plurality of terminals are provided on the bottom surface of the multilayer stack. The shield entirely covers the top surface and the four side surfaces of the multilayer stack. The shield includes a portion that is thicker than the other portions of the shield.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: May 18, 2021
    Assignee: TDK CORPORATION
    Inventors: Shohei Kusumoto, Noriaki Ootsuka, Minoru Abe, Yoshinori Sato
  • Patent number: 10998308
    Abstract: A semiconductor device has a protected node and a reference node, and a bi-directional ESD structure electrically coupled between the protected node and the reference node. The bi-directional ESD structure includes a main transistor electrically coupled between the protected node and the reference node, an upper control transistor with current nodes electrically coupled between the protected node and a control node of the main transistor, and a lower control transistor with current nodes electrically coupled between the reference node and a control node of the main transistor. The bi-directional ESD structure also includes an upper trigger network configured to provide a transient on-state signal to the upper control transistor from a positive electrical pulse on the protected node. The bi-directional ESD structure further includes a lower trigger network configured to provide a transient on-state signal to the lower control transistor from a negative electrical pulse on the protected node.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: May 4, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xianzhi Dai, Muhammad Yusuf Ali
  • Patent number: 10978869
    Abstract: A MOSFET and an electrostatic discharge (ESD) protection device on a common chip includes a MOSFET with a source, a gate, and a drain, and an ESD protection device configured to implement a diode function that is biased to prevent current from flowing through the common chip from the source to the drain.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: April 13, 2021
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 10916538
    Abstract: The present technology relates to a semiconductor device and a manufacturing method therefor, a solid-state imaging element and electronic equipment that make it possible to suppress breakdown of a side wall insulating film by charge damage to suppress short-circuiting. The semiconductor device according to an aspect of the present technology includes a first semiconductor substrate on which a given circuit is formed, a second semiconductor substrate, and through electrodes that electrically connect the first semiconductor substrate and the second semiconductor substrate to each other. The through electrode is formed such that a through-hole is opened through a protection diode structure formed in the first semiconductor substrate, an insulating film is deposited on a side wall of the through-hole, and an electrode material is then filled inside the through-hole in which the insulating film is deposited. The present technology can be applied, for example, to a CMOS image sensor.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: February 9, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hiroshi Takahashi
  • Patent number: 10897246
    Abstract: RF switching circuitry includes a plurality of FETs coupled between an input node, an output node, and a gate drive node. When a positive power supply voltage is provided at the gate drive node, the plurality of FETs turn on and provide a low impedance path between the input node and the output node. When a negative power supply voltage is provided at the gate drive node, the plurality of FETs turn off and provide a high impedance path between the input node and the output node. Switch acceleration circuitry in the RF switching circuitry includes a bypass FET and multi-level driver circuitry. The bypass FET selectively bypasses the common resistor in response to a multi-level drive signal. The multi-level driver circuitry uses a built-in gate to capacitance of the bypass FET to provide the multi-level drive signal at an overvoltage that is above the positive power supply voltage.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: January 19, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Padmmasini Desikan, Dirk Robert Walter Leipold
  • Patent number: 10854710
    Abstract: A semiconductor device includes a first transistor formed on a substrate and including first and second impurity regions, a second transistor formed on the substrate and including a third impurity region electrically connected to the second impurity region, and a fourth impurity region, a power supply terminal electrically connected to the first impurity region, a ground terminal electrically connected to the fourth impurity region, a first guard ring surrounding the first transistor in a plan view and electrically connected to the ground terminal, and a second guard ring surrounding the second transistor in a plan view and electrically connected to the ground terminal. A conductivity type of the first through fourth impurity regions is different from a conductivity type of the first and second guard rings. The second guard ring has a width narrower than a width of the first guard ring in a plan view.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: December 1, 2020
    Assignee: SOCIONEXT, INC.
    Inventor: Hidetoshi Tanaka
  • Patent number: 10833068
    Abstract: The present disclosure provides a semiconductor device that prevents a resistor component connected in series with a base electrode from the electrostatic damage.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: November 10, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Akihiko Tsubaki, Kanako Deguchi
  • Patent number: 10819320
    Abstract: An arrangement (100) is disclosed, comprising an electrical pulse generating module (10) configured to generate at least one electrical pulse, and a transformer (20) electrically connected to the electrical pulse generating module (10). The electrical pulse generating module (10) comprises an electrical energy storage module (40) that can be charged or discharged, and a switch unit (50) controllably switchable between at least a conducting state and a non-conducting state. When the switch unit (50) is switched into the non-conducting state, a power supply (30) charges the electrical energy storage module (40) by way of a charging current. When the switch unit (50) is switched into the conducting state, the electrical energy storage module (40) is discharged to create an electrical pulse to be received by the transformer (20).
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: October 27, 2020
    Assignee: ScandiNova Systems AB
    Inventor: Klas Elmquist
  • Patent number: 10804220
    Abstract: In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Kong-Beng Thei, Meng-Han Lin
  • Patent number: 10784551
    Abstract: A band-pass filter includes a main body, five resonators, a shield, and a partition. The main body is formed of a dielectric. The partition is formed of a conductor. The five resonators are configured so that capacitive coupling is established between every two of the resonators adjacent to each other in circuit configuration. Each of the five resonators includes a resonator conductor portion. A first stage resonator and a fifth stage resonator are magnetically coupled to each other although not adjacent to each other in circuit configuration. The partition extends to pass between the respective resonator conductor portions of the first stage resonator and the fifth stage resonator, and is electrically connected to the shield.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: September 22, 2020
    Assignee: TDK CORPORATION
    Inventors: Yuta Ashida, Noriyuki Hirabayashi, Shigemitsu Tomaki
  • Patent number: 10727327
    Abstract: Fabrication methods and device structures for a silicon controlled rectifier. A cathode is arranged over a top surface of a substrate and a well is arranged beneath the top surface of the substrate. The cathode is composed of a semiconductor material having a first conductivity type, and the well also has the first conductivity type. A semiconductor layer, which has a second conductivity type opposite to the first conductivity type, includes a section over the top surface of the substrate. The section of the semiconductor layer is arranged to form an anode that adjoins the well along a junction.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Rahul Mishra, Vibhor Jain, Ajay Raman, Robert J. Gauthier
  • Patent number: 10720422
    Abstract: A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: July 21, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 10700057
    Abstract: The disclosed embodiments include an ESD robust transistor with a compound-SCR protection. The transistor may include a semiconductor substrate having a first conductivity type, a drain region coupled with the semiconductor substrate having a drain SCR component with a first drain region of the first conductivity type and a second drain region of the second conductivity type. The transistor may also include a source coupled with the semiconductor substrate, a channel region of the second conductivity type, and a gate coupled with the channel region having SCR components with a first gate region of the first conductivity type and a second gate region of the second conductivity type. The drain SCR components and the gate SCR components may create a low resistance discharge path along the channel region that activates in response to the ESD such that the ESD discharges through the transistor without causing damage to the transistor.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: June 30, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Arash Elhami Khorasani, Mark Griswold
  • Patent number: 10685954
    Abstract: A silicon controlled rectifier includes a P-type substrate, an N-type doped well, a first P-type strip-shaped heavily-doped area arranged in the N-type doped well, a first N-type strip-shaped heavily-doped area arranged in the P-type substrate, and at least one N-type heavily-doped area arranged in the P-type substrate and the N-type doped well. The at least one N-type heavily-doped area is not arranged between the first P-type strip-shaped heavily-doped area and the first N-type strip-shaped heavily-doped area, thus the surface area of a semiconductor substrate can be reduced. The conductivity types of the abovementioned components are alternatively changed.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 16, 2020
    Assignee: Amazing Microelectronic Corp.
    Inventors: Yu-Shu Shen, Pin-Hui Lee
  • Patent number: 10665584
    Abstract: A well-less Transient Voltage Suppressor (TVS) Silicon-Controlled Rectifier (SCR) has a P+ anode region that is not in an N-well. The P+ anode region 20 is surrounded by N+ isolation regions near the surface, and a deep N+ region underneath that is formed in a p-substrate. A N+ cathode region is formed in the p-substrate. The deep N+ region has a doping of 5×1018 to 5×1019/cm3, compared to a doping of 1×1016/cm3 for a typical N-well, or a doping of 1×1013 to 1×1015/cm3 for the p-substrate. The high doping in the deep N+ region causes a recombination current that can shunt half of the anode current. Since the deep N+ region is much shallower than an N-well, the sidewall capacitance is greatly reduced, allowing for higher speed applications.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 26, 2020
    Assignee: Hong Kong Applied Science and Technology Research Insstitute Company, Limited
    Inventors: Chenyue Ma, Chun-Kit Yam, Xiao Huo
  • Patent number: 10573637
    Abstract: Various aspects of the disclosure are directed to circuitry that may be used to shunt current. As may be consistent with one or more embodiments a first circuit has a plurality of alternating p-type and n-type semiconductor regions with respective p-n junctions therebetween, arranged between an anode end and a cathode end. A second (e.g., bypass) circuit is connected to one of the alternating p-type and n-type semiconductor regions, and forms a further p-n junction therewith. The second circuit operates to provide carrier flow, which influences operation of the first circuit.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: February 25, 2020
    Assignee: Nexperia B.V.
    Inventors: Steffen Holland, Hans-Martin Ritter
  • Patent number: 10573712
    Abstract: The present disclosure relates to a super-junction structure, a method for manufacturing the super-junction structure and a semiconductor device including the super-junction structure. The super-junction structure includes an epitaxy layer of a first doping type and a plurality of first pillar regions of a second doping type which are formed in the epitaxy layer and are separated from each other. Each of the first pillar regions has a doping concentration that decreases from bottom to top. A portion of the epitaxy layer between adjacent ones of the first pillar regions is a second pillar region. The first pillar regions and the second pillar region are arranged alternatively to form the super-junction structure. The first pillar regions are characterized by the doping concentration that decreases from bottom to top so that the super-junction structure has a relatively high breakdown voltage and a relatively low on resistance.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: February 25, 2020
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventors: He Sun, Zhongping Liao
  • Patent number: 10546813
    Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, James J. Demarest, Christopher J. Penny, Christopher J. Waskiewicz
  • Patent number: 10497696
    Abstract: An electrostatic discharge (ESD) protection device includes a first bi-directional silicon controlled rectifier having a doped well of a first conductivity type, a buried doped layer having a second conductivity type opposite the first conductivity type, first and second highly doped regions of the second conductivity type in the doped well, and a third highly doped region of the first conductivity type in the doped well. The first, second and third highly doped regions are connected to a first node. A first transistor in the doped well includes an emitter coupled to the first highly doped region, a collector coupled to a conductive line in the buried doped layer, and a base coupled to the third highly doped region. A second transistor in the doped well includes an emitter coupled to the second highly doped region, a collector coupled to the conductive line in the buried doped layer, and a base coupled to the third highly doped region.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: December 3, 2019
    Assignee: NXP USA, Inc.
    Inventors: Rouying Zhan, Patrice Besse, Alain Salles
  • Patent number: 10475849
    Abstract: A device including a plurality of interconnected concentric coplanar diodes.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: November 12, 2019
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Hubert Bono, Jonathan Garcia
  • Patent number: 10453793
    Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, James J. Demarest, Christopher J. Penny, Christopher J. Waskiewicz
  • Patent number: 10453836
    Abstract: A method of forming a LDMOS with a self-aligned P+ implant and LVPW region at the source side and the resulting device are provided. Embodiments include forming a DNWELL in a p-sub; forming a PWHV in the DNWELL; forming an NW in the DNWELL; forming a LVPW in the PWHV; forming STI structures through the LVPW and through the DNWELL and NW, respectively; forming a gate over the PWHV; forming a first and a second P+ implant in the LVPW, an edge of the second P+ implant aligned with an edge of the gate; forming a first N+ implant in the LVPW between the first STI structure and the second P+ implant and a second N+ in the NW adjacent to the second STI structure; and forming contacts over the first and second P+ and N+ implants, respectively, and an electrical contact over the second N+ implant.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: October 22, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yohann Frederic Michel Solaro, Vvss Satyasuresh Choppalli, Chai Ean Gill
  • Patent number: 10447033
    Abstract: An electrostatic discharge (ESD) protection device with a high holding voltage is disclosed including at least an ESD clamp coupled to a holding voltage tuning circuit. The ESD clamp may be coupled to the holding voltage tuning circuit through a connection circuit such as a diode. The ESD clamp may be implemented by a first silicon controlled rectifier (SCR) and the holding voltage tuning circuit may be implemented as a second SCR.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: October 15, 2019
    Assignee: SOFICS BVBA
    Inventor: Sven Van Wijmeersch
  • Patent number: 10418806
    Abstract: A safety protection circuit is described, comprising a fuse, a first voltage detection circuit, a first Silicon-Controlled Rectifier, SCR, wherein the first SCR is triggered upon detection of a threshold voltage by the first voltage detection circuit, a second voltage detection circuit, and a second SCR, wherein the second SCR is triggered upon detection of a threshold voltage by the second voltage detection circuit.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: September 17, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Juan Luis Lopez Rodriguez, David Soriano Fosas, Marc Soler Jauma
  • Patent number: 10396174
    Abstract: A method for manufacturing a fin-type diode includes providing a substrate structure including a substrate, first and second sets of fins on the substrate, an isolation region between the first and second sets of fins and having an upper surface lower than an upper surface of the first and second set of fins, a well region partially in the substrate and overlapping the first and second sets of fins. The method also includes forming a dielectric layer on the first and second sets of fins, forming a dummy gate structure covering the dielectric layer on an end of the second set of fins and the upper surface of the isolation region, doping the first set of fins to form a first doped region, and doping the second set of fins and a portion of the well region below the second set of fins to form a second doped region.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 27, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10374234
    Abstract: A battery electrode assembly includes a current collector with conduction barrier regions having a conductive state in which electrical conductivity through the conduction barrier region is permitted, and a safety state in which electrical conductivity through the conduction barrier regions is reduced. The conduction barrier regions change from the conductive state to the safety state when the current collector receives a short-threatening event. An electrode material can be connected to the current collector. The conduction barrier regions can define electrical isolation subregions. A battery is also disclosed, and methods for making the electrode assembly, methods for making a battery, and methods for operating a battery.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: August 6, 2019
    Assignee: UT-BATTELLE LLC
    Inventors: Michael Naguib Abdelmalak, Srikanth Allu, Nancy J. Dudney, Jianlin Li, Srdjan Simunovic, Hsin Wang
  • Patent number: 10366974
    Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes a bipolar transistor device connected between a first node and a second node, a series protection device connected in series with the bipolar transistor device, and a diode device connected between the second node and a third node. A drain terminal of an NMOS device to be protected is connectable to the first node. A body of the NMOS device to be protected is connectable to the second node. A source terminal of the NMOS device to be protected is connectable to the third node. The diode device and the bipolar transistor device are configured to form a parasitic silicon controlled rectifier. Other embodiments are also described.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: July 30, 2019
    Assignee: NXP B.V.
    Inventors: Gijs Jan de Raad, Da-Wei Lai
  • Patent number: 10361247
    Abstract: A device including a plurality of interconnected concentric coplanar diodes.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: July 23, 2019
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Hubert Bono, Jonathan Garcia
  • Patent number: 10355019
    Abstract: A semiconductor device includes a substrate, a first transistor, a first diode structure, and a second diode structure. The first transistor is disposed on the substrate. The first transistor includes a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is connected to the substrate by the first diode structure. The first drain electrode is connected to the substrate by the second diode structure. The first diode structure and the second diode structure may be used to improve potential unbalance in the transistor, and operation performance and reliability of the semiconductor device may be enhanced accordingly.
    Type: Grant
    Filed: July 1, 2018
    Date of Patent: July 16, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Xiang Li, Ding-Lung Chen, Yu-Cheng Tung
  • Patent number: 10304820
    Abstract: An ESD protection apparatus includes first and second parasitic bipolar junction transistors having different majority carriers formed in a substrate and an ESD protection device having a grounding end and a connecting end connected to the first parasitic bipolar junction transistor. When an ESD voltage applied to the ESD protection apparatus is greater than a ground voltage, a first current is grounded by passing through one of a first assembled protecting circuit including the first parasitic bipolar junction transistor and the ESD protection device and a second assembled protecting circuit including the first and the second parasitic bipolar junction transistor; and when an ESD voltage applied to the ESD protection apparatus is less than a ground voltage, a second current coming from a ground is directed to a voltage source by passing through the other one of the first assembled protecting circuit and the second assembled protecting circuit.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 28, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Yu Wang, Wen-Tsung Huang
  • Patent number: 10283648
    Abstract: A fuse device is formed by a PN junction semiconducting region that is electrically insulated from other portions of an integrated circuit. The fuse device includes a first semiconducting zone having P type of conductivity and a second semiconducting zone having N type of conductivity in contact at a PN junction. First and second electrically conducting contact zones are provided on the first and second semiconducting zone, respectively, without making contact with the PN junction. One of the first and second semiconducting zones is configured with a non-homogeneous concentration of dopants, where a region with a lower value of concentration of dopant is located at the PN junction and a region with a higher value of concentration of dopant is locates at the corresponding electrically conducting contact zone.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 7, 2019
    Assignee: STMicroelectronic (Rousset) SAS
    Inventor: Pascal Fornara
  • Patent number: 10256338
    Abstract: A semiconductor device includes a semiconductor substrate, a first epitaxial layer of a first conductivity type, a first semiconductor region of the first conductivity type, a second epitaxial layer of a second conductivity type, a second semiconductor region of the first conductivity type, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode; and a gate electrode pad. The first semiconductor region is not provided beneath the gate electrode pad.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 9, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeharu Koga