Abstract: In a plasma processing apparatus, a ceiling electrode plate provided to face a substrate holding stage via a process space contacts and is supported by an electrode support by interposing a cooling plate, and a heat-transfer sheet is provided in a contact surface between the ceiling electrode plate and the cooling plate. The heat-transfer sheet has thermal conductivity of 0.5 to 2.0 W/m·K. The heat-transfer sheet is provided of a heat-resistant adhesive agent or a rubber including silicon, or the heat-transfer sheet is formed of a ceramic filler including oxide, nitride, or carbide. The ceramic filler of 25 to 60 volume % is contained in the heat-resistant adhesive agent or the rubber. A thickness of the heat-transfer sheet is in a range between 30 and 80 ?m, and the heat-transfer sheet is not provided in a predetermined area around gas holes of the ceiling electrode plate.

Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress may be escaped. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board served as current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and crack of the cover plate.

Abstract: A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.

Abstract: A light emitting device includes a plurality of chips efficiently disposed in a limited space of an opening that has an approximately elliptical or elongate-circular opening shape. The device includes a lead having a slit formed between a portion for bonding a wire to and a portion for mounting chips on, thereby to prevent extrusion of an adhesive and eliminate defective bonding.

Abstract: A semiconductor switching module includes a power semiconductor element that is embodied in planar technology. In at least one embodiment, the power semiconductor element is provided with a base layer, a copper layer, and at least one power semiconductor chip that is mounted on the copper layer, and another electrically conducting layer which covers at least one load terminal of the power semiconductor chip. According to at least one embodiment of the invention, devices are provided for safely connecting the load terminal to a load circuit. The devices are configured such that a contact area thereof presses in a planar manner onto the electrically conducting layer.

Abstract: The power semiconductor apparatus includes a resin package made up of a power semiconductor element and a control semiconductor element which are mounted on a main front surface of a lead frame and sealed with mold resin, a power terminal led out of the resin package and electrically connected to the power semiconductor element, a control terminal led out of the resin package and electrically connected to the control semiconductor element and a cylindrical case which is formed in a manner separable from the resin package and encloses the resin package, wherein the power terminal and the control terminal are led out of lead insertion slots formed in the case, and a part of the power terminal which is led out of the case is bent along an end face of the case.

Abstract: A temperature sensing system for a flange mounted device is provided. The temperature sensing system (100) can be comprised of a flexible wiring board (102). The temperature sensing system can be further comprised of a temperature sensing device (122) mounted to the flexible wiring board. The flexible wiring board can have one or more conductive traces (114a, 114b, 114c) disposed thereon. The conductive traces can form an electrical connection with the temperature sensing device. The temperature sensing system can also comprise a thermal pad directly connected to the temperature sensing device. The thermal pad can be formed of a thermal conductor. The thermal pad can also have a thermal contact surface. The thermal contact surface can be sized and shaped for direct physical contact with a portion of the device (302), wherein thermal energy is communicated directly from the thermal pad to the temperature sensing device. A method for sensing a temperature of a flange mounted device is also provided.

Abstract: A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads. In certain embodiments, one or more air gaps may be formed between the dielectric film and the active surface of the at least one power semiconductor chip. Methods for fabricating the semiconductor chip packaging structure are also disclosed.

Abstract: A family of emitter controlled thyristors employ plurality of control schemes for turning the thyristor an and off. In a first embodiment of the present invention a family of thyristors are disclosed all of which comprise a pair of MOS transistors, the first of which is connected in series with the thyristor and a second which provides a negative feedback to the thyristor gate. A negative voltage applied to the gate of the first MOS transistor causes the thyristor to turn on to conduct high currents. A zero to positive voltage applied to the first MOS gate causes the thyristor to turn off. The negative feedback insures that the thyristor only operates at its breakover boundaries of the latching condition with the NPN transistor portion of the thyristor operating in the active region. Under this condition, the anode voltage VA continues to increase without significant anode current increase.

Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.

Abstract: An object of the present invention is to provide a novel semiconductor mounting system having a semiconductor mounting member, a metal member and a joining layer joining the mounting and metal members, to improve the flatness of a mounting surface and to control the temperature on the surface of a semiconductor. A semiconductor mounting system 12 has a semiconductor mounting member 1, a metal member 7 and a joining layer 27 joining the mounting member 1 and metal member 7. The metal member 1 has a surface mounting a semiconductor. The adhesive sheet 4 has a resin matrix 11 and a filler 10 dispersed in the resin matrix 11.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an adhesive is formed on a dielectric and on an electrode, the adhesive is patterned exposing the electrode, and a programmable material is formed on the adhesive and on the electrode. In an aspect, a method is provided such that an adhesive is formed on a dielectric, an opening is formed through the dielectric exposing a contact formed on a substrate, and a programmable material is formed on the adhesive and on a portion of the contact. A conductor is formed on the programmable material and the contact transmits to a signal line.

Abstract: A semiconductor device having a supporting member that reduces a resonance phenomenon. A pair of reinforcing members is fixed on a gate drive substrate with spacers interposed there between and upright portions of the pair of reinforcing members are fastened with screws on a side wall of a cathode flange. A spacer is fixed on the gate drive substrate and a projection of the spacer is inserted in an engaging member fixed on the bottom of the cathode fin electrode and thus fixed on the bottom of the cathode fin electrode. The pair of upright portions as the first and second supporting points and the projection of the spacer as the third supporting point stably support the gate drive substrate on the cathode fin electrode without freedom of rotation at the three positions arranged to surround an opening.

Abstract: The present invention relates to power semiconductor devices and particularly to a power semiconductor device which contains a plurality of power semiconductor elements, and an object of the invention is to provide a power semiconductor device which is capable of reducing differences in impedance caused by differences in length among wire interconnections, facilitating the electric connection between the main circuit terminals and the outside, and lightening restrictions on the number and layout of the power semiconductor elements installed.

Abstract: A power semiconductor module comprises a metal base, plural wiring substrates provided on said the base, a first wiring substrate of the wiring substrates having a power circuit portion including a power semiconductor device, and substrate containing portions having a resin portion in which one of the wiring substrates is contained. The one of the wiring substrates is positioned in self-alignment on the metal substrate on the basis of an inner wall of the resin portion of the substrate-containing portion.

Abstract: A semiconductor device including (a) a base plate, (b) an insulation substrate including of an insulator plate with a front electrode and a back electrode bonded thereon and fixed onto the base plate by the back electrode, (c) a semiconductor element fastened onto the insulation substrate by the front electrode, (d) an insulating cover covering the semiconductor element, and (e) electrodes that are led from the semiconductor element to the outside of the insulating cover. The back electrode is larger than the insulator plate, and the base plate has a through hole that is smaller than the back electrode and larger than the insulator plate. The insulation substrate is positioned in the through hole and is fastened onto the back surface of the base plate by the periphery of the back electrode. The insulation substrate can make direct contact with a heat sink without the base plate intervening therebetween, and thereby thermal resistance between the semiconductor element and the heat sink is decreased.

Abstract: A connecting device for power semiconductor modules with compensation for mechanical stresses includes a sleeve connected to a substrate and having a region with a given very small diameter. A wire pin is provided for insertion into the region of the sleeve during operation to form an electrical connection for a board. The wire pin has a diameter greater than the given diameter for clamping the wire pin upon insertion in the region. Axial freedom of movement of the wire pin in the sleeve makes it possible to avoid mechanical stresses resulting from different material characteristics when a temperature change takes place.

Abstract: The present invention relates to a power transistor module for radio frequency applications, particularly for use in an amplifier stage in a radio base station or in a ground transmitter for TV or radio, wherein said power transistor module comprises a support plate, a power transistor chip arranged thereon, outer electrical connections projecting from the module for external connection and inner electrical connections connected between said transistor chip and said outer connections, at least one of said inner electrical connections comprising a first conductor pattern arranged on a flexible foil. The invention further comprises a power amplifier comprising said module, a method in the fabrication of said module, a method in the fabrication of a power amplifier, where said module is electrically connected to a circuit board mounted at a heat sink and to be mounted at said heat sink, and finally to a power amplifier manufactured according to the method.

Abstract: Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.

Abstract: A power semiconductor switching device comprises a mounting board (110) on which a reverse bias driving circuit (20) for applying a reverse bias between the control electrode and one of two main electrodes of a GTO element (11) housed in a flat package is contained. The mounting board (110) has a through hole through which the main electrode of the GTO element (11) penetrates so that the flat package is located in the proximity of the through hole and the perimeter of the through hole partially surrounds the flat package, and a conducting member formed on one surface of the mounting board (110) and electrically connected to the control electrode of the GTO element (11).

Abstract: The top-side (n-type) electrode and bottom-side (p-type) electrode of a Si chip with a p-n junction are pressed against a Cu cathode electrode and a Cu anode electrode via Mo plates respectively, thereby establishing electrical connection. The inner wall of a case is round and the Si chip is almost square. The top of the case is covered with ceramic, for example. A washer is a compression member. A chip frame holds the Si chip and Mo plates in compression positions and simultaneously determines their locations within the case. Specifically, the side face of the Si chip is not flush with the side face of each of the Mo plates. This enables the chip frame to make the creepage distance longer. Since the chip frame is a single chip frame without any joint, the creepage distance between the anode and cathode electrodes is defined by part of the chip frame that faces part of the surface of the Si chip and parts of the surfaces of the Mo plates sandwiching the Si chip between them.

Abstract: A channel layer of n-type GaAs doped with Si as an impurity is formed on a GaAs semiinsulating substrate. A gate electrode of, for example, aluminum is formed on the channel layer. The gate electrode is in Schottky-contact with channel layer. Formed on opposite sides of the gate electrode on the channel layer are drain- and source side electric field relaxation layers of n-type In.sub.x G.sub.1-x As doped with impurities. Each electric field relaxation layer substantially produces a potential difference at its lateral edge portion by an electric current flowing across the lateral edge portion. A WSi drain electrode is formed on the drain-side electric field relaxation layer. A WSi source electrode is formed on the source-side electric field relaxation layer.

Abstract: An optically-triggered silicon controlled rectifier (SCR) device (21) mounted on a lead frame (34). The SCR device contains a cathode layer (24), an optical gate or control layer (23), and an anode layer (31) formed on a semiconductor substrate (22). The device is soldered onto a pedestal (33) formed on the lead frame. To connect the device to the lead frame, solder is deposited upon the anode layer and the solder fixes the anode layer to the pedestal on the lead frame. The pedestal may be formed by etching or stamping a depression (35) in the lead frame. The device is centered on the pedestal such that the edges of the device are located adjacent the depression, and are spaced from the lead frame.

Abstract: A semiconductor component comprises a semiconductor body that has its underside secured on a metallic substrate and is joined at its upper side to an auxiliary member composed of a material having great thermal conductivity and which serves as a heat buffer. This auxiliary member increases the loadability of the semiconductor component with respect to additional, thermal stressing pulses.